JP5320351B2 - Power converter failure monitoring device - Google Patents

Description

  The present invention relates to a failure monitor device for a power converter that monitors a failure of a power converter that converts direct current to alternating current or alternating current to direct current.

  Power converters that use multiple switching elements are equipped with a fault monitoring device that monitors the status of analog monitor signals such as gate pulses, element currents, and voltages for failure analysis of each switching element and monitors faults. ing. When a failure occurs, these gate pulses and analog monitor signals are displayed on, for example, a personal computer to analyze the operation at the time of the failure.

  In such a power converter failure monitoring device, the gate pulse of the switching element needs a resolution of several μs, while the resolution of the analog monitor signal (voltage, current, etc.) is asynchronous with the gate pulse and the signal changes. In general, a method of sampling with a resolution of several hundred μs is common.

  In this way, in a device with a sample timing scale that is several orders of magnitude, the capacity of the monitor memory increases or the display is not accurate due to the sampling difference between the gate pulse and the analog monitor signal. Was spending.

  As an example of shortening the time for investigating the cause of failure, the present applicant has previously proposed the following. That is, a clock generator that outputs a pulse with a fixed period, a circuit that detects a change point of the gate pulse based on the timing of the clock, a circuit that detects an abnormal pattern of the gate pulse at the change point of the gate pulse, and an external A means for outputting a pulse trigger based on a failure detection signal and an abnormal pattern detection signal from, a time counter for generating time data when the pulse trigger is output, and a power synchronized with the time when the pulse trigger is output Manages analog monitor signals (analog monitor data) such as converter DC input current or voltage or output current and time data, and addresses that link the analog monitor signals (data) and time data during monitor playback Address counters and microcomputers that control these operations The have, to sample and concentrate the analog monitoring signal when the power converter abnormality, a malfunction monitoring apparatus to shorten the elucidation of fault cause time (see Patent Document 1).

According to such a failure monitoring device, the change in the analog monitor signal synchronized with the gate pulse can be monitored, so that the detailed state of the analog monitor signal at the time of abnormality such as when a gate breakage accident occurs can be confirmed. , Cause pursuit time can be shortened.
However, in power converters that use multiple switching elements, even if the gate pulses supplied to the switching elements are in a normal combination, a failure of the switching element may occur. Therefore, it is necessary to consider the relationship between the gate pulse to the switching element and the feedback signal indicating the state of the corresponding element.

Patent No. 3793909

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a failure monitoring device capable of investigating the cause of a failure when the switching element is in an abnormal state and reducing the time taken for the countermeasure.

In order to achieve the above object, the present invention, in addition to sampling the analog monitor signal synchronized with the gate pulse at the time of abnormality, in the period when the feedback signal corresponding to the gate pulse supplied to the switching element returns, This means that only a large amount of analog monitor data required for failure analysis can be monitored.
Alternatively, the analog monitor signal is sampled during a period in which the gate pulse signal and the feedback signal do not match.
Specifically, for example, a clock generator that outputs a pulse with a fixed period, a circuit that detects a change point of a gate pulse and a feedback signal based on the timing of the clock, and an abnormal pattern of the gate pulse and the feedback signal are detected. A circuit that outputs a pulse trigger based on an external failure detection signal and an abnormal pattern detection signal, a time counter that generates time data when the pulse trigger is output, and a pulse trigger that is output, Synchronously with this, a monitor memory for storing analog monitor data such as DC input current or voltage or output current of the power converter and time data, and an address counter for managing addresses for linking the analog monitor data and time data during monitor reproduction And a microcomputer that controls these operations. Has over data, a gate pulse is supplied to the switching element, to be mismatched periods of the feedback signal from the switching element, characterized in that a means for outputting a pulse trigger.

  According to the present invention, when the switching element is in an abnormal state, the analog monitor signal can be collected intensively in synchronization with the gate pulse, so that the change of the analog monitor signal when the power converter is abnormal necessary for failure analysis is reduced. It becomes accurate, and the time taken to track down and deal with the cause of failure can be reduced.

FIG. 1 is a diagram illustrating a failure monitor apparatus for a power converter according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram of hardware blocks of the failure monitoring apparatus according to the first embodiment of this invention. FIG. 3 is an explanatory diagram illustrating a structure of analog monitor data of the failure monitoring apparatus according to the first embodiment of the present invention. 4A to 4H are explanatory diagrams illustrating an example of an analog monitor signal by the failure monitoring apparatus according to the first embodiment of the present invention. 5 (a), (i), (j), and (e) to (h) show another example of the analog monitor signal by the failure monitoring apparatus according to the first embodiment of the present invention, and the power converter operates normally. It is explanatory drawing in the case of being. 6 (a), (i), (j), and (e) to (h) show another example of the analog monitor signal by the failure monitoring apparatus according to the first embodiment of the present invention, and the power converter operates abnormally. It is explanatory drawing in the case of being.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram illustrating a failure monitor apparatus for a power converter according to a first embodiment of the present invention. In FIG. 1, an inverter that converts direct current to alternating current is described as the power converter, but the target power converter may be a static inverter (SIV) or a converter that converts alternating current to direct current.

  In FIG. 1, in a three-phase power converter, two switching elements (for example, IGBT: switching element such as an insulated gate bipolar transistor) 4 connected in series between DC power supplies 6 are three-phased (U phase, V phase, W As a phase), the switching element 4 of each phase is connected from the serial connection destination to the AC motor 5 serving as a load. The PWM modulation signal 101 output from the PWM generator 2 of each switching element 4 is input to the gate drive 3. The gate drive 3 is operated by this PWM modulation signal, and the output signal is applied to the gate of the switching element 4.

  Further, the PWM modulation signal 101 is applied to the failure monitor device 1. Here, since the PWM modulation signal 101 and the output signal of the gate drive 3 have the same pulse timing except for the voltage level, the PWM modulation signal 101 is referred to as a gate pulse signal in this embodiment. Further, in the gate drive 3, since the on / off state of the switching element 4 can be determined by a transistor directly connected to the gate of the switching element 4, a signal output from the inside of the gate drive 3 (see 102 in FIG. 1) The feedback signal of the switching element 4 is used. Reference numeral 100 denotes a signal for supplying a gate stop signal to the PWM generator 2 and controlling the PWM generator when an abnormality occurs in the power converter.

The failure monitor device 1 of this embodiment includes a gate pulse signal 101 and a feedback signal 102, an analog monitor signal 24 such as an output current and a DC voltage of the power converter, and a failure detection from a control device of the power converter (not shown). A signal is input. The output current is detected from the output stage of the power converter by a current detector (CT: Current Transformer), and the DC voltage is detected from the DC power supply 6 by a voltage detector (PT: Potential Transformer).
In FIG. 1, for the sake of convenience, only the failure monitoring apparatus for one switching element 4 is described, but it goes without saying that it is performed for all elements.

Next, details of the failure monitoring apparatus 1 will be described. FIG. 2 is a hardware block diagram of the failure monitoring apparatus 1.
In FIG. 2, 7 is a clock generator that outputs a clock pulse of a fixed period, 8 is a change inspection that detects change points of a PWM signal (gate pulse signal) and a feedback signal based on the clock timing of the clock generator 7. An output circuit 9 is an abnormal pattern detection circuit for detecting an abnormal pattern of the gate pulse signal and the feedback signal.

Reference numeral 10 denotes a free-run timer, and the timer 10 constitutes a time counter that generates time data when a pulse trigger 23 described later is output.
Reference numeral 11 denotes an A / D converter that receives an analog signal composed of a current CT and a voltage PT of the power converter and converts it into a digital signal. Reference numeral 12 denotes an address counter. An address for linking the analog monitor data obtained by converting the monitor signal 24 into a digital signal by the A / D converter 11 and the time data is managed.
Reference numeral 13 denotes a monitor memory. The monitor memory 13 includes an area in which hardware is written (page 1-7) and an area in which software is written (page 8) as shown in FIG. 3, and the pulse trigger is output. At the same time, the analog monitor signal (analog monitor data) such as the DC input current or voltage or output current of the power converter and the time data are stored in the area (page 1), for example.
Reference numeral 14 denotes a microcomputer, and the microcomputer 14 controls these operations. Reference numeral 15 denotes a page register. Thick lines indicate an address bus and data bus, and thin lines indicate a control signal line.

21, 22, 23, 30 and 31 indicate outputs of the plurality of logic elements 101 to 107 constituting the logic circuit.
Here, in the logic elements OR 101, AND 102, and OR 103, a fault detection signal from a control device (not shown), for example, an abnormal current flows in the current detector CT. A means for outputting a pulse trigger 22 (refer to FIG. 4 and FIG. 5) based on the failure detection signal that makes a failure upon detection of the abnormal current and the abnormal pattern detection signal constitutes a logic element EXOR (exclusive OR) 106. AND (OR) 107 and OR (OR) 103 constitute a means for comparing the gate pulse to the switching element and a feedback signal corresponding to the gate pulse to detect a mismatch period. The logic elements OR (or) 103 and 104 and AND (and) 105 are involved in both means.

  In FIG. 3, pages 1 to 7 are shown as areas to be written by the hardware, and the first hard data (for example, the gate pulse signal 101 and the feedback signal 102) to the seventh hard data are written for each page. Here, time data and analog monitor data (for example, analog monitor signal 24) are written in the addresses of the respective pages. Further, page 8 is shown as an area written by the software, and this page has first to seventh failure software data areas. The hardware address counter value at the time of failure and the failure occurrence time as each failure software data. Write data.

  Subsequently, the operation of the failure monitoring apparatus 1 will be described. The microcomputer 14 sets a page (page address) for writing analog monitor data to the monitor memory 13 in the page register 15 and then outputs monitor start data. On the other hand, the clock generator 7 outputs a clock pulse having a cycle sufficiently shorter than the pulse width of the gate pulse signal for edge detection. In this embodiment, the switching frequency of the switching element 4 is set to 1.25 MHz with respect to several kHz. With this clock frequency, an edge of 1 μs can be detected.

  When there is no failure detection signal, that is, when an abnormal pattern is not detected, the abnormal pattern trigger 21 is not output (output of the AND 102), and the pulse trigger 22 is not output (output of the OR 103). The address counter 12 is periodically operated by a timer trigger 23 (output of the timer 10) output from the timer 10, and the output (analog monitor data 1-n) of the A / D converter 11 at the address (page register value + address counter value). ) And time data 1-n (relative time) output by the timer 10 at that time are stored in the page 1 as shown in FIG. Thereafter, when a state in which no failure is detected continues, this operation is repeated, and previously written data is overwritten.

  Next, when there is a failure detection signal or an abnormal pattern of the gate pulse, the abnormal pattern detection signal 25 of the abnormal pattern detection circuit 9 is detected when the change point detection circuit 8 detects the change point of the gate pulse signal and the feedback signal. If there is a failure detection signal from a power converter control device (not shown), an abnormal pattern trigger 21 is output (output of AND 102), the address counter 12 is activated at each change point of the gate pulse, and the page register value + The output of the A / D converter 11 (analog monitor data) and the time data (relative time) output by the timer 10 at that time are stored as management data in the page 8 as shown in FIG. .

  Upon receiving the failure detection signal, the microcomputer 14 first stores the management data of page 8 in FIG. 3, that is, the address counter value of the hardware data at the time of failure occurrence and the failure occurrence time data in the monitor memory 13. The output of the monitor start signal is stopped within a predetermined time, and the update of the current data of the hardware and software is stopped. After incrementing the value of the page register 15 and switching the page of the monitor memory 13 stored in the hardware to page 2 (second hard data) and switching the software writing area to the second fault soft data, The monitoring operation starts again.

  Hereinafter, similarly, when there is a failure detection, the value of the page register 15 is incremented, and the pages of the monitor memory 13 in which the hardware sequentially stores the analog monitor data are changed to pages 3 to 7 (third to seventh hard data). ) And the software writing area is switched to the third to seventh failure software data, and then the monitoring operation is started again.

  4A to 4H show an abnormal pattern detection signal (FIG. 4D) between the two gate pulse signals 1 (see FIG. 4A) and the gate pulse signal 2 (see FIG. 4B). An example of a monitoring result when the switching element 4 has failed is shown. When the abnormal pattern trigger 21 is output (output of the AND 102), the pulse trigger 22 (see FIG. 4 (e)) is output (output of the OR 103) at each change point of the gate pulse signal at that time, and the analog monitor at the time of abnormality is output. Data (see FIG. 4G) is collected in synchronization with the gate pulse signal 1 and stored in the monitor memory 13. If this data is reproduced, the reproduced data can be reproduced in substantially the same manner as the analog monitor data (see FIG. 4 (g)) as shown by the solid line in FIG. 4 (h), and is shown by the one-dot chain line in FIG. 4 (h). It can be seen that there is a great difference from the reproduction data of the analog monitor data only for the timer trigger 23 (the output of the timer 10, see FIG. 4F).

  In this embodiment, analog monitor data can be collected intensively and stored in the monitor memory 13 before an abnormal pattern is detected or a failure detection signal is generated. That is, as shown in FIG. 2, the period of mismatch between the gate pulse and the feedback signal of the gate pulse is detected by the EXOR 106, and the clock frequency of the clock generator 7 is output during the period when the mismatch signal 30 (output of the EXOR 106) is output. Thus, the mismatch detection trigger 31 (output of the AND 107) is generated. This is combined with the above-described abnormal pattern trigger 21 (output of AND102) to generate a pulse trigger 22 (output of OR103).

  FIG. 5 shows an operation example. The feedback signal of the gate pulse signal 1 (see FIG. 5 (i)) returns from the gate driver 3 with a time delay. Even when the switching element 4 is operating normally, this delay time occurs. Therefore, a mismatch period between the gate pulse signal 1 and the feedback signal of the gate pulse signal 1 is detected, and the pulse trigger 22 (output of the OR103, the period of the mismatch signal 30 (output of the EXOR 106, see FIG. 5 (j)) is output. 5 (e)) is generated, and analog monitor data (see FIG. 5 (g)) is intensively collected and stored in the monitor memory 13. A power converter control device (not shown) generates a failure detection signal according to the delay time of the feedback signal. However, considering the operation variation in the gate driver 3 circuit, it is regarded as normal operation even if it is delayed by about 10 μs in order to avoid malfunction. . If this data is reproduced, the reproduced data can be reproduced in substantially the same manner as the analog monitor data (see FIG. 5G) as indicated by the solid line in FIG.

  Therefore, even if concentrated in the mismatch period as shown in FIG. 5, the influence on the monitor memory 13 is small. Since the normal operation is performed even at 10 μs, for example, even if the clock for generating the mismatch detection trigger 31 (output of the AND 107) is fixed to 5 μs and sampled twice in the mismatch period, the timer trigger 23 (timer output) is a number as described above. This is 100 μs (200 μs in this embodiment), and there is no problem in terms of resolution.

  FIG. 6 shows an example in which the feedback signal is abnormal and the pattern of the gate pulse signal 1 does not return. The failure detection signal is generated after at least 10 μs elapse of the mismatch signal 30 (output of the EXOR 106). In FIG. 6, analog monitor data is intensively collected and stored in the monitor memory 13 before failure detection. Therefore, if this data is reproduced, as shown by the solid line in FIG. 6 (h), the analog monitor data before failure detection (see FIG. 6 (g)) can be reproduced almost faithfully. It can be seen that there is a great difference from the reproduction data of the analog monitor data of only the timer trigger 23 (the output of the timer 10) indicated by a one-dot chain line. This operation is the same when the feedback signal returns with a pattern in which no gate pulse signal is generated.

  As described above, according to the failure monitoring apparatus of the present embodiment, the analog monitor signal is accurately reproduced, and at the same time, the time when the failure detection signal is generated, the time when the monitor signal is abnormal, and before the occurrence of the abnormality From the observation result of the analog monitor signal, it is possible to quickly determine what has occurred, and then take appropriate measures.

DESCRIPTION OF SYMBOLS 1 Failure monitor apparatus 2 PWM production | generation part 3 Gate drive 4 Switching element 5 AC motor 6 DC power supply 7 Clock generator 8 Change point detection circuit 9 Abnormal pattern detection circuit 10 Timer 11 A / D converter 12 Address counter 13 Monitor memory 14 Micro Computer 15 Page register 20 Pulse change point 21 Abnormal pattern trigger 22 Pulse trigger 23 Timer trigger 24 Analog monitor signal (analog monitor data)
25 Abnormal pattern detection signal 30 Mismatch signal 31 Mismatch detection trigger

Claims (4)

In a power converter failure monitoring device for driving a plurality of switching elements each with a predetermined gate pulse,
A clock generator for outputting a pulse having a constant period; a circuit for detecting a change point of the gate pulse signal and the feedback signal based on the timing of the clock; and a circuit for detecting an abnormal pattern of the gate pulse signal and the feedback signal. A means for outputting a pulse trigger based on a failure detection signal from the power converter and the abnormal pattern detection signal; a time counter for generating time data when the pulse trigger is output; and the pulse trigger is output. In synchronism therewith, the analog monitor data of the analog monitor signal such as the DC input current or voltage or output current of the power converter, the monitor memory for storing the time data, the analog monitor data and the time data at the time of monitor reproduction Address cow that manages the address to link Comprising a motor, a microcomputer for controlling these operations,
A means for comparing the gate pulse to the switching element and a feedback signal corresponding to the gate pulse to detect a mismatch period;
A fault monitor apparatus for a power converter, wherein the analog monitor signal is regenerated based on the output of the mismatch period by the mismatch period detection means and the output of the pulse trigger output means.   2. The failure monitor apparatus for a power converter according to claim 1, wherein the means for detecting the mismatch period and the pulse trigger output means are a PWM generator for outputting the gate pulse signal and a gate drive for outputting the feedback signal. And a fault monitoring device for a power converter comprising a plurality of logic elements arranged between the respective units.   3. The failure monitor apparatus for a power converter according to claim 2, wherein the plurality of logic elements are an output signal of the abnormal pattern detection circuit, a first OR element of the failure detection signal, and an output of the first OR element. A first AND element of the signal and the output signal of the change point detection circuit; an exclusive OR element of the gate pulse and the feedback signal; an output signal of the exclusive OR element; and a second of the output signal of the clock generator. An AND element, a second OR element of the output signal of the first AND element, an output signal of the second AND element, a third OR element of the output of the timer and the output signal of the second OR element, and the micro A fault monitor apparatus for a power converter comprising a third AND element of a monitor start signal of a computer and an output signal of the third OR element. In a failure monitor device for a power converter that drives a switching element with a predetermined gate pulse signal,
A clock generator that outputs pulses with a constant period;
A circuit that detects a change point of a gate pulse signal and a feedback signal indicating an on / off state of the switching element based on the timing of the clock generator;
Means for comparing the gate pulse signal and the feedback signal to detect a mismatch period of both signals;
Pulse trigger generation means for generating a pulse trigger based on a pulse output from the clock generator during a mismatch period between the gate pulse signal and the feedback signal;
A monitor memory for recording analog monitor data of an analog monitor signal such as a DC input current or a voltage or an output current of the power converter in synchronization with the pulse trigger; .

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