JP5316131B2 - Data transfer system and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent latency accompanying packet transfer from occurring and to provide efficient data transfer. <P>SOLUTION: A data transfer system is composed of a master device and a target device which can transfer data to the master device. The master device has a transmission means which transmits a data transfer request to the target device after transmitting information giving the amount of data which the master device can receive. The target device has: a measurement means which measures a data transfer rate in accordance with the data transfer request transmitted from the transmission means of the master device; and a transmission means which transmits a restriction request for restricting the amount of the data transfer request to the master device when the value of the data transfer rate measured by the measurement means is a predetermined value or more. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to the field of data transfer systems and data transfer methods.

  In a data communication system in which a plurality of devices (data communication apparatuses) are connected via a common communication path and perform data communication with each other, contention occurs when different types of traffic perform data transfer using the same communication path. There is a problem that communication quality (data transfer rate and continuity) required for each traffic cannot be obtained.

  In order to improve such a problem, a server system in which a plurality of servers are connected by a computer network such as Ethernet (registered trademark) is provided with a communication load measuring means for measuring the communication load of the computer network. A method has been proposed in which the amount of information transferred is increased or decreased accordingly (see, for example, Patent Document 1).

  In addition, a method has been proposed in which a communication device (node) includes a traffic observation unit and traffic information of each node obtained by observation is used for data transfer route selection (see, for example, Patent Document 2).

  In addition, a method of providing a plurality of servers for processing data and distributing processing and data communication paths has been proposed (see, for example, Patent Document 3).

  By the way, in recent years, high-speed serial transmission lines that have transmission speeds exceeding several Gbps and can transfer data at a much higher speed than Ethernet (registered trademark) have been put into practical use. Local I / O (In / Out) standards are spreading. For this reason, data communication networks within LSI chips, between chips, and between boards have come to be used for embedded electronic devices by packet data communication using serial transmission lines and switches, similar to computer networks. It was.

  Typically, PCI Express (hereinafter referred to as PCIe), which is a standard for high-speed serial communication and is widely used as a local IO for PCs, is known. In the data transfer method by PCIe, in order to reduce data packet contention, a credit-based credit (Credit) base is used between PCIe links (between own device and devices connected directly by point-to-point / hereinafter simply referred to as links). Flow control is performed. This is a mechanism in which an overflow or underflow does not occur by checking the empty state of the buffer on the receiving side before starting the data transfer on the transmitting side.

  Specifically, the target device (receiving side) that receives a request at the time of link initialization is the amount of requests to the master device (transmitting side) that issues a request for each request type, such as Memory Write or Memory Read. The credit information (including the credit value) indicating whether or not can be received is notified. The notification is notified by a control packet called data link layer packet / DLLP (Init FC). Note that in a device compliant with the PCIe standard, a reception buffer is mounted on the reception port, and the above-described credit value generally corresponds to the free capacity of the reception buffer of the target device (or switch). The master device transmits a packet only when there is a certain remaining buffer capacity of the target device based on the notified credit information. Then, the master device subtracts the size of the packet transmitted by itself from the notified credit value. When the master device has used up the credit value of the target device, the master device performs an operation to pause the request. On the other hand, every time the transfer process of the received packet is completed, the target device notifies the master device of the amount of request (additional credit value) that can be newly received by DLLP (Update FC). The master device can issue a new request for the credit value that can be received by the target device again. With such credit-based flow control, the transmitting side does not transmit data exceeding the buffer capacity of the receiving side, so no retransmission operation of packet transfer occurs, and the data transmission efficiency of the communication path can be improved. It can be done.

  On the other hand, when the data transmission speed is increased at the master device, the credit value notified at the master device (transmission side) becomes zero before the additional credit value is received from the target device. In this case, the master device cannot transmit data to the target device. After receiving the DLLP (Update FC) from the target device (reception side) and receiving a notification that the buffer capacity has been secured, the master device can transmit data to the target device. It should be noted that the target device has run out of packet buffer processing, etc., so that the target device has no available reception buffer capacity, that is, the master device is not notified of the additional credit value, and the master device has used up all of the notified credit value. The state is expressed as “credit depletion” below.

  By the way, even in a data transfer system using PCIe, there is a case where the influence of stopping the data transfer of a certain traffic due to the influence of packet competition may stop the transfer of other traffic. FIG. 1 is an example of a diagram showing a data communication system configured by PCI Expres. The figure shows a data communication system in which four master devices (M1-M4) are connected to two target devices (T1, T2) via three switches (SW1-SW3) using the PCIe standard. Has been. In the figure, master devices M1 and M3 generate high-priority traffic that cannot be interrupted even for a short time, and M2 and M4 generate low-priority traffic. M2 and M4 issue requests to T1, and M1 and M3 issue requests to T2.

  Since the flow control of PCIe is control between links (point-to-point), if a delay occurs in data reception processing at T1, credit depletion first occurs at link 1 between T1 and SW2, In SW2 connected to T1, packet transfer addressed to port A connected to T1 stops. When the transfer of the packet addressed to T1 of SW2 stops, the depletion of credit also occurs in the link 2 between SW1 and SW2, and the transfer of the packet addressed to SW2 stops. Although the data transfer to SW2 is being performed, the packet transfer addressed to port A connected to T1 is stopped, so the buffer capacity of SW2 eventually becomes saturated, and the link between SW1 and SW2 Even in the case of 2, the depletion of credit occurs. At this time, since the traffic from M1 to T2 also passes through the link 2 between SW1 and SW2, the depletion of credit occurs in the link 3 between SW1 and M1, and the traffic of M1 is also stopped. Similarly, the depletion of the credit of link 1 between T1 and SW2 also stops the traffic via SW3, and also stops the traffic from M3 to T2. As described above, when the output port of the switch is shared, the influence of stopping the data transfer of a certain traffic may stop the transfer of other traffic. In other words, the suspension of the transfer of the low priority traffic affects the transfer of the high priority traffic.

  For this reason, the ASI (Advanced Switching Interconnect) standard derived from PCIe defines SBFC (Status Based Flow Control) as a more advanced flow control method than the PCIe standard. According to SBFC, when a credit shortage occurs in an output destination port, the switch device notifies the master device connected to the input port of the switch device of the credit shortage information. The notification allows the master device to detect a shortage of credit in the 1 Hop destination port, so that an operation for temporarily suspending a request addressed to the port can be performed to prevent influence on other traffic transfers.

  As described above, high-speed serial transmission lines capable of high-speed data transfer have been put into practical use, and data communication networks within LSI chips, between chips, and between boards by packet data communication using serial transmission lines and switches. However, it has also been used in electronic devices for embedded applications. When using a high-speed serial transmission line for embedded electronic equipment, compared to the data transfer quality of conventional computer networks, there are strict restrictions on the data communication rate in the short term and the latency required for packet transfer. Omissions may not be allowed.

  As an example of this, an example of image data transfer restriction assuming image data transfer of a copying machine will be described. FIG. 2 is an example of a diagram schematically showing a configuration of image data. As shown in the figure, the image data is constituted by a two-dimensional array in the main scanning direction and the sub-scanning direction. The image data transfer of the plotter or scanner is executed by synchronous transfer in which the process of transferring the pixel data in the main scanning direction in a predetermined time period is repeated in the sub-scanning direction. This is because the data transfer synchronization constraint is determined by the mechanical drive conditions. In particular, in the plotter using the electrophotographic process, the heavy photoconductor drum and the paper transport mechanism are driven at high speed. The speed cannot be changed. Therefore, it is necessary to control the data transfer amount at a timing synchronized with the driving speed of the mechanism.

FIG. 3 is an example of a diagram schematically showing a transaction in image data transfer. As shown in the figure, data transfer is performed by sub-scanning as a transaction consisting of a plurality of (n) packet groups line by line with a plurality of pixel data as one packet data for each line in the main scanning direction. It must be transferred in synchronism with the speed at which the image is scanned in the direction. If the allowable time per transaction is called “one line period”, one line period of the plotter is determined by the paper feed speed and the print image resolution, and one line period of the scanner is determined by the moving speed of the scanner unit and the reading resolution. Is done. The calculation formula of a line period is shown.
Plotter 1 line cycle (s) = 1 / {[paper feed speed (mm / s)] x [number of pixels per mm]}
Scanner 1 line cycle (s) = 1 / {[Head moving speed (mm / s)] x [Number of pixels per 1 mm]}
Specifically, an example of calculating the plotter line period is shown. To simplify the calculation, it is assumed that the printing resolution of the plotter is 50 dots / mm for both main scanning and sub-scanning, and the number of bits for each pixel is 2 bits assuming CMYK color printing. Further, assuming that the document size is A4 in the horizontal direction, the main scanning direction is 297 mm × the sub-scanning direction is 210 mm. The printing speed is assumed to be 60 sheets. At this time, since the printing time per sheet is 1 second, the paper feed speed in the sub-scanning direction is 210 mm / s. When calculating the plotter 1 line period,
1 / (210 × 50) = 0.000095 s = 95μs (microseconds)
It becomes. The number of pixels per color in the main scanning direction is
297mm × 50dot / mm = 14850 dot
Thus, the data amount is 14850 dots × 2 bits / 8 = 3713 bytes. Furthermore, when calculating the data amount for four colors,
3713Byte x 4 colors = 14850Byte
In other words, the transfer of the image data needs to be completed in 14850 bytes in 95 μs. The data transfer rate at this time is 14850 Byte / 0.000095s = about 156 MB / s.
When sending one line of data, assuming that it is divided into 128-byte packets and transferred,
14850 Byte / 128 Byte = 117, and it is necessary to satisfy the extremely strict data transfer restriction that 117 128 Byte data packets must be transferred to 95 μs within one line period. In addition, image data communication in a copier is a process that does not need to be synchronized with the line cycle, for example, data transfer in image processing, because the image is finally printed on paper or stored in an image file. There is a very severe restriction that data loss and quality degradation due to compression are not allowed at all, as in video and audio streaming.

  In the invention described in Patent Document 1, load measurement means, load information calculation means, and communication load determination means are provided on the computer network, and from when a high load state is detected until it is reflected in actual traffic adjustment. Both require time from sec to mmsec. Accordingly, the communication load cannot be adjusted in a communication system for an embedded device that requires a short latency in units of μsec to nsec, such as transfer in synchronization with the line cycle of the copying machine described above. Also, increasing or decreasing the amount of information transferred according to the size of the communication load cannot be applied when the amount of information is fixed as in a print image.

  Further, in the inventions described in Patent Document 2 and Patent Document 3, the traffic management means is centrally managed at one place, and the latency until the traffic information of each place in the network is reflected in the traffic adjustment is long for embedded device applications. There is a problem of becoming too much. Furthermore, in the invention described in Patent Document 2, it is necessary to provide the traffic monitoring means in all connection nodes of the network, and there is a problem that the scale of the entire circuit constituting the network increases and the cost increases.

  In addition, in the conventional data transfer system based on PCIe, traffic arbitration between links is processed with a short latency by the flow control method. However, as described above, credit due to data processing delay at one link of the data communication network, etc. When depletion occurs, data transfer stops to other traffic sharing the route with the traffic via the link, and there is a problem that sufficient data transfer rate cannot be obtained with high priority traffic. .

  In addition, when an ASI standard switch device is used, the credit shortage information is notified to the device of 1 Hop destination, so this problem can be alleviated, but if the number of stages through the switch increases, the destination port It takes a long time for the credit shortage information to reach the master device. In addition, general ASI (same for PCIe) switch devices have an internal buffer of about a few kilobytes to 10 kilobytes. Therefore, the latency deterioration phenomenon caused by waiting for the previous request stored in the internal buffer is more It will appear prominently. When the time allowed for one line of data transfer is several tens of microseconds as in the case of the image data transfer of the above-described copying machine, this latency deterioration phenomenon remarkably lowers the printing and scanning performance. In this way, in the SBFC of the ASI standard, credit depletion information is transmitted to each device in order, so that latency occurs before the request issuance from the master device is stopped, and there are other effects due to the influence of the buffer on the communication path. There is a problem that the latency of the request from the device is deteriorated. In addition, there is a problem that the circuit implementation scale of the communication device of the switch device corresponding to the ASI standard, each master device, and the target device is much larger than the PCIe and the cost is high.

  In view of the above-described problems, an object of the present invention is to provide a data transfer system and a data transfer method for suppressing the generation of latency required for packet transfer and realizing efficient data transfer.

In order to solve the above problems, a data transfer system according to the present invention is a data transfer system including a target device and a master device capable of transferring data to the target device, and the master device is connected to the target device. After receiving information indicating the amount of data that can be received by the target device, the data transfer is performed when a transmission unit that transmits a data transfer request to the target device and a restriction request transmitted from the transmission unit of the target device are received. Control means for limiting the amount of requests, and the target device measures a data transfer rate based on the data transfer request transmitted from the transmission means of the master device, and the measurement means Total Transmission means for transmitting a restriction request for restricting the amount of the data transfer request to all the master devices included in the data transfer system when the value of the data transfer rate is greater than or equal to a predetermined value. All the master devices have information indicating whether to comply with the restriction request, and when receiving the restriction request transmitted from the transmission means, the control means transfers data to the target device according to the information. It is a control means for limiting the amount of requests.

  In addition, what applied the arbitrary combination of the component of this invention, expression, or a component to a method, an apparatus, a system, a computer program, a recording medium, etc. is also effective as an aspect of this invention.

  ADVANTAGE OF THE INVENTION According to this invention, generation | occurrence | production of the latency required for packet transfer can be suppressed, and the data transfer system and data transfer method which implement | achieve efficient data transfer can be provided.

It is a figure which shows an example of the data communication system comprised by PCI Express. It is a figure which shows an example of an image data structure typically. It is a figure which shows typically an example of the transaction in image data transfer. It is a figure which shows an example of the general structure of a PCI Express system. It is a figure which shows an example of a structure of the PCI Express system in this embodiment. It is a figure which shows an example of the target device structure which concerns on this embodiment. It is a figure which shows an example of the master device structure which concerns on this embodiment. It is a figure which shows an example of a structure of the PCI Express system explaining operation | movement of a master device and a target device. It is a flowchart explaining an example of operation | movement of a target device. It is a flowchart explaining an example of operation | movement of a master device. It is a figure which shows an example of a structure of the PCI Express system explaining operation | movement of the master device by this modification, and a target device. It is a figure which shows an example of the target device structure which concerns on this embodiment. 1 is a diagram illustrating an example of a configuration in which a PCI Express system according to the present invention is applied to an MFP. FIG. It is a figure which shows an example of the data communication system comprised by ASI. It is a figure which shows an example of SW1 typically.

  DESCRIPTION OF EMBODIMENTS Embodiments for carrying out the present invention will be described in each embodiment with reference to the drawings. Hereinafter, the present invention will be described using a data transfer system based on PCIe as an example.

[Embodiment 1]
(System configuration)
FIG. 4 is an example of a diagram illustrating a general configuration of the PCI Express system. The PCIe graphics 113 is connected to the root complex 112 to which the CPU 110 and the memory 111 are connected by the PCIe 114a, and the switch 117a in which the endpoint 115a and the legacy endpoint 116a are connected by the PCIe 114b is connected by the PCIe 114c. The tree structure (tree structure) in which the switch 117b in which the endpoint 115b and the legacy endpoint 116b are connected by the PCIe 114d, and the PCI bridge 119 in which the PCI bus slot 118 is connected in the switch 117c in which the PCIe 114e is connected in is connected through the PCIe 114f. It is said that.

  FIG. 5 is an example of a diagram illustrating a configuration of the PCI Express system according to the present embodiment. A data communication system is shown in which four master devices (M1-M4) are connected to two target devices (T1, T2) via three switches (SW1-SW3) using the PCIe standard. . If the general configuration of the PCI Express system in FIG. 4 is associated with each device, for example, SW2 is the root complex 112, SW1 is the switch 117c, SW3 is the switch 117a, T1 (or T2) is the memory 111, and M1-M4 is the end. Each corresponds to the point 115b (or the legacy endpoint 116b).

(Flow control)
Next, flow control (flow control) defined by PCIe will be described in a confirming manner. As a general flow control, there is a method in which the transmitting side first transmits data and transmits again when a problem occurs on the receiving side. On the other hand, in PCIe, the transmission side confirms the free capacity of the reception side buffer in advance and transmits a packet when a sufficient free capacity is secured.

  PCIe flow control is realized by DLLP (Data Link Layer Packet) generated by the data link layer. Details are left to the standards, etc., but roughly, they can be roughly divided into “InitFC” and “UpdateFC” as DLLP types. These flow control DLLPs have a format for storing the values of “Hdr FC” and “DataFC”. From these values, for example, the sending side knows how much buffer on the receiving side is left. Can be done.

  PCIe flow control is performed on a credit basis. First, the receiving side notifies the transmitting side of the buffer capacity (credit value) that it can receive at the time of link initialization. The transmission side compares the buffer capacity on the reception side with the length of the packet to be transmitted, and if there is a certain remaining in the buffer capacity on the reception side, transmits the packet. Then, the transmission side subtracts the size of the packet transmitted by itself from the notified buffer capacity of the reception side. Further, when empty information on the buffer capacity is transmitted from the receiving side, the corresponding amount is added. Hereinafter, this will be described in some detail.

  First, the receiving side issues Init FC (DLLP) to notify the transmitting side of a credit value (a value indicating a buffer capacity that can be received by itself). Note that the credit value information (internal credit counter) on the receiving side has been initialized. When receiving the Init FC, the transmission side sets the initial value of the internal credit counter (credit free capacity information register) to the credit value specified by Init FC. This is the initialization procedure.

  Then, the transmission side transmits data. At this time, each time data is transmitted, the transmitting side decreases the value of the credit counter by the amount of transmitted data.

  Every time data is received, the receiving side issues an Update FC (DLLP) to notify the transmitting side of a predetermined credit value (for example, a buffer capacity value for the received data). Each time the sending side receives the Update FC, the sending side increments the credit counter value by the value set in the Update FC. This is to recover the value of the credit counter.

  In this way, the transmission side can perform data transmission corresponding to the receivable buffer capacity notified from the reception side. Transmission data and Update FC are basically handled as one set, and one Update FC is issued for one Init FC. This is because when one Update FC is issued for a plurality of transmission data, recovery of the value of the credit counter is delayed, and in order to perform data transmission at a high speed, it is desirable to immediately issue the Update FC.

  As described above, the flow control defined by PCI Express is performed, but each device on the data transmission system according to the present invention also performs the flow control operation according to the above definition.

(Target device)
FIG. 6 is an example of a diagram illustrating a target device configuration according to the present embodiment. The target device (corresponding to T1 and T2) includes a PCIe communication core 601, a traffic monitor 602, a flow control unit 603, a register 604, a user circuit 605, and a memory 606.

  The PCIe communication core 601 corresponds to reception means for receiving transferred data, and has a three-layer structure of Transaction Layer, Datalink Layer, and Physical Layer. Communication with the user circuit 605 is performed via / F (InterFace). That is, when operating as a target device, a Memory Read or Memory Write request received from a master device connected via a switch at the end of the PCIe link is transferred from the Application I / F to the user circuit 605.

  The traffic monitor 602 has a function of measuring a data transfer rate per unit time based on a data transfer request (Memory Read or Memory Write request) transferred to the user circuit 605. The unit time value (information) is preset (stored) in the register 605, and the traffic monitor 602 acquires this and measures the data transfer rate. The measured data transfer rate is notified to the flow control unit 603.

  The flow control unit 603 determines whether or not the data transfer rate measured by the traffic monitor 602 is equal to or greater than a predetermined upper limit threshold set in the register 604 (determination unit). In addition, when it is determined that the data transfer rate is equal to or higher than a predetermined threshold, the master device has a function of issuing a restriction request (flow control request) for instructing a restriction of an issuance band of the data transfer request to the master device. Here, the issue bandwidth limit of the data transfer request means a limit on the amount of the data transfer request per unit time. Further, after determining that the measured data transfer rate is equal to or higher than a predetermined threshold, it is determined whether the measured data transfer rate is equal to or lower than a predetermined lower threshold, and the measured data transfer rate is again lower than the predetermined lower threshold. When it is determined as follows, a release request (flow control request) for instructing release of the bandwidth limit for issuing the data transfer request is issued to the master device. In the present embodiment, it is assumed that a restriction request / release request (by a broadcast packet) that is a flow control request is issued to all master devices connected on the PCIe communication system. The data transfer request issuance bandwidth refers to the amount of data transfer requests requested by the master device per unit time.

  The user circuit 605 is a circuit that provides a function related to the target device. When receiving the Memory Write request, the user circuit 605 stores the Memory Write data in the memory 606. When receiving the Memory Read request, the user circuit 605 reads the Memory Read data from the memory 606 and transfers it to the Application I / F. Memory Read data is stored in a Compleiton data packet in the PCIe communication core and transferred to the master device at the end of the PCIe link.

  In the register 604, information on a unit time value, a transfer rate upper limit threshold value, and a transfer rate lower limit threshold value is set (stored) in advance. As described above, the unit time value is used for data transfer rate measurement by the traffic monitor 602, and the transfer rate upper limit threshold and the transfer rate lower limit threshold are used for threshold determination by the flow control unit 603.

(Master device)
Next, a master device for the target device will be described. FIG. 7 is an example of a diagram illustrating a master device configuration according to the present embodiment. The master device (corresponding to M1-M4) includes a PCIe communication core 701, a flow control request receiving unit 702, a flow control unit 703, a register 704, a user circuit 705, and a memory 706. Differences from the target device will be described and description of overlapping points will be omitted.

  The flow control request receiving unit 702 has a function of receiving a restriction request / release request that is a flow control request issued from the target device. Since the restriction request / cancellation request employs a request based on the PCIe standard, the flow control request receiving unit 702 receives the request after passing through the PCIe communication core 701.

  The flow control unit 703 receives the restriction request / release request received by the flow control request reception unit 702 and analyzes the content. The analysis contents are the target device of the issuer, the request type (Message Broadcast / Memory Write), whether the request is for requesting the issue bandwidth limit of the data transfer request, or the request for releasing the issue bandwidth limit. , Etc. The type of request (especially Memory Write) will be touched again in a later-described modification. Then, the flow control unit 703 determines based on the priority information set in the register 704 in advance whether or not it is a target for restricting / releasing the issuance band of the data transfer request to the target device. To do. The priority information indicates whether the priority of traffic issued by the target device is high or low. Therefore, for example, when the priority is low, the restriction request / cancellation request is accepted (determination is made). If the priority is high, it is not necessary to accept the restriction request / cancellation request, and the request is ignored (determination is made). The priority information is stored not only as high / low information but also as numerical information, and priorities can be set in stages according to the numerical values. When the flow control unit 703 determines to accept the restriction request / cancellation request, the flow control unit 703 instructs the user circuit 705 to cancel / limit the issuance band of the data transfer request.

  The data transfer system and components according to the present invention have been described above. Subsequently, these operations will be described.

(Operation)
FIG. 8 is an example of a diagram illustrating a configuration of a PCI Express system for explaining operations of the master device and the target device. Using the PCIe standard, a data communication system is shown in which four master devices (M1-M4) are connected to two target devices (T1, T2) via three switches (SW1-SW3) Yes. In the figure, master devices M1 and M3 generate high-priority traffic that cannot be interrupted even for a short time, and M2 and M4 generate low-priority traffic. M2 and M4 issue requests to T1, and M1 and M3 issue requests to T2.

  As an outline of the operation, when the transfer rate of the target device T1 exceeds the upper limit threshold set in T1, T1 immediately issues a PCIe Message Broadcast request. As a result, a band limitation instruction is given (notified) to all master devices M1-M4. Since M2 and M4 are set in advance to a low priority, data transfer to T1 is temporarily stopped (or the data transfer rate is lowered). For this reason, the credit is not exhausted in the link 1 of the PCIe, and the credit is not exhausted in the links 2 and 3 as well. Accordingly, continuous data transfer is possible without hindering traffic from M1 and M3 having high priority. Details will be described below.

  FIG. 9 is a flowchart for explaining the operation of the target device. Each time the target device (for example, T1) receives a data transfer request packet (Memory Read or Memory Write request), the target device performs an operation of transferring the request packet from the Application I / F to the user circuit 605 via the PCIe core 601. It is repeating. In parallel with this, the traffic monitor 602 determines whether or not the unit time has passed (S901), and if it has passed, the data transfer rate per unit time based on the data transfer request transferred to the user circuit 605. Is measured (S902). Note that the unit time value (information) refers to what is preset (stored) in the register 605.

  The flow control unit 603 determines whether or not the measured data transfer rate is equal to or higher than the upper limit threshold set in the register 604 (S903). When it is determined that the data transfer rate is equal to or higher than the predetermined threshold, a restriction request (flow control request) for instructing a restriction band for issuing a data transfer request is issued to all master devices (S904). If the measured data transfer rate has not reached the upper limit threshold set in the register 604, the process waits again until the unit time elapses (returns to S901).

  The traffic monitor 602 again determines whether or not the unit time has elapsed (S905), and if it has elapsed, measures the data transfer rate per unit time based on the data transfer request transferred to the user circuit 605 (S906). ).

  The flow control unit 603 determines whether or not the measured data transfer rate is equal to or lower than a predetermined lower limit threshold (S907). When it is determined that the measured data transfer rate is equal to or less than the predetermined lower threshold, a release request (flow control request) for instructing release of the issue bandwidth limitation of the data transfer request is issued to all master devices (S908). If the measured data transfer rate has not fallen below the lower threshold set in the register 604, the process waits again until the unit time elapses (returns to S905).

  As described above, each time the target device receives a data transfer request packet, the target device performs the operations from S901 to S908 as the request packet transfer process until the data transfer operation is completed in parallel with the operation to transfer to the user circuit 605. Continue to process repeatedly asynchronously. Next, the operation of the master device that has received such a target device operation will be described.

  FIG. 10 is a flowchart for explaining the operation of the master device. First, the master device (for example, M1-4) receives a restriction / cancellation request packet from the target device (S1001). This corresponds to S904 or S907 in FIG. More specifically, the restriction / cancellation request packet is transferred from the Application I / F to the flow control request receiving unit 702 via the PCIe core 701.

The flow control unit 703 receives the restriction request / release request received by the flow control request reception unit 702 and analyzes the content (S1002). As described above, the analysis contents include the target device of the issuer, the type of request (Message Broadcast / Memory Write), whether the request is a request to limit the issue bandwidth of the data transfer request, or the issue bandwidth limit is released. Is it a request? Then, it is determined whether the request type is Message Broadcast (S1003).
Subsequently, priority determination is performed (S1004). If the priority is low due to the priority information, the request is followed. If the priority is high, the process ends. That is, when the priority is low, the instruction of the restriction request / release request is followed (S1005). If it is a restriction request, the user circuit 705 is instructed to restrict the bandwidth for issuing a data transfer request. On the other hand, if it is a release request, the user circuit 705 is instructed to release the data transfer request issue bandwidth restriction.

  Here, S1003 will be described in detail. When the target device gives an instruction for bandwidth limitation or bandwidth limitation release by a Message Broadcast request, this request packet is transmitted to all the master devices. On the master device side that receives this, an operation for determining whether or not to accept the instruction is performed according to the priority information set for each device. This is determined by the priority of traffic issued by each master device. For example, a master device with lower traffic priority is set to have lower priority because it wants to accept bandwidth limitation, while a master device with higher traffic priority does not accept bandwidth limitation. Therefore, the priority is set to be higher. In other words, for the time being, the target device puts a Message Broadcast request in all the master devices, and the master device side determines whether to accept or reject the request.

  On the other hand, in S1003, the case where it is not a Message Broadcast request corresponds to the case where it is a Memory Write request. This is a type of request packet that complies with PCIe and can specify the destination directly. Therefore, if the received packet type is a Memory Write request, the target device sends a Memory Write request by designating the destination directly to the master device. That is, since the priority determination is performed on the target device side and is directly transmitted to the master device having a low priority, the determination in S1003 is performed so that the priority determination can be omitted again on the master device side. Done. Therefore, when it is not a Message Broadcast request (when it is a Memory Write request), it is sufficient to follow the instruction for bandwidth limitation or bandwidth limitation without priority determination. This point will be described later again in a modified example.

  Here, a supplementary description will be given of the unit time value, the upper threshold value, and the lower threshold value set in the register 604. As described above, the unit time is used when the traffic monitor 602 measures the request amount (transfer rate) per unit time. This unit time value designates a time shorter than the time period required for the data transfer when there is a restriction on the time period among the traffic flowing on the route. For example, according to the data transfer example of the copying machine described above, there was a device with a transfer time restriction at a cycle of 95 μsec, so the time cycle when calculating the transfer rate with the register of the target device is a value sufficiently smaller than 95 μsec. It is necessary to. Furthermore, since the number of packets that must be transferred per time period is 117, the unit time value set in the register is at least several to several tens or more in order to calculate a highly accurate transfer rate. It is desirable to set the time longer than the time when the request packet can be transferred. When using a PCIe x1 lane to transfer 128 bytes of data with a single Memory Write request packet as in the case of copier data transfer, 1 symbol time (time required for 1 byte transfer) of 1 lane is 4 ns. The transfer takes at least 128 × 4 = 512 ns. The time required for continuous transfer of 10 packets is 5.12 μsec.

  Next, it is desirable to set the upper threshold value to approximately 80% of the amount of data that can be transferred per unit time in order to instruct bandwidth limitation before reaching the transfer rate limit. It is desirable to adjust according to the latency required for packet transmission on the communication path. The latency required to reach the master device after notification of the broadcast transfer from the target device depends on the PCIe link width (number of lanes), the number of stages of PCIe switches, and the like. If the latency is small, the upper threshold can be set to a large value (for example, 90% of the amount of data that can be transferred per unit time), but if the latency is large, the upper threshold is reduced (for example, per unit time). Efficient traffic adjustment is possible.

  The lower threshold is preferably set to a value of about 50% of the amount of data that can be transferred per unit time in order to quickly release the bandwidth limitation when traffic congestion is resolved. It is desirable to adjust according to the latency required for packet transmission on the communication path. If the latency is small, the lower threshold can be set to a large value (for example, 70% of the amount of data that can be transferred per unit time), but if the latency is large, the lower threshold is made smaller (for example, the unit time By setting it to 30% of the amount of data that can be transferred per unit, efficient traffic adjustment is possible.

  For example, as described above, if the time required to transfer 10 128-byte packets continuously, 5.12 μsec is set in the register as a unit time value, it can be transferred to the register per unit time as the upper limit threshold value. Assuming 80% of the data volume, set 128Byte × 10 × 0.8 = 1024Byte. Assuming 50% of the amount of data that can be transferred per unit time as the lower limit threshold, 128 bytes × 10 × 0.5 = 640 bytes is set.

  As described above, according to the first embodiment, a master device and a target device are connected by using a switch device corresponding to the PCIe standard or a communication core circuit, and the target device performs data transfer by credit-based flow control in the PCIe standard. Since the target device instructs the master device to limit the data transfer request before the data transfer stops, the data transfer rate is reduced and the latency required for packet transfer is minimized when data transfer contention occurs. Can be suppressed. In addition, since the master device is directly instructed to limit the data transfer request, the latency can be further reduced. In addition, since broadcast transfer using a Message Broadcast request is used, even if the number of master devices increases or decreases, the time and effort for changing the configuration and register settings of the target device are reduced.

[Modification]
FIG. 11 is an example of a diagram illustrating a configuration of a PCI Express system for explaining operations of the master device and the target device according to the present modification. When the transfer rate of the target device T1 according to this modification exceeds the upper limit threshold set in T1, T1 immediately issues a “Memory Write request” for PCIe. In the target device, the priority is determined, and the restriction / release request is transmitted by directly specifying the destination of the master device that is assumed to be low in priority by the Memory Write request (packet). Thereby, only the master devices M2 and M4, which are set in advance in the T1 register and have a low priority, are instructed to limit the bandwidth. Then, according to the restriction / cancellation request, M2 and M4 temporarily stop data transfer for T1 (or decrease the data transfer rate). For this reason, the credit is not exhausted in the link 1 of the PCIe, and the credit is not exhausted in the links 2 and 3 as well. Therefore, continuous data transfer is possible without hindering traffic from M1 and M3 with high priority. In other words, since the bandwidth limitation instruction is given to the master devices M2 and M4 that have low priority, the master device side may follow the instruction without determining the priority. A circuit for determining the priority on the master device side becomes unnecessary, and the present invention can be realized with a simpler configuration.

  FIG. 12 is an example of a diagram illustrating a target device configuration according to the present embodiment. The target device (corresponding to T1 and T2) includes a PCIe communication core 601, a traffic monitor 602, a flow control unit 603-2, a register 604-2, a user circuit 605, and a memory 606. The flow control unit 603-2 and the register 604-2 according to the present modification will be described.

  Master priority information for each master device is further set (stored) in the register 604-2. For example, information that M1 and M3 have high priority and M2 and M4 have low priority is described.

  As described above, the flow control unit 603-2 determines whether the measured data transfer rate is equal to or higher than the upper limit threshold set in the register 604 for each unit time (S903). When it is determined that the data transfer rate is equal to or higher than a predetermined threshold, a limit request (flow control request) for instructing a limit for issuing a data transfer request is issued to the master device (S904). The information is acquired, and the master device that issues the restriction request is determined based on the priority. For example, master priority information is acquired, and master devices that issue restriction requests are determined as M2 and M4 with low priority. Then, according to the determination, a Memory Write request packet is issued with the corresponding master device as the destination.

  The master device (M2, M4) that has received this, as described in (S1003) of FIG. 10, omits the priority determination and performs the operation according to the instruction by the request as it is. In the master device according to this modification, the register 704 (FIG. 7) may be omitted. This is because priority determination is not necessary on the master device side.

  As described above, according to the target device of the present modification, the band limitation instruction is given only to the master devices M2 and M4 that are assumed to have low priority. Therefore, the master device side may follow the instruction without determining the priority. . That is, a circuit for determining priority on the master device side is not necessary, and the present invention can be realized with a simpler configuration. In addition, since a Memory Write request is issued (transferred) only to a master device with a specific low priority, unnecessary packets are not transferred to the communication route to the master device with a high priority, and the use efficiency of the data transmission channel can be expected to improve. .

[Embodiment 2]
As the second embodiment, the data communication system according to the present invention is applied to a multifunction peripheral (MFP) including two scan units (front unit and back unit). FIG. 13 is an example of a diagram showing a configuration in which the PCI Express system according to the present invention is applied to an MFP.

  In the present embodiment, it is assumed that master devices that generate high priority traffic are two scanner units (scan 1 and scan 2). In this data transfer system, it is assumed that both sides of a document are read simultaneously by two scanner units. In addition, it is assumed that the master device that generates low priority traffic is two image processing units (image processing 1 and image processing 2).

  Since scan 1 and scan 2 must process the transfer of line data in synchronization with the mechanical drive of the scanner head, they have transfer restrictions synchronized with the line period as described above. On the other hand, the image processing unit (image processing 1, image processing 2) has a feature that allows operations to temporarily stop or restart data transfer because there is no transfer restriction synchronized with the line cycle. The target device for each master device is a memory for storing image data. Specifically, the target device includes a memory unit 1 (memory 1) for storing processed image data and a memory unit 2 (memory 2) for storing scanned image data independently.

  As described above, the master device for scan 1 and scan 2 issues a data transfer request to the memory 2 via the PCIe link and the PCIe switch (SW1-3), and the master device for image processing 1 and image processing 2 The data transfer request is issued to the memory 1 via the PCIe link and the PCIe switch.

Similar to the example of the plotter described above, an example of calculation of data transfer restrictions in scan 1 and scan 2 will be described.
Scanner 1 line cycle (s) = 1 / {[Head moving speed (mm / s)] x [Number of pixels per 1 mm]}
To simplify the calculation, assume that the scanning resolution of the scanner is 50 dots / mm for both main scanning and sub-scanning, and that the number of bits for each pixel is 8 bits, assuming RGB color reading. Further, assuming that the document size is A4 vertical, the main scanning direction is 210 mm × the sub-scanning direction is 297 mm. The reading speed is assumed to be 60 sheets. At this time, since the reading time per sheet is 1 second, the paper feed speed in the sub-scanning direction is 297 mm / s. When calculating the scanner 1 line cycle,
1 / (297 × 50) = 0.000067 s = 67μs
become. The number of pixels per color in the main scanning direction is
210mm × 50dot / mm = 10500 dots
Thus, the data amount is 10500 dots × 8 bits / 8 = 10500 bytes. Furthermore, when calculating the amount of data for three RGB colors,
10500Byte × 3 colors = 31500Byte
It is. In other words, the transfer of scanned image data needs to be completed in 31500 bytes in 67 μs. The data transfer rate at this time is 31500 Byte / 0.000067s = about 470 MB / s. Since PCIe has a transfer performance limit of 250 MB / s or less per lane, considering the protocol loss, in this embodiment, the PCIe link width on the master device side is x4 lanes (1 GB / s) as shown in FIG. s or less transfer performance limit), and the PCIe link width on the target device side is x8 because two traffics through the PCIe x4 link pass through.

When sending one line of data, assuming that it is divided into 128-byte packets and transferred,
31500 Byte / 128 Byte = 247, and it is necessary to satisfy the data transfer restriction that 247 128 Byte data packets must be transferred to 67 μs within one line period.

  The target device shown in the first embodiment is used for the memory 1 and the memory 2 that are target devices. Since there are master devices (scan 1 and scan 2) that have a transfer time constraint with a period of 67 μsec, the unit time value when calculating the transfer rate with the register of the target device must be a value sufficiently smaller than 67 μsec. . Furthermore, the unit time value set in the register is several to several tens of request packets in order to calculate a highly accurate transfer rate for 247 packets that must be transferred per time period. Set the time longer than the transferable time. The packet transfer time is at least one packet transfer since 1 Symbol Time (time required for 1 Byte transfer) of 4 lanes is 1 ns when 128 bytes of data is transferred with one Memory Write request packet using PCIe x4 lanes. It takes 128ns. When the time required for continuously transferring 20 packets is used to measure the transfer rate, 128 ns × 20 = 2560 ns = 2.56 μsec. Set the register unit time value of the target device to 2.56μs.

  As a transfer rate upper limit threshold, assume that 80% of the data amount that can be transferred per unit time is set in the register, and 128 bytes × 20 × 0.8 = 2048 bytes are set. As the transfer rate lower limit threshold, it is assumed that 50% of the data amount that can be transferred per unit time is set in the register, and 128 Byte × 20 × 0.5 = 1280 Byte is set.

  When the target device shown in FIG. 12 is used for the memory 1 and the memory 2, the master priority information of the register of the memory 1 includes the master device of the image processing 1 and the image processing 2 as the master device having a low priority. Set it.

  The master device shown in FIG. 7 is used for scan 1, scan 2, image processing 1, and image processing 2 serving as master devices. That is, traffic priority information is set in the register of the master device. Specifically, information indicating that the priority is high in the registers for scan 1 and scan 2 and that the priority is low is set in the registers for image processing 1 and image processing 2.

  Referring to FIG. 13 again, when the transfer rate of memory 1 as the target device (request amount per 2.56 μsec unit time) exceeds the transfer rate upper limit threshold (2048 bytes) set in the register of memory 1, PCIe is immediately used. The message broadcast request (or Memory Write request) of the master device limits the bandwidth to the master devices of scan 1, scan 2, image processing 1, and image processing 2 (in the case of a memory write request, only image processing 1 and image processing 2). An instructing request packet is notified. At this time, the time required for the transfer of the notification packet is the time required for the packet to pass through the path of PCIe × 8 link−SW2-PCIe × 4 link−SW1 (or SW3) −PCIe × 4 link. Even if the packet passing latency is 100 ns for the x8 port and 200 ns for the x4 port, the total is about 300 ns, and the master device is notified in a sufficiently early time with respect to 67 μs which is the data transfer cycle of scan 1 and scan 2.

  In the image processing 1 and the image processing 2, since the priority relating to the traffic of the own node is low, the data transfer to the memory 1 is temporarily stopped. For this reason, no credit is depleted in the PCIe link 1, and no credit is depleted in the links 2 and 3. Therefore, traffic from scans 1 and 2 with high priority is not hindered and continuous data transfer is possible.

  Further, when the data transfer in the image processing 1 and the image processing 2 is stopped and the data transfer rate in the memory 1 is lowered to the transfer rate lower limit threshold (1280 Byte) or less, the memory 1 similarly receives a Message Broadcast request (or Memory Write request). ) Notifies the master device of scan 1, scan 2, image processing 1, and image processing 2 (in the case of a Memory Write request, image processing 1 and image processing 2) of a request packet instructing release of the bandwidth limitation. . The image processing 1 and the image processing 2 that have received the notification packet start data transfer again.

  By repeating the above operations, low-priority image processing 1 and image processing 2 also maintain a state where 50% to 80% of the data amount (transfer rate) that the memory 1 can transfer per unit time is used. Image processing can be advanced while scanning 1 and scan 2 with high priority continue to transfer 247 128-byte data packets to 67 μs within one line period, that is, very strict data transfer It is possible to operate under restricted conditions.

[Supplement]
In addition, the flow control by the ASI (Advanced Switching Interconnect) standard that appeared earlier will be mentioned. As described above, the ASI standard derived from PCIe defines SBFC (Status Based Flow Control) as a more advanced flow control method than the PCIe standard. According to SBFC, when a credit shortage (depletion) occurs in the output destination port, the switch device notifies the master device connected to the input port of the switch device of the credit shortage information. The notification allows the master device to detect a shortage of credit in the 1 Hop destination port, so that an operation for temporarily suspending a request addressed to the port can be performed to prevent influence on other traffic transfers. This will be described in detail below.

  FIG. 14 is an example of a diagram showing a data communication system configured by ASI. In ASI, the information on the credit depletion at the output port A is transmitted to the 1 Hop ahead device of link 1 where the credit depletion has occurred. Therefore, in SW1, the credit is depleted in the link 4 between M2 and SW1 before the credit is exhausted in the link 2 between SW1 and SW2. At this time, all the links in the route of M1-SW1-SW2-M2 do not run out of credit. Similarly, credit exhaustion does not occur in all links in the route of M3-SW3-SW2-T2. For this reason, traffic of M1 and M3 with high priority will not stop. In this way, even if the output port of the switch is shared, if low-priority traffic forwarding stops, the low-priority traffic is sent one hop before the high-priority traffic forwarding. Can be stopped.

  However, as the number of stages passing through the switch increases, the delay time until the shortage of credit at the destination port reaches the master device becomes longer. Referring to FIG. 14 again, the master device of M2 or M4 issues many packets on the SW1, SW2, and SW3 paths before stopping the request for T1 whose data processing capability is reduced. There is a possibility that the latency until the requests of M1 and M3, which are master devices whose priority is desired to be high, reaches T2 may be deteriorated.

  FIG. 15 is an example of a schematic enlarged view of SW1. Of course, SW2 and SW3 may be considered to have the same configuration. In the SW1, an arbiter that arbitrates input packets from each port and an internal buffer that can store a plurality of data packets are mounted. M2 continues to transfer the request packet to SW1 until the credit is depleted, so many packets from M2 are stored in the internal buffer. In the figure, six request packets from M2 are already stored before buffering request packets from M1. For this reason, the request from M1 is not transferred to SW2 unless all the six preceding packets from M2 have been transferred, and latency is increased.

  Specifically, assuming that the number of lanes of the PCIe link is x1 (250 MB / s) and the request packet size is 128 bytes, the transfer time of one packet is about 512 ns. For this reason, the time required for completing the transfer of six packets is 512 ns × 6 = 3072 ns, and the latency of M1 packet transfer increases by about 3 μsec. Since a general PCIe switch device has an internal buffer of about several kilobytes to 10 kilobytes, the latency deterioration phenomenon caused by waiting for a preceding request stored in the internal buffer becomes more prominent. As described in the second embodiment and the like, when the time allowed for one line of data transfer is several tens of μs as in the case of image data transfer of a copying machine, it causes a significant decrease in printing or scanning performance. . In this way, in the SBFC of the ASI standard, credit depletion information is transmitted to each device in order, so that latency occurs before the request issuance from the master device is stopped, and there are other effects due to the influence of the buffer on the communication path. There is a problem that the latency of the request from the device is deteriorated.

  Therefore, it is difficult to apply a data transfer system based on the ASI standard to an information processing apparatus having very strict data transfer constraint conditions such as the above-described multifunction peripheral (MFP). The data transfer system according to the present invention instructs the master device to restrict the data transfer request directly. That is, since the range for notifying the credit shortage is not limited by the number of Hops or the like, it is difficult for data to accumulate in the buffer of the switch in the path, and the latency can be further reduced.

[Summary]
As described above, in the data communication system according to the present invention, a switch device corresponding to the PCIe standard and a communication core circuit are used, and each target device and each master device directly process traffic arbitration. There is no concentration of requests that exceed the data transfer capability between them, and there is no data transfer stoppage due to credit-based flow control. For this reason, even if it is used for data communication in applications where the restrictions on the amount of data transfer per unit time are extremely strict, such as in electronic devices for embedded applications, if there is a data transfer conflict, the data transfer rate will be reduced. It is possible to minimize the occurrence of packet transfer latency due to the influence of the switch internal buffer on the way. In particular, for example, two-dimensional image data in the main-scanning and sub-scanning directions, such as a scanner or plotter of a copying machine (MFP), is matched to the mechanical driving speed of the scanner head or the plotter photosensitive member line by line in the main scanning direction. A significant effect can be expected in a data transfer system configured to share a common data transmission path for traffic to be transferred and traffic without line synchronization restrictions such as image processing.

  Therefore, according to the present invention, it is possible to provide a data transfer system and a data transfer method that suppress the occurrence of latency required for packet transfer and realize efficient data transfer.

  Note that the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

601 PCIe communication core 602 traffic monitor 603 flow control unit 603-2 flow control unit 604 register 604-2 register 605 user circuit 701 PCIe communication core 702 flow control request reception unit 703 flow control unit 704 register 705 user circuit

JP-A-10-91549 JP 2003-209568 A Japanese Patent No. 2912225

Claims (7)

A data transfer system comprising a target device and a master device capable of transferring data to the target device,
The master device is
Transmission means for transmitting a data transfer request to the target device after receiving information indicating the amount of data that the target device can receive from the target device;
A control means for limiting the amount of the data transfer request when receiving a restriction request transmitted from the transmission means of the target device,
The target device is
Measuring means for measuring a data transfer rate based on the data transfer request transmitted from the transmitting means of the master device;
A transmission unit that transmits a restriction request for limiting the amount of the data transfer request to all the master devices included in the data transfer system when the value of the data transfer rate measured by the measurement unit is equal to or greater than a predetermined value. And comprising
All the master devices have information indicating whether or not to comply with the restriction request, and when receiving the restriction request transmitted from the transmission unit, the control unit performs a data transfer request to the target device according to the information. A data transfer system which is a control means for limiting the amount of data. Before Symbol transmitting means of the target device, after the data transfer rate measured by said measuring means is determined to be equal to or greater than the predetermined value, the data transfer rate measured by said measuring means becomes equal to or less than a predetermined value And a transmission means for transmitting a release request for releasing the restriction on the amount of the data transfer request to the master device,
Billing before Symbol control means of the master device, wherein said case of receiving the release request transmitted from the previous SL transmitting means of the target device, a control means for releasing the limitation of the amount of the data transfer request Item 4. The data transfer system according to Item 1 . Before Symbol transmitting means of the target device, after the data transfer rate measured by said measuring means is determined to be equal to or greater than the predetermined value, the data transfer rate measured by said measuring means becomes equal to or less than a predetermined value A release request for releasing the restriction on the amount of the data transfer request is transmitted to all master devices included in the data transfer system,
2. The control unit according to claim 1 , wherein, when all the master devices receive the release request, the control unit is a control unit that releases the restriction on the amount of data transfer requests to the target device according to the information. Data transfer system. A data transfer system comprising a target device and a master device capable of transferring data to the target device,
The master device is
Transmission means for transmitting a data transfer request to the target device after receiving information indicating the amount of data that the target device can receive from the target device;
The amount of the data transfer request is limited when the restriction request transmitted from the transmission unit of the target device is received, and the amount of the data transfer request is limited when the release request transmitted from the transmission unit of the target device is received. Control means for releasing the restriction of
The target device is
Measuring means for measuring a data transfer rate based on the data transfer request transmitted from the transmitting means of the master device;
When it is determined that the value of the data transfer rate measured by the measuring unit is greater than or equal to a predetermined value, the data transfer rate measured by the measuring unit is less than or equal to a predetermined value . Transmitting means for transmitting a limit request for limiting the amount to the master device ,
The target device has information indicating whether to transmit the restriction request or the release request to the master device, and determines a master device that is a transmission destination of the restriction request or the release request according to the information. Lud over data transfer system to the. The transmission channel data transfer system according to claims 1 to 4 any one, characterized in that it is a serial data transmission line by PCI Express. A data transfer method in a data transfer system comprising a target device and a master device capable of transferring data to the target device,
The master device is
A transmission procedure for transmitting a data transfer request to the target device after receiving information indicating the amount of data that can be received by the target device from the target device;
A control procedure for limiting the amount of the data transfer request when receiving a restriction request transmitted by the transmission procedure of the target device; and
The target device is
A measurement procedure for measuring a data transfer rate based on the data transfer request transmitted by the transmission procedure of the master device;
A transmission procedure for transmitting a restriction request for restricting the amount of the data transfer request to all the master devices included in the data transfer system when the value of the data transfer rate measured by the measurement procedure is a predetermined value or more. And run
When all the master devices have information indicating whether to comply with the restriction request, and when receiving the restriction request transmitted by the transmission procedure, the control procedure performs a data transfer request to the target device according to the information. A data transfer method characterized by being a control procedure for limiting the amount of data. A data transfer method in a data transfer system comprising a target device and a master device capable of transferring data to the target device,
The master device is
A transmission procedure for transmitting a data transfer request to the target device after receiving information indicating the amount of data that can be received by the target device from the target device;
When receiving a restriction request transmitted by the target device transmission procedure, the amount of the data transfer request is limited, and when receiving a release request transmitted by the target device transmission procedure, the amount of the data transfer request And a control procedure for releasing the restriction of
The target device is
A measurement procedure for measuring a data transfer rate based on the data transfer request transmitted by the transmission procedure of the master device;
After the data transfer rate value measured by the measurement procedure is determined to be greater than or equal to a predetermined value and the data transfer rate measured by the measurement procedure is less than or equal to a predetermined value, the data transfer request A sending procedure for sending a limit request to limit the amount to the master device;
The target device has information indicating whether to transmit the restriction request or the release request to the master device, and determines a master device that is a transmission destination of the restriction request or the release request according to the information. Data transfer method.

Images