JP5306906B2 - Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device having a lateral overflow drain structure keeping the linearity of a signal output which depends on accumulation time, in employing a structure shared by a plurality of pixels. <P>SOLUTION: In employing a structure shared among pixels wherein a plurality of pixels share an FD section that is a charge-to-voltage converter in a solid-state imaging device having a lateral overflow drain structure, charges in a photodiode shared by all pixels are reset by an anti-blooming shutter operation simultaneously with or prior to reading out signals from pixels in a readout row to keep the linearity of the signal output that depends on accumulation time. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

The present invention relates to a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic apparatus.

  As one type of solid-state imaging device, an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device, for example, a CMOS (Complementary Metal Oxide Semiconductor) type (including MOS type) solid-state imaging device (hereinafter referred to as “CMOS”). Image sensor ”).

  In this CMOS image sensor, when the side on which the wiring layer is arranged with respect to the photoelectric conversion portion is the front side, the front side incident type (also referred to as the front side irradiation type) that takes in incident light from the front side. A pixel structure is common. On the other hand, there is a back-illuminated type (sometimes referred to as a back-illuminated type) pixel structure that takes in incident light from the side opposite to the side where the wiring layer is arranged, that is, the back side (for example, Patent Document 1). reference).

  Incidentally, in order to prevent the electric charge overflowing from the photoelectric conversion portion from leaking into the adjacent pixels, the front-illuminated pixel structure generally adopts a vertical overflow drain structure shown in FIG. This vertical overflow drain structure is a structure in which the potential barrier at the bottom of the photoelectric conversion unit (PD) 51 is set lower than the potential barrier below the transfer gate 53 and the charges overflowing from the photoelectric conversion unit 51 are discarded to the substrate 52 side. is there.

  On the other hand, since the back-illuminated pixel structure does not have a substrate, the charges overflowing from the photoelectric conversion unit cannot be discarded. Therefore, in the case of a back-illuminated pixel structure, as shown in FIG. 17, the electric charge overflowing from the photoelectric conversion unit 51 passes through the transfer gate 53 to the floating diffusion unit (hereinafter referred to as “FD unit”) 54. It is necessary to adopt a lateral overflow drain structure. Incidentally, by preventing the electric charge overflowing from the photoelectric conversion unit 51 from leaking into adjacent pixels, blooming (a phenomenon in which a portion where no light is incident appears bright) can be suppressed.

  As another technique for countermeasures against blooming, an electronic shutter for countermeasures against blooming is provided at the same time as an electronic shutter for defining an exposure time (accumulation time) for a pixel row from which no charge is read once in one frame period. There is a technique to perform (see, for example, Patent Document 2). Another technique for countermeasures against blooming is basically a technique for a front-illuminated solid-state imaging device, and the charge of the photoelectric conversion unit 51 is thrown away to the power source via the FD unit 54.

  Incidentally, in the CMOS image sensor, a plurality of pixels including a photoelectric conversion unit are arranged in a two-dimensional array. Each pixel has many constituent elements (for example, transistors) constituting a transfer gate unit, a reset gate unit, an amplifier unit, and the like in addition to the photoelectric conversion unit in one pixel region. There is a limit to plan.

However, recently, there is a so-called multiple pixel sharing structure that suppresses the occupied area other than the photoelectric conversion unit per pixel by sharing a part of the components originally provided for each pixel between the plurality of pixels. Proposed. This multi-pixel sharing structure is becoming an indispensable technique for miniaturizing pixels in a CMOS imager.

JP 2003-031785 A JP 2008-288904 A

  In the back-illuminated pixel structure, when a multi-pixel sharing structure is adopted, the following problems occur if the charge in the photoelectric conversion unit of the pixel sharing the FD unit for the readout row is not discarded in advance. To do. That is, if charge is accumulated in the photoelectric conversion unit of the pixel sharing the FD part, the charge leaks to the FD part of the pixel in the readout row because the charge leaks under the transfer gate having a low potential barrier. The linearity of the signal output depending on the accumulated time cannot be maintained (details will be described later).

  Here, the problem in the back-illuminated pixel structure when the multi-pixel sharing structure is adopted has been described, but the problem also applies to the front-illuminated pixel structure when the lateral overflow drain structure is adopted. I can say that. That is, the problem that the linearity of the signal output depending on the accumulation time cannot be maintained is applicable to all solid-state imaging devices having a lateral overflow drain structure employing a multi-pixel sharing structure.

Accordingly, the present invention provides a solid-state imaging device having a lateral overflow drain structure capable of maintaining the linearity of the signal output depending on the accumulation time, a driving method of the solid-state imaging device, and the solid-state imaging device when adopting a multi-pixel sharing structure It is an object to provide an electronic device having

In order to achieve the above object, the present invention includes a photoelectric conversion unit, a transfer transistor that transfers a charge photoelectrically converted by the photoelectric conversion unit to a charge-voltage conversion unit, and a reset transistor, and the photoelectric conversion unit A plurality of pixels are arranged in a matrix form, and at least the charge voltage conversion unit is shared by the plurality of pixels . The pixel has a structure that discards the charges overflowing from the transfer transistor , the charge voltage conversion unit, and the reset transistor to the selected power supply line. Scanning the pixel array unit and a plurality of rows including the row for reading signals from each pixel of the pixel array unit by alternately driving the selected power supply lines at a first voltage level and a second voltage level to select a state; the selection power source line with multiple lines of selected state, before reading out signals from pixels on the read row, a first pixel in the readout row, readout row A second pixel sharing the charge voltage conversion unit with the pixel, a row scanning unit for resetting the charge in the photoelectric conversion unit with respect to a pixel in the readout row and a third pixel not sharing the charge voltage conversion unit; The pixel has a back-illuminated pixel structure that captures incident light from the side opposite to the side where the wiring layer is disposed with respect to the photoelectric conversion unit, and the row scanning unit includes the selection power line There among the plurality of rows in the selected state, about the line containing the pixel to be reset, the changing the potential of the selection power source line from the first voltage level to the second voltage level, said the previous SL transfer transistor reset transistor both on the potential of the selection power source line is changed from the second voltage level to said first voltage level, by turning off both of the transfer transistor and the reset transistor, the first A configuration in which the charge in the photoelectric conversion unit is simultaneously reset for the same number of pixels by a combination of the first pixel and the second pixel, or a combination of the first pixel, the second pixel, and the third pixel. Is adopted.

The structure that discards the charge overflowing from the photoelectric conversion unit to the charge voltage conversion unit through the transfer gate unit is a lateral overflow drain structure. In the solid-state imaging device having the lateral overflow drain structure, in sharing the charge-voltage conversion unit among a plurality of pixels, the signal in the photoelectric conversion unit of the shared pixel is read simultaneously with or before the signal is read from the pixel in the readout row. Reset the charge. Even if charge is accumulated in the photoelectric conversion unit of the shared pixel by this reset operation, the charge is discarded, so that the charge overflows from the photoelectric conversion unit of the shared pixel before the signal is read from the pixel in the readout row. There is no leakage into the voltage converter.

According to the present invention, in a solid-state imaging device having a lateral overflow drain structure, charge does not overflow from the photoelectric conversion unit of the shared pixel and leak into the charge-voltage conversion unit. The linearity of signal output can be maintained.

1 is a system configuration diagram showing an outline of a system configuration of a CMOS image sensor to which the present invention is applied. It is sectional drawing which shows an example of a structure of a back-illuminated pixel structure. It is a circuit diagram which shows an example of the pixel circuit which does not take a multiple pixel sharing structure. It is a circuit diagram which shows an example of the pixel circuit which takes a multiple pixel sharing structure. 4 is a timing chart for explaining the circuit operation of a pixel circuit sharing four pixels. It is a timing chart for demonstrating the conventional problem in the case of the pixel circuit of 4 pixel sharing. It is explanatory drawing about the linearity of the signal output depending on accumulation time. It is a timing chart for demonstrating the conventional problem in the case of the pixel circuit of 2 pixel sharing. 6 is a timing chart for explaining driving in the case of sharing four pixels in the CMOS image sensor according to the present embodiment. It is explanatory drawing about the anti-blooming shutter operation | movement in the case of sequential reading. It is explanatory drawing about the anti-blooming shutter operation | movement in the case of 1/3 thinning-out reading. It is explanatory drawing about the anti-blooming shutter operation | movement in the case of 2/8 thinning-out reading. It is explanatory drawing about the anti-blooming shutter operation | movement in the case of 2/15 thinning-out reading. It is explanatory drawing about the anti-blooming shutter operation | movement in the case of 1/5 thinning-out reading. It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention. It is sectional drawing which shows a surface incidence type pixel structure. It is sectional drawing which shows a back-illuminated pixel structure.

Hereinafter, modes for carrying out the invention (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The description will be given in the following order.

1. Solid-state imaging device to which the present invention is applied (example of a CMOS image sensor)
2. 2. Back-illuminated pixel structure Multiple pixel sharing structure (example of 4-pixel sharing)
4). 4. Problems when adopting back-illuminated type multiple pixel sharing structure 5. Characteristic part of this embodiment Electronic equipment (example of imaging device)

<1. Solid-state imaging device to which the present invention is applied>
(System configuration)
FIG. 1 is a system configuration diagram showing an outline of a system configuration of a solid-state imaging device to which the present invention is applied, for example, a CMOS image sensor which is a kind of XY address type solid-state imaging device. Here, the CMOS image sensor is an image sensor created by applying or partially using a CMOS process.

  The CMOS image sensor 10 according to this application example is integrated on a pixel array unit 12 formed on a semiconductor substrate (hereinafter also referred to as “chip”) 11 and on the same chip 11 as the pixel array unit 12. And a peripheral circuit portion. In this example, for example, a row scanning unit (vertical driving unit) 13, a column processing unit 14, a column scanning unit (horizontal driving unit) 15 and a system control unit 16 are provided as peripheral circuit units.

  In the pixel array unit 12, unit pixels (hereinafter sometimes simply referred to as “pixels”) having a photoelectric conversion unit that generates and accumulates photoelectric charges having a charge amount corresponding to the amount of incident light are arranged in a matrix. Two-dimensional arrangement. A specific configuration of the unit pixel will be described later.

  The pixel array section 12 is further provided with a pixel drive line 17 for each pixel row with respect to the matrix-like pixel arrangement along the horizontal direction / row direction (pixel arrangement direction of the pixel row), and vertical for each pixel column. The signal line 18 is wired along the vertical direction / column direction (pixel arrangement direction of the pixel column). The pixel drive line 17 transmits a drive signal for driving to read a signal from the pixel. In FIG. 1, the pixel drive line 17 is shown as one wiring, but the number is not limited to one. One end of the pixel drive line 17 is connected to an output end corresponding to each row of the row scanning unit 13.

  The row scanning unit 13 includes a shift register, an address decoder, and the like, and is a pixel driving unit that drives each pixel of the pixel array unit 12 at the same time or in units of rows. Although the specific configuration of the row scanning unit 13 is not shown, the row scanning unit 13 generally has two scanning systems, a reading scanning system and a sweeping scanning system.

  The readout scanning system selectively scans the unit pixels of the pixel array unit 12 sequentially in units of rows in order to read out signals from the unit pixels. The signal read from the unit pixel is an analog signal. The sweep-out scanning system performs sweep-out scanning with respect to the readout row on which readout scanning is performed by the readout scanning system, preceding the readout scanning by a time corresponding to the shutter speed.

  By the sweep scanning by the sweep scanning system, unnecessary charges are swept out from the photoelectric conversion elements of the unit pixels in the readout row, so that the photoelectric conversion elements are reset. A so-called electronic shutter operation is performed by sweeping (reset) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion element is discarded and a new exposure is started (photocharge accumulation is started).

  The signal read by the reading operation by the reading scanning system corresponds to the amount of light incident after the immediately preceding reading operation or electronic shutter operation. The period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photocharge accumulation period (exposure period) in the unit pixel.

  A signal output from each unit pixel in the pixel row selectively scanned by the row scanning unit 13 is supplied to the column processing unit 14 through each vertical signal line 18. For each pixel column of the pixel array unit 12, the column processing unit 14 performs predetermined signal processing on a signal output from each pixel of the selected row through the vertical signal line 18, and temporarily outputs the pixel signal after the signal processing. Hold on.

  Specifically, the column processing unit 14 receives a signal of a unit pixel and removes noise from the signal by, for example, CDS (Correlated Double Sampling), signal amplification, or AD (analog-digital). ) Perform signal processing such as conversion. By the noise removal processing, fixed pattern noise unique to the pixel such as reset noise and variation in threshold value of the amplification transistor is removed. The signal processing illustrated here is only an example, and the signal processing is not limited to these.

  The column scanning unit 15 includes a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 14. By the selective scanning by the column scanning unit 15, the pixel signals processed by the column processing unit 14 are sequentially output to the horizontal bus 19 and transmitted to the outside of the chip 11 through the horizontal bus 19.

  The system control unit 16 receives a clock given from the outside of the chip 11, data for instructing an operation mode, and the like, and outputs data such as internal information of the CMOS image sensor 10. The system control unit 16 further includes a timing generator that generates various timing signals. Based on the various timing signals generated by the timing generator, the row scanning unit 13, the column processing unit 14, the column scanning unit 15, and the like. Drive control of the peripheral circuit section is performed.

The configuration of the CMOS image sensor 10 described above is basically the same for both the front-incident pixel structure and the back-illuminated pixel structure. However, it is assumed that the CMOS image sensor according to the present invention has a back-illuminated pixel structure. A specific configuration of the back-illuminated pixel structure will be described below.

<2. Back-illuminated pixel structure>
FIG. 2 is a cross-sectional view showing an example of the configuration of a back-illuminated pixel structure. Here, a cross-sectional structure for two pixels is shown.

  In FIG. 2, a photodiode 22 that is a photoelectric conversion unit and a pixel transistor 23 that drives the photodiode 22 are formed in the silicon portion 21. That is, the silicon part 21 is an element forming part.

  A color filter 25 is formed on one surface side of the silicon portion 21 via an interlayer film 24. Thereby, light incident from one surface side of the silicon part 21 is guided to the light receiving surface of the photodiode 22 via the color filter 25.

  On the other hand, on the other surface side of the silicon part 21, a wiring layer 27 is formed in which a gate electrode and a metal wiring of the pixel transistor 23 are multilayered in the interlayer insulating film 26. A support substrate 29 is attached to the surface of the wiring layer 27 opposite to the silicon portion 21 with an adhesive 28.

  In the above pixel structure, the wiring layer 27 side of the silicon part 21 where the photodiode 22 and the pixel transistor 23 are formed is referred to as a front surface side, and the side opposite to the wiring layer 27 of the silicon part 21 is referred to as a back surface side. Under this definition, the pixel structure is a back-illuminated pixel structure because incident light is taken from the back side of the silicon portion 21.

  According to this back-illuminated pixel structure, each wiring of the wiring layer 27 is laid out in consideration of the light-receiving surface of the photodiode 22 in order to capture incident light from the opposite surface side of the wiring layer 27, that is, from the back surface side. There is no need. Accordingly, since the degree of freedom of the wiring layout is increased, there is an advantage that the pixel can be miniaturized as compared with the surface irradiation type.

Further, the distance between the photodiode 22 and the color filter 25 is extremely short compared to the surface irradiation type. Even in the case of a back-illuminated pixel structure, a micro lens (on-chip lens) is required, but omitting the micro lens can be considered as one of the embodiments.

<3. Multiple pixel sharing structure>
In the CMOS image sensor 10 employing the back-illuminated pixel structure having the above-described configuration, in the present embodiment, for each pixel of the pixel array unit 11, some of the components that are originally provided for each pixel are arranged between a plurality of pixels. A multi-pixel sharing structure is used. Before describing the multiple pixel sharing structure, a pixel configuration that does not employ the multiple pixel sharing structure will be described.

(Pixel circuit without multiple pixel sharing structure)
FIG. 3 is a circuit diagram illustrating an example of a pixel circuit that does not employ a multiple pixel sharing structure. As shown in FIG. 3, the pixel 30 according to this circuit example has a configuration including three transistors of a transfer transistor 32, a reset transistor 33, and an amplification transistor 34 in addition to, for example, a photodiode 31 that is a photoelectric conversion unit. Yes. Here, a case where, for example, N-channel MOS transistors are used as these transistors 32 to 34 is shown.

  Here, the transfer transistor 32 constitutes a transfer gate portion that transfers the charge photoelectrically converted by the photodiode 31 to an FD portion (floating diffusion portion) 35 that is a charge-voltage conversion portion. The reset transistor 33 constitutes a reset gate unit that resets the potential of the FD unit 35. The amplification transistor 34 forms an amplification unit that outputs a signal corresponding to the potential of the FD unit 35 to the vertical signal line 18.

  In FIG. 3, the anode electrode of the photodiode 31 is grounded. The transfer transistor 32 is connected between the cathode electrode of the photodiode 31 and the FD portion 35, and a transfer pulse TRG is selectively given from the row scanning portion 13 to the gate electrode. Then, the transfer transistor 32 is turned on, photoelectrically converted by the photodiode 31, and the signal charge (here, photoelectrons) accumulated therein is transferred to the FD unit 35.

  The reset transistor 33 has a drain electrode connected to the selection power source SELVdd and a source electrode connected to the FD unit 35, and a reset pulse RST is selectively applied to the gate electrode from the row scanning unit 13 prior to charge transfer from the photodiode 31. Given to. Then, the reset transistor 33 is turned on, and the FD unit 35 is reset by throwing away the charge of the FD unit 35 to the selected power source SELVdd. Here, the selected power supply SELVdd selectively takes a Vdd level and, for example, a GND level as a power supply voltage.

  The amplification transistor 34 has a source follower configuration in which a gate electrode is connected to the FD portion 35, a drain electrode is connected to the selection power source SELVdd, and a source electrode is connected to the vertical signal line 18. Then, the amplification transistor 34 enters an operation state when the selected power supply SELVdd becomes the Vdd level, and outputs the potential of the FD portion 35 after being reset by the reset transistor 33 to the vertical signal line 18 as a reset level. Further, the amplification transistor 34 outputs the potential of the FD portion 35 after charge transfer by the transfer transistor 32 to the vertical signal line 18 as a signal level.

  Here, the selected power supply SELVdd selectively takes the GND level (0 V) or a first voltage level (for example, 0.6 V) in the vicinity thereof and the Vdd level, and switches from the GND level or the first voltage level to the Vdd level. The pixel is selected by.

(Pixel circuit according to this embodiment adopting a multi-pixel sharing structure)
FIG. 4 is a circuit diagram showing an example of a pixel circuit adopting a multiple pixel sharing structure. In FIG. 4, the same parts as those in FIG. 3 are denoted by the same reference numerals. Here, as an example, at least the FD part (charge-voltage conversion part) 35 that is originally provided for each pixel is arranged between a plurality of adjacent pixels, for example, the same vertical pixel and four vertical pixels adjacent to each other. A shared 4-pixel sharing structure will be described.

  In a pixel circuit adopting a four-pixel sharing structure, for example, one FD between these four pixels in units of vertical four pixels 30-1, 30-2, 30-3, and 30-4 that belong to the same pixel column and are adjacent to each other. The unit 35 is configured to be shared (shared). When sharing a plurality of adjacent pixels, it is easier to control the timing of signal readout from each pixel by sharing the same pixel column.

  The four pixels 30-1, 30-2, 30-3, and 30-4 as units each have photodiodes 31-1, 31-2, 31-3, and 31-4 that are photoelectric conversion units. Yes. Each of the four pixels 30-1, 30-2, 30-3, 30-4 is a pair (pair). An amplification transistor 34 is provided in the pixel region of the two pixels 30-1 and 30-2 in one set, and a reset transistor 33 is provided in the pixel region of the two pixels 30-3 and 30-4 in the other set. It has been.

  In the above-described pixel circuit that does not adopt the multiple pixel sharing structure, the drain electrodes of the reset transistor 33 and the amplification transistor 34 are both connected to the selection power source SELVdd. That is, a common selection power supply SELVdd is prepared as each drain power supply for the reset transistor 33 and the amplification transistor 34.

  On the other hand, in the pixel circuit according to this example, separate power supplies are prepared as drain power supplies for the reset transistor 33 and the amplification transistor 34. As separate power supplies, a fixed power supply Vdd having a fixed power supply voltage (voltage level) and a selection power supply SELVDD having a variable power supply voltage are prepared. The selection power source SELVDD selectively takes a first voltage level at or near the GND level (0 V) and a second voltage level VDD higher than the voltage level Vdd of the fixed power source Vdd, for example, and the second voltage level from the first voltage level to the second voltage level. Pixel selection is performed by switching to the level VDD.

  The drain electrode of the reset transistor 33 is connected to the selection power source SELVDD, and the drain electrode of the amplification transistor 34 is connected to the fixed power source Vdd. The source electrode of the reset transistor 33 is connected to the FD unit 35 shared among the vertical four pixels 30-1, 30-2, 30-3, 30-4. A reset pulse RST is selectively applied to the gate electrode of the reset transistor 33. The gate electrode of the amplification transistor 34 is connected to the FD portion 35, and the source electrode is connected to the vertical signal line 18.

(Circuit operation of a pixel circuit sharing four pixels)
Next, the circuit operation of the pixel circuit sharing the four pixels having the above-described configuration will be described with reference to the timing chart of FIG. 5, taking as an example a case where the accumulation time is 1H (H is a horizontal scanning period).

  At time t10, the selected power supply SELVDD is switched from the first voltage level (for example, GND level) to the second voltage level VDD, so that the pixels in the first to fourth rows are selected. Next, at time t11, both the transfer pulse TRG1 and the reset pulse RST in the first row become active (in this example, “H” level), so that the transfer transistor 32-1 of the pixel 30-1 and the four pixels are common. Both reset transistors 33 are turned on. As a result, the charges in the photodiode 31-1, that is, unnecessary charges are swept out to the selected power supply SELVDD via the FD section 35.

Next, the selection power SELVDD at time t12 will switch from the second voltage level to the first voltage level (level of GND or near) the via FD portion 35 and the reset transistor 33 from the off photodiode 31-1 sweep is carried out of the charge to the selected power SELVDD. The sweeping operation is an operation for Ru discard the charge within the photodiode 31-1.

  Next, at time t13, both the transfer pulse TRG1 and the reset pulse RST in the first row become inactive (in this example, “L” level). As a result, both the transfer transistor 32-1 and the reset transistor 33 of the pixel 30-1 are turned off. Then, when the transfer transistor 32-1 is turned off, accumulation of photoelectrically converted signal charges (photoelectrons) is started in the photodiode 31-1 in the first row.

  Subsequently, the reset pulse RST becomes active again at time t14, and then the selected power source SELVDD is switched to the second voltage level VDD at time t15, whereby the reset transistor 33 common to the four pixels is turned on. As a result, the charges in the 4-pixel shared FD section 35 are swept out to the selected power source SELVDD through the reset transistor 33. As a result, the potential of the FD unit 35 is reset to the second voltage level VDD of the selected power supply SELVDD.

  Then, when the reset pulse RST becomes inactive at time t16, the reset operation of the FD unit 35 ends, and the potential of the FD unit 35 at this time becomes the reset level of the pixels 30-1 in the first row. This reset level is output to the vertical signal line 18 by the amplification transistor 34 as a so-called P-phase level.

Next, the transfer pulse TRG1 in the first row becomes active at time t17, whereby the transfer transistor 32-1 of the pixel 30-1 is turned on. Thereby, the signal charge photoelectrically converted by the photodiode 31-1 is transferred to the FD unit 35 by the transfer transistor 32-1. That is, the period from time t13 to time t17 is the signal charge accumulation period of the pixel 30-1 in the first row.

  At time t18, the transfer pulse TRG1 in the first row becomes inactive, and the transfer of signal charges in the first row is completed. At this time, the potential of the FD portion 35 becomes a potential corresponding to the amount of signal charges transferred from the photodiode 31-1. The potential of the FD portion 35 becomes the signal level of the pixel 30-1 in the first row. This signal level is output to the vertical signal line 18 by the amplification transistor 34 as a so-called D-phase level.

  Next, at time t19, both the transfer pulse TRG2 and the reset pulse RST in the second row are activated, so that both the transfer transistor 32-2 and the reset transistor 33 of the pixel 30-2 are turned on. As a result, the charge in the photodiode 31-2 is swept out to the selected power source SELVDD via the FD portion 35.

  Subsequently, at time t20, the selected power supply SELVDD is switched to the first voltage level VDD, so that the reset transistor 33 is turned off. Thereby, the operation of sweeping out charges from the photodiode 31-2 to the selected power supply SELVDD via the FD section 35 and the reset transistor 33, that is, the reset operation of the photodiode 31-2 is completed.

  At time t21, the transfer pulse TRG2 in the second row becomes inactive, so that the transfer transistor 32-2 of the pixel 30-2 is turned off, and photoelectric conversion is performed in the photodiode 31-2 in the second row. Accumulation of the signal charge is started.

  Subsequently, the reset pulse RST becomes active at time t22, and then the selected power supply SELVDD is switched to the second voltage level VDD at time t23, whereby the reset transistor 33 is turned on. As a result, the charge of the FD portion 35 is discarded to the selected power source SELVDD through the reset transistor 33. As a result, the potential of the FD unit 35 is reset to the second voltage level VDD of the selected power supply SELVDD.

  Then, the reset pulse RST becomes inactive at time t24, so that the reset operation of the FD unit 35 ends, and the potential of the FD unit 35 at this time is the reset level (P phase) of the pixel 30-2 in the second row. Is output to the vertical signal line 18 by the amplification transistor 34.

  Next, when the transfer pulse TRG2 in the second row becomes active at time t25, the transfer transistor 32-2 of the pixel 30-2 is turned on. Thereby, the signal charge photoelectrically converted by the photodiode 31-2 is transferred to the FD section 35 by the transfer transistor 32-2. That is, the period from time t21 to time t25 is a signal charge accumulation period of the pixel 30-2 in the second row.

  Then, the transfer pulse TRG2 in the second row becomes inactive at time t26, whereby the transfer of signal charges in the second row is completed. At this time, the potential of the FD unit 35 is a potential corresponding to the amount of signal charges transferred from the photodiode 31-2. Then, the potential of the FD portion 35 is output to the vertical signal line 18 by the amplification transistor 34 as the signal level (D phase) of the pixel 30-2 in the second row.

  Next, at time t27, both the transfer pulse TRG3 and the reset pulse RST in the third row are activated, so that both the transfer transistor 32-3 and the reset transistor 33 of the pixel 30-3 are turned on. As a result, the charge in the photodiode 31-3 is swept out to the selected power supply SELVDD via the FD portion 35.

  Subsequently, at time t28, the selected power supply SELVDD is switched to the first voltage level VDD, so that the reset transistor 33 is turned off. Thereby, the operation of sweeping out charges from the photodiode 31-3 to the selected power supply SELVDD via the FD section 35 and the reset transistor 33, that is, the reset operation of the photodiode 31-3 is completed.

  At time t29, the transfer pulse TRG3 in the third row becomes inactive, so that the transfer transistor 32-3 of the pixel 30-3 is turned off, and photoelectric conversion is performed in the photodiode 31-3 in the third row. Accumulation of the signal charge is started.

  Subsequently, the reset pulse RST becomes active at time t30, and then the selected power supply SELVDD is switched to the second voltage level VDD at time t31, whereby the reset transistor 33 is turned on. As a result, the charge of the FD portion 35 is discarded to the selected power source SELVDD through the reset transistor 33. As a result, the potential of the FD unit 35 is reset to the second voltage level VDD of the selected power supply SELVDD.

  Then, the reset pulse RST becomes inactive at time t32, so that the reset operation of the FD unit 35 ends, and the potential of the FD unit 35 at this time is the reset level (P phase) of the pixel 30-3 in the third row. Is output to the vertical signal line 18 by the amplification transistor 34.

  Next, the transfer pulse TRG3 in the third row is activated at time t33, so that the transfer transistor 32-3 of the pixel 30-3 is turned on. Thereby, the signal charge photoelectrically converted by the photodiode 31-3 is transferred to the FD section 35 by the transfer transistor 32-3. That is, the period from time t29 to time t33 is the signal charge accumulation period of the pixel 30-3 in the third row.

  Then, at time t34, the transfer pulse TRG3 in the third row becomes inactive, and the transfer of signal charges in the third row is completed. At this time, the potential of the FD portion 35 becomes a potential corresponding to the amount of signal charges transferred from the photodiode 31-3. The potential of the FD portion 35 is output to the vertical signal line 18 by the amplification transistor 34 as the signal level (D phase) of the pixel 30-3 in the third row.

  Next, at time t35, both the transfer pulse TRG4 and the reset pulse RST in the fourth row are activated, so that both the transfer transistor 32-4 and the reset transistor 33 of the pixel 30-4 are turned on. As a result, the charge in the photodiode 31-4 is swept out to the selected power supply SELVDD via the FD portion 35.

Thereafter, similarly, the reset level (P phase) and the signal level (D phase) are read out for the pixels 30-4 in the fourth row and output to the vertical signal line 18 by the amplification transistor 34. Thereafter, the series of circuit operations described above in units of four rows are repeatedly executed for all pixel rows.

<4. Problems when using a back-illuminated multi-pixel sharing structure>
Here, as described above, in the back-illuminated pixel structure, when the multiple pixel sharing structure is adopted, the charge in the photodiode 31 of the pixel sharing the FD portion 35 with respect to the readout row is preliminarily stored. Describes the problems that must be thrown away.

  This problem occurs because the back-illuminated pixel structure adopts a lateral overflow drain structure in which charges overflowing from the photodiode 31 are discarded to the FD section 35 under the gate of the transfer transistor 32. That is, if charges are accumulated in the photodiode 31 of the pixel sharing the FD portion 35, the charge leaks into the FD portion 35 of the pixel in the readout row through the gate of the transfer transistor 32 having a low potential barrier. Therefore, there arises a problem that the linearity of the signal output depending on the accumulation time defined by the electronic shutter cannot be maintained.

  Here, the above problem will be described more specifically with reference to the timing chart of FIG. 6 taking the case of the pixel circuit sharing the four pixels as an example.

  In the case of a pixel circuit sharing four pixels, there is a row in which the shutter operation for discarding electrons (charges) is not performed in the photodiode 31 sharing the pixel in the short-time storage up to 3H. Electron leakage into the FD unit 35 occurs. Specifically, as indicated by the dot-and-dash circle in FIG. 6, when the accumulation time is 1H, the photodiodes 31-2, 31-3, 31-4 in the second, third, and fourth rows have no shutter. As a result, electrons overflow. When the accumulation time is 2H, the photodiodes 31-3 and 31-4 in the third and fourth rows do not have shutters, and when the accumulation time is 3H, the photodiodes 31-4 in the fourth row have no shutters, so electrons overflow. .

  As described above, when electrons leak into the FD unit 35, the linearity of the signal output depending on the accumulation time defined by the electronic shutter cannot be maintained as shown in FIG. In the case of a pixel circuit sharing four pixels, the linearity of the signal output depending on the accumulation time can be maintained when the accumulation time is 4H or more, but in the short-time accumulation up to 3H, the signal output depending on the accumulation time. The linearity of cannot be maintained.

  Here, the case of a pixel circuit sharing four pixels has been described as an example, but the same problem occurs in the case of a pixel circuit sharing other than four pixels. For example, in the case of a pixel circuit sharing two pixels, as shown in FIG. 8, the shutter operation is not performed by the photodiode 31 sharing the pixel when the storage time is 1H for a short time. When the accumulation time is 1H, the dependency of the signal output accumulation time cannot be maintained.

  That is, in a pixel circuit that shares the FD unit 35 with n pixels (n is an integer of 2 or more), when the accumulation time is short-time accumulation up to (n−1) H, the signal output linearity that depends on the accumulation time You can't keep sex.

  Further, the problem of the nonlinearity of the signal output depending on the accumulation time has been described by taking the case of the back-illuminated pixel structure as an example, but it is not limited to the back-illuminated pixel structure. That is, even in the front-illuminated pixel structure, it is conceivable to adopt a lateral overflow drain structure in which charges overflowing in the photoelectric conversion unit 51 are discarded to the FD unit 54.

Specifically, in FIG. 16, the potential barrier below the transfer gate 53 is made lower than the potential barrier at the bottom of the photoelectric conversion unit 51 by setting the voltage value of the gate voltage applied to the transfer gate 53. A lateral overflow drain structure can be realized. Even in the case of the front-illuminated pixel structure, when the lateral overflow drain structure is adopted, the linearity of the signal output depending on the accumulation time cannot be maintained.

<5. Characteristic part of this embodiment>
As described above, in the solid-state imaging device having the lateral overflow drain structure, in the present embodiment, when adopting a pixel sharing structure in which at least the FD unit 35 is shared among a plurality of pixels, a nonlinear signal output depending on the accumulation time is adopted. It was made to solve the problem of sex. In the present embodiment, when adopting the pixel sharing structure, pixels that share the FD unit 35 (hereinafter referred to as “shared pixels”) at the same time or before (in advance) when signals are read from the pixels 30 in the readout row. The charge in the photodiode 31 of (described) is reset.

  Below, the characteristic part of this embodiment is demonstrated more concretely. Here, as the pixel sharing structure, for example, a structure in which the FD unit 35 illustrated in FIG. 4 is shared between four adjacent pixels, for example, four pixels belonging to the same pixel column will be described as an example. However, the present invention is not limited to application to a 4-pixel sharing structure.

  As an example, the driving of the solid-state imaging device adopting the 4-pixel sharing structure is performed by the circuit operation based on the timing chart of FIG. 5 as described above. In the case of this driving, only when each of the four pixels 30-1 to 30-4 sharing the FD unit 35 is selected as a readout row by scanning by the row scanning unit 13, the photodiodes 31-1 to 31-31. A reset operation (electronic shutter operation) is performed to discard the charges in 4.

  Specifically, in the timing chart of FIG. 5, the pixel 30-1 in the first row in the period t11-t12, the pixel 30-2 in the second row in the period t19-t20, and the pixel in the third row in the period t27-t28. An electronic shutter operation is performed such as 30-3. That is, in each readout row selected by the row scanning unit 13, an electronic shutter operation that defines an accumulation time is only executed once as each reset operation of the photodiodes 31-1 to 31-4.

  In this way, in the case of driving that performs a reset operation that discards the charge in the photodiode 31 only when it is selected as a readout row, before reading out the signal from the pixel 30 in the readout row, the other shared pixels will Charge is accumulated in the diode 31. Then, in the solid-state imaging device having the lateral overflow drain structure, if the charge accumulated in the photodiode 31 of the shared pixel leaks under the gate of the transfer transistor 32 and leaks to the pixel in the readout row, it depends on the accumulation time described above. The problem of nonlinearity of signal output occurs.

  Therefore, in the solid-state imaging device having the lateral overflow drain structure, in the present embodiment, in adopting the pixel sharing structure, in the photodiode 31 of the shared pixel at the same time or before the signal is read from the pixel 30 in the readout row. The structure which resets the electric charge of is taken. The specific driving will be described with reference to the timing chart of FIG. FIG. 9 shows the timing relationship for driving the first to fourth rows when the accumulation time is 1H.

  Here, as an example, a case where the first row is selected as a readout row by the column scanning unit 13 will be described. When the first row is selected as a readout row, an electronic shutter operation is performed prior to reading out signals from each pixel in the first row. With this electronic shutter operation, as is apparent from the description of the operation based on FIG. 5, the signal charge accumulation time of the photodiode 31-1 is determined. Actually, in the timing chart of FIG. 5, accumulation of signal charges is started from time t13 when both the reset pulse RST and the transfer pulse TRG1 become inactive.

  In this example, at the timing of the electronic shutter of the first row, the shared pixels, that is, the photodiodes 31-2 to 31-4 of the pixels 30-2 to 30-4 of the second to fourth rows are reset. Perform the action. This reset operation is performed by the row scanning unit 13 under the control of the system control unit 16.

  Specifically, when the first-phase transfer pulse TR1 and the reset pulse RST are in the active state, the transfer pulses TR2 to TR4 in the second to fourth rows are also set in the active state. As a result, since the transfer transistors 32-2 to 32-4 in the second to fourth rows are turned on, the charges in the photodiodes 31-2 to 31-4 in the second to fourth rows are changed. It is swept out to the selected power supply SELVDD via the FD section 35 and the reset transistor 33.

  This reset operation is a shutter operation performed on the shared pixel separately from the electronic shutter operation on the pixel in the readout row. This reset operation is a technique similar to the shutter operation for countermeasures against blooming performed in the prior art described in Patent Document 2, and is therefore referred to as an anti-blooming shutter operation in this specification. .

  In the case of 4-pixel sharing, as shown in FIG. 10, the anti-blooming shutter operation is performed on the remaining three shared pixels in synchronization with the electronic shutter operation of the pixels in each readout row. In FIG. 10, ◯ indicates the signal readout timing from the pixel in the readout row, □ indicates the electronic shutter timing for the readout row, and X indicates the anti-blooming shutter timing of the shared pixel.

  In FIG. 10, the time between the circles and the squares in the same pixel row indicates the signal charge accumulation time (1H in this example). Further, in FIG. 10, a time t between the ◯ mark and the □ mark in the adjacent pixel rows indicates a timing difference between the signal reading and the electronic shutter in the adjacent pixel rows (see FIG. 5).

  In the example of FIG. 10, when the accumulation time is 1H and the readout row is the 0th row, the electronic shutter operation of the 0th row is performed 1H before the readout operation of the 0th row. The anti-blooming shutter operation is performed on the shared pixels, that is, the pixels on the first to third rows, at the same timing as the electronic shutter operation on the zeroth row. The electronic shutter operation, anti-blooming shutter operation, and readout operation are sequentially repeated in units of rows.

  By the above-described anti-blooming shutter operation, the charge in the photodiodes 31 of all the shared pixels can be discarded once before the operation of reading out signals from the pixels in the readout row. Thus, before the signals are read from the pixels in the readout row, charges do not overflow from the photodiodes 31 of all the shared pixels and leak into the FD unit 35 sharing the four pixels. The linearity of the dependent signal output can be maintained.

  This technique for maintaining the linearity of the signal output depending on the accumulation time is particularly useful when applied to a solid-state imaging device having a back-illuminated pixel structure. This is because the back-illuminated pixel structure does not have a substrate that discards the charges overflowing from the photodiode 31, and therefore needs to adopt a lateral overflow drain structure that discards the charges to the FD portion 35 through the gate of the transfer transistor 32. Because there is.

  In this example, the anti-blooming shutter operation for the shared pixel is performed before the electronic shutter operation timing of the readout row, that is, before the signal is read out from the pixel in the readout row, but when the signal is read out from the pixel in the readout row. It is also possible to do it simultaneously.

  Here, readout of signals from the pixels in the readout row starts from readout of the reset level (P phase) in the timing chart of FIG. Therefore, simultaneously with reading out signals from the pixels in the readout row, when the readout row is the first row, the selection power source SELVDD is at the second voltage level VDD and the reset pulse RST transitions from the active state to the inactive state. Say time t16.

(Thinning readout)
In the above, the technique for maintaining the linearity of the signal output depending on the accumulation time is applied to sequential readout in which each pixel 30 of the pixel array unit 12 is sequentially scanned by the row scanning unit 13 in units of rows. However, the present invention can also be applied to thinning readout. Here, thinning readout is a technique of skipping pixel rows at a constant row cycle and reading signals from the pixels of the remaining pixel rows. By using this thinning readout, the number of vertical readouts (number of rows / number of lines) can be reduced, so that high-speed imaging can be realized.

  Also when applied to this thinning readout, an anti-blooming shutter operation is performed on each photodiode 31 of all shared pixels at the same time (or in advance) when signals are read from the pixels in the pixel row selected as the readout row. You can do it.

  For example, FIG. 11 shows the timing relationship between the electronic shutter, the anti-blooming shutter, and the readout operation in the case of 1/3 decimation readout in which two rows are skipped in units of 3 rows and signals are read from the remaining one row.

  In FIG. 11, the time between the ◯ mark and the □ mark in the same pixel row indicates the signal charge accumulation time (1H in this example). Further, the time between the ◯ mark and the □ mark in adjacent pixel rows indicates the timing difference between the signal readout and the electronic shutter in the adjacent pixel rows.

  In the case of 1/3 thinning readout, the pixel rows of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row,... Are sequentially selected as readout rows. Here, when the 12th row is selected as the readout row, for example, the electronic shutter operation of the 12th row is performed 1H before the readout operation of the 12th row.

  Then, the anti-blooming shutter operation of the shared pixels, that is, the pixels of the 14th row is performed at the same timing as the electronic shutter operation of the 12th row. Further, the anti-blooming shutter operation is performed on the other shared pixels, that is, the pixels on the 13th and 15th rows, at the electronic shutter timing before the electronic shutter operation on the 12th row.

  As a result, when a signal is read from one of the four pixels sharing the FD unit 35, an anti-blooming shutter operation is performed on each photodiode 31 of all the shared pixels before reading the signal from the pixel. It will be. In this example, as shown in FIG. 11 surrounded by a broken line, when a signal is read out from a pixel on the 12th row, the pixel on the 14th row is read at the electronic shutter timing of the pixel, and the electronic shutter timing before that is read. The anti-blooming shutter operation is performed on the pixels in the 13th and 15th rows.

  12, 13, and 14 show timing relationships of the electronic shutter, anti-blooming shutter, and readout operations in the case of other thinning readout. 12, 13, and 14, the time between the ◯ mark and the □ mark in the same pixel row indicates the signal charge accumulation time (1H in this example). Further, the time between the ◯ mark and the □ mark in adjacent pixel rows indicates the timing difference between the signal readout and the electronic shutter in the adjacent pixel rows.

  FIG. 12 is an explanatory diagram of an anti-blooming shutter operation in the case of 2/8 decimation readout. FIG. 13 is an explanatory diagram of the anti-blooming shutter operation in the case of 2/15 decimation readout. FIG. 14 is an explanatory diagram of the anti-blooming shutter operation in the case of 1/5 decimation readout.

  As is apparent from FIGS. 11 to 14, the number of anti-blooming shutters required for each thinning operation is different. However, in any of the thinning-out readouts, the pixels 31 sharing the FD unit 35 are used as a unit before reading out signals from the pixels in the readout row (or simultaneously) with respect to the photodiodes 31 of all the shared pixels. A blooming shutter operation is performed.

  Thus, by applying the technique according to the present embodiment to the thinning-out readout, high-speed imaging can be realized while maintaining the linearity of the signal output depending on the accumulation time. Here, when the technique according to the present embodiment is applied to thinning-out reading, the number of shutters of the anti-blooming shutter (the number of resets of the photodiode 31) is set to be the same at the electronic shutter timing of each reading row. (Refer to FIGS. 11 to 14).

  By setting the number of shutters of the anti-blooming shutter at the electronic shutter timing of each readout row to the same number, it is possible to suppress the occurrence of so-called shutter steps, and thus a good captured image can be obtained. Here, the shutter step refers to a phenomenon in which a horizontal band is generated on the captured image due to the shutter operation being stopped during the vertical video period, and the horizontal band moves up and down according to the shutter speed.

  In the above embodiment, the case where the present invention is applied to a CMOS image sensor has been described as an example, but the present invention is not limited to application to a CMOS image sensor. That is, the present invention is applicable to all XY address type solid-state imaging devices in which unit pixels that detect electric charges according to the amount of visible light as physical quantities and output them as electric signals are arranged in a matrix.

The solid-state imaging device may be formed as a single chip, or may be in a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.

<6. Electronic equipment>
The solid-state imaging device according to the present invention can be mounted and used in all electronic devices that use a solid-state imaging device for an image capturing unit (photoelectric conversion unit). Examples of the electronic device include an imaging device (camera system) such as a digital still camera and a video camera, a portable terminal device having an imaging function such as a mobile phone, and a copying machine using a solid-state imaging device for an image reading unit. Note that a camera module mounted on an electronic device may be an imaging device.

(Imaging device)
FIG. 15 is a block diagram illustrating an example of a configuration of, for example, an imaging apparatus which is one of electronic apparatuses according to the present invention. As shown in FIG. 15, an imaging apparatus 100 according to the present invention includes an optical system including a lens group 101 and the like, an imaging element 102, a DSP circuit 103 that is a camera signal processing unit, a frame memory 104, a display apparatus 105, and a recording apparatus 106. The operation system 107 and the power supply system 108 are included. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.

  The lens group 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 102. The imaging element 102 converts the amount of incident light imaged on the imaging surface by the lens group 101 into an electrical signal in units of pixels and outputs the electrical signal. As the imaging element 102, a solid-state imaging device such as a CMOS image sensor according to the above-described embodiment can be used.

  The display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 102. The recording device 106 records a moving image or a still image captured by the image sensor 102 on a recording medium such as a video tape or a DVD (Digital Versatile Disc).

  The operation system 107 issues operation commands for various functions of the imaging apparatus under operation by the user. The power supply system 108 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

Such an imaging apparatus 100 is applied to a camera module for a mobile device such as a video camera, a digital still camera, or a mobile phone. In this imaging apparatus 100, the CMOS image sensor according to the above-described embodiment is used as the imaging element 102, so that the CMOS image sensor can maintain the linearity of the signal output depending on the accumulation time, thereby providing a good captured image. it can.

  DESCRIPTION OF SYMBOLS 10 ... CMOS image sensor, 11 ... Semiconductor substrate (chip), 12 ... Pixel array part, 13 ... Row scanning part, 14 ... Column processing part, 15 ... Column scanning part, 16 ... System control part, 17 ... Pixel drive line, 18 ... vertical signal line, 30 (30-1 to 30-4) ... pixel, 31 (31-1 to 31-4) ... photodiode, 32 (32-1 to 32-4) ... transfer transistor, 33 ... reset Transistor, 34 ... Amplification transistor, 35 ... FD (floating diffusion) part

Claims (7)

A photoelectric conversion unit, a transfer transistor for transferring photoelectrically converted charges in the charge-voltage converter in the photoelectric conversion unit, and a reset transistor, the charge overflowing from the photoelectric conversion unit, the transfer transistor, the charge voltage A pixel array unit having a structure in which a plurality of pixels are arranged in a matrix, and at least the charge-voltage conversion unit is shared by a plurality of pixels, the conversion unit and the reset transistor being discarded to a selected power supply line;
The selected power supply lines in a plurality of rows including a row for reading a signal from each pixel of the pixel array unit are scanned at a first voltage level and a second voltage level alternately to make a selection state, and the selected power supply lines for multiple lines of selected state, before reading out signals from pixels on the read row, a first pixel in the readout row, and the second pixel sharing the pixel and the charge-voltage converter of the read row, the readout A row scanning unit that resets charges in the photoelectric conversion unit with respect to pixels in a row and a third pixel that does not share the charge-voltage conversion unit;
The pixel has a back-illuminated pixel structure that takes in incident light from the side opposite to the side where the wiring layer is arranged with respect to the photoelectric conversion unit,
The row scanning unit, among the selected power supply line of the multiline selected, with the line containing the pixel to be reset, changing the potential of the selected power supply line from the first voltage level to the second voltage level , before SL by changing the potential of the transfer transistor and the reset transistor together on to the selected power supply line from the second voltage level to said first voltage level, by turning off both of the reset transistor and the transfer transistor, Charges in the photoelectric conversion unit are simultaneously applied to the same number of pixels in the combination of the first pixel and the second pixel, or the combination of the first pixel, the second pixel, and the third pixel. Reset,
Solid-state imaging device. The row scanning unit accumulates for a short time until the accumulation time is (n−1) H, where n is the number of pixels sharing the charge-voltage conversion unit (n is an integer of 2 or more) and the horizontal scanning period is H. The charge in the photoelectric conversion unit is reset at the time of
The solid-state imaging device according to claim 1. The row scanning unit resets the charge in the photoelectric conversion unit by sweeping out the charge in the photoelectric conversion unit via the charge-voltage conversion unit by the transfer transistor .
The solid-state imaging device according to claim 1 or 2. The row scanning unit resets the charge in the photoelectric conversion unit at a timing of an electronic shutter that defines a signal charge accumulation time in the first pixel of the readout row;
The solid-state imaging device according to claim 3. The row scanning unit skips pixel rows at a constant row period, and performs thinning readout for reading signals from the pixels of the remaining pixel rows.
The solid-state imaging device according to claim 4. A photoelectric conversion unit, a transfer transistor for transferring photoelectrically converted charges in the charge-voltage converter in the photoelectric conversion unit, and a reset transistor, the charge overflowing from the photoelectric conversion unit, the transfer transistor, the charge voltage A pixel array unit having a structure in which a plurality of pixels are arranged in a matrix and disposed at least in the selected power supply line through the conversion unit and the reset transistor , and includes at least the charge-voltage conversion unit among a plurality of pixels, In driving the back-illuminated solid-state imaging device that takes in incident light from the side opposite to the side where the wiring layer is arranged with respect to the photoelectric conversion unit,
The selected power supply lines in a plurality of rows including a row for reading a signal from each pixel of the pixel array unit are scanned at a first voltage level and a second voltage level alternately to make a selection state, and the selected power supply lines for multiple lines of selected state, before reading out signals from pixels on the read row, a first pixel in the readout row, and the second pixel sharing the pixel and the charge-voltage converter of the read row, the readout Resetting the charge in the photoelectric conversion unit for the pixels in the row and the third pixel not sharing the charge-voltage conversion unit,
Upon the reset, among the selected power supply line of the multiline selected, with the line containing the pixel to be reset, changing the potential of the selected power supply line from the first voltage level to the second voltage level, before Both the transfer transistor and the reset transistor are turned on to change the potential of the selected power supply line from the second voltage level to the first voltage level , and both the transfer transistor and the reset transistor are turned off . The charge in the photoelectric conversion unit is simultaneously reset for the same number of pixels by a combination of one pixel and the second pixel, or a combination of the first pixel, the second pixel, and the third pixel. ,
A driving method of a solid-state imaging device. A photoelectric conversion unit, a transfer transistor for transferring photoelectrically converted charges in the charge-voltage converter in the photoelectric conversion unit, and a reset transistor, the charge overflowing from the photoelectric conversion unit, the transfer transistor, the charge voltage A pixel array unit having a structure in which a plurality of pixels are arranged in a matrix, and at least the charge-voltage conversion unit is shared by a plurality of pixels, the conversion unit and the reset transistor being discarded to a selected power supply line;
The selected power supply lines in a plurality of rows including a row for reading a signal from each pixel of the pixel array unit are scanned at a first voltage level and a second voltage level alternately to make a selection state, and the selected power supply lines for multiple lines of selected state, before reading out signals from pixels on the read row, a first pixel in the readout row, and the second pixel sharing the pixel and the charge-voltage converter of the read row, the readout A row scanning unit that resets charges in the photoelectric conversion unit with respect to pixels in a row and a third pixel that does not share the charge-voltage conversion unit;
The pixel has a back-illuminated pixel structure that takes in incident light from the side opposite to the side where the wiring layer is arranged with respect to the photoelectric conversion unit,
The row scanning unit, among the selected power supply line of the multiline selected, with the line containing the pixel to be reset, changing the potential of the selected power supply line from the first voltage level to the second voltage level , before SL by changing the potential of the transfer transistor and the reset transistor together on to the selected power supply line from the second voltage level to said first voltage level, by turning off both of the reset transistor and the transfer transistor, Charges in the photoelectric conversion unit are simultaneously applied to the same number of pixels in the combination of the first pixel and the second pixel, or the combination of the first pixel, the second pixel, and the third pixel. Reset,
An electronic device having a solid-state imaging device.

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