JP5365381B2 - Circuit board inspection method, circuit board inspection device - Google Patents

Description

  The present invention relates to a method and an apparatus for inspecting a circuit board having an IC component mounted on a wiring board, and more particularly, to an inspection method and an inspection apparatus for a circuit board when the IC component is compatible with a serial communication function. About.

  In recent years, so-called wiring boards with built-in components in which components are built in an insulating plate have been actively researched and developed. These wiring boards require inspection as wiring boards with components in the process of production, and this inspection includes detection of disconnection or short-circuit failure in connection between the components and the wiring pattern.

  The inspection to check the connection state between the component and the wiring pattern should be performed using the surface layer pattern in the wiring board design where the pattern that is the same node as the land where the component terminal is connected and mounted appears as the surface layer pattern. Can do. That is, the connection state can be inspected for the wiring board finished in the final form.

  However, even in such a case, compared to the case where the component is a two-terminal, for example, a resistor, a capacitor, an inductor, etc., in the case of an integrated circuit element (IC) having a considerably larger number of terminals, the mounting Inspection of disconnection and short circuit failure is not easy. One of the reasons is that there are various characteristics between ICs and between terminals, and it is not possible to detect disconnection or short-circuit failure in mounting by simply measuring impedance like resistors, capacitors and inductors. is there.

  Note that, for example, the following Patent Documents 1 to 3 are cited as publicly known documents that refer to a method for inspecting an electrical connection state of a wiring board having components. Neither of these describes any viewpoints of interest in the present application.

JP 2003-197849 A JP 2005-5692 A JP 2006-344847 A

  The present invention provides a method and apparatus for inspecting a circuit board having an IC component mounted on a wiring board, and can simplify the connection inspection of the IC component by using the serial communication function of the IC component. It is an object of the present invention to provide a circuit board inspection method and inspection apparatus.

In order to solve the above problems, a circuit board inspection method according to an aspect of the present invention includes a first clock input terminal and a first serial data input / output terminal, and a clock having a predetermined frequency is the first clock. As the first predetermined serial data synchronized with the clock of the predetermined frequency is input to the first serial data input / output terminal to the first clock input terminal, the first serial data input / output terminal first And a second clock input terminal and a second serial data input / output terminal, and the clock having the predetermined frequency is supplied to the second clock input terminal. As the second predetermined serial data different from the first predetermined serial data is input to the second serial data input / output terminal, respectively. Serial from the data output terminal and a second IC that outputs a second acknowledgments are mounted, the first IC is, current sink further has a terminal, and the predetermined frequency of the clock is the first As the third predetermined serial data, which is different from the first and second predetermined serial data, is input to the first serial data input / output terminal in synchronization with the clock having the predetermined frequency. A first wiring pattern for electrically connecting the first clock input terminal and the second clock input terminal , an IC for sucking a current of a predetermined magnitude from the current suction terminal toward the inside ; a second wiring pattern that connects electrically the first serial data input terminal and the second serial data output terminal, said current intake of the first IC An inspection apparatus intended for the circuit board with the write terminal and a third wiring pattern electrically conductive mintues first test needle to the circuit board and electrically connected to the first wiring pattern against and said second conducting wiring pattern abuts the second inspection needle into the circuit board, further wherein the third third abutment Ru probe testing needle to the circuit board and electrically connected to the wiring pattern A first signal generator for generating a signal to supply a clock of the predetermined frequency to the first inspection needle and simultaneously supply the first predetermined serial data to the second inspection needle; A first determination unit that determines whether or not the first recognition signal has been detected by a second inspection needle; and a clock having a predetermined frequency is supplied to the first inspection needle and simultaneously the second inspection needle A signal to supply the second predetermined serial data to A second signal generating unit, a second determination unit for determining whether the second recognition signal is detected by the second inspection needle, and a predetermined frequency for the first inspection needle. A third signal generator for generating a signal for supplying the third predetermined serial data to the second inspection needle at the same time as supplying a clock; and a current of the predetermined magnitude via the third inspection needle And a third determination unit for determining whether or not the image can be detected .

That is, in this inspection method, the predetermined first and second ICs are mounted, and a circuit board provided with the predetermined first and second wiring patterns is an inspection target. Each of the first and second ICs has a clock input terminal and a serial data input / output terminal. A clock having a predetermined frequency is input to the clock input terminal, and predetermined serial data synchronized with the clock having the predetermined frequency is input / output to the serial data. A recognition signal is output from the serial data input / output terminal as it is input to each terminal. As an example of such an IC, for example, an IC corresponding to so-called I ² C (inter-integrated circuit) can be cited. I ² C is a serial communication method (protocol) between ICs proposed by Philips.

  Two (or more) ICs having the above-described functions are mounted on the circuit board to be inspected, and the clock line and serial data line connected to the IC are defined by the first and second wiring patterns. Each is shared between ICs. Therefore, the inspection is started by conducting to the first wiring pattern and abutting the first inspection needle against the circuit board and conducting to the second wiring pattern and abutting the second inspection needle against the circuit board.

  Next, whether or not the first recognition signal is detected by the second inspection needle by supplying a clock having a predetermined frequency to the first inspection needle and simultaneously supplying the first predetermined serial data to the second inspection needle. Determine. As a result, the connection inspection relating to the clock input terminal and the serial data input / output terminal of the first IC is performed. Next, a clock having a predetermined frequency is supplied to the first inspection needle, and at the same time, second predetermined serial data is supplied to the second inspection needle, and whether or not the second recognition signal can be detected by the second inspection needle. Determine whether. As a result, the connection inspection relating to the clock input terminal and the serial data input / output terminal of the second IC is performed.

  The same applies when three or more ICs having the above functions are mounted on the circuit board. Since this inspection method uses the serial communication function of the IC component, the configuration of multiple IC components can be reduced without complicating the configuration by changing the contact position of the inspection needle or pattern separation on the circuit board. It is possible to simplify the connection inspection.

A circuit board inspection apparatus according to another aspect of the present invention includes a first clock input terminal and a first serial data input / output terminal, and a clock having a predetermined frequency is the first clock input terminal. In addition, as the first predetermined serial data synchronized with the clock having the predetermined frequency is input to the first serial data input / output terminal, a first recognition signal is output from the first serial data input / output terminal. And a second clock input terminal and a second serial data input / output terminal, and the clock having the predetermined frequency is synchronized with the clock having the predetermined frequency at the second clock input terminal. As the second predetermined serial data different from the first predetermined serial data is input to the second serial data input / output terminal, the second serial data A second IC is mounted to output a second recognition signal from an output terminal, said first IC further includes a current sink terminal, and the clock of the predetermined frequency is the first clock input terminal In addition, as the third predetermined serial data different from the first and second predetermined serial data, which is synchronized with the clock of the predetermined frequency, is input to the first serial data input / output terminal, the current suction is performed. An IC that sucks in a current of a predetermined magnitude from the terminal to the inside; a first wiring pattern that electrically connects the first clock input terminal and the second clock input terminal; and the first serial a second wiring pattern that connects the data input-output terminal and the second serial data input and output terminals electrically, electrical said current sink terminal of the first IC An inspection apparatus directed to the third circuit board and a wiring pattern for conduction, the first to the abutment and the second first test needle to the circuit board electrically connected to the wiring pattern a second abutting the test needle, further wherein the third third probe section Ru abutted inspection needle on the circuit board and electrically connected to the wiring pattern on the circuit board and electrically connected to the wiring pattern, the first A first signal generator for generating a signal to supply the first predetermined serial data to the second inspection needle at the same time as supplying the clock of the predetermined frequency to the inspection needle, and to the second inspection needle A first determination unit that determines whether or not the first recognition signal has been detected; and a clock having the predetermined frequency is supplied to the first inspection needle and the second predetermined determination is simultaneously applied to the second inspection needle. A second signal generator that generates a signal to supply serial data A live part, a second determination part for determining whether the second recognition signal has been detected on the second inspection needle, and a clock of the predetermined frequency supplied to the first inspection needle at the same time A third signal generator for generating a signal to supply the third predetermined serial data to the second inspection needle, and whether or not the predetermined magnitude of current has been detected via the third inspection needle And a third determination unit for determining whether or not.

  This inspection apparatus is an apparatus for carrying out the above-described inspection method. Therefore, the predetermined first and second ICs are mounted, and the predetermined first and second wiring patterns are further provided. Inspected circuit boards.

  In order to carry out the above inspection method, first, the first wiring pattern is conducted and the first inspection needle is abutted against the circuit board, and the second wiring pattern is conducted and the second inspection needle is applied to the circuit board. It has a probe part to abut.

  In addition, a first signal generator for generating a signal to supply a clock having a predetermined frequency to the first inspection needle and simultaneously supplying first predetermined serial data to the second inspection needle, and a second inspection needle And a first determination unit that determines whether or not the first recognition signal has been detected. Thereby, the connection inspection regarding the clock input terminal and the serial data input / output terminal of the first IC can be performed.

  Further, a second signal generator for generating a signal to supply a clock having a predetermined frequency to the first inspection needle and simultaneously supplying second predetermined serial data to the second inspection needle, and a second inspection needle And a second signal generation unit that determines whether or not the second recognition signal has been detected. Thereby, the connection inspection regarding the clock input terminal and the serial data input / output terminal of the second IC can be performed.

  If this inspection device is used, since the serial communication function of the IC component is used, the configuration of multiple IC components can be reduced without complicating the configuration by changing the contact position of the inspection needle or separating the patterns on the circuit board. It is possible to simplify the connection inspection.

  According to the present invention, it is possible to provide a circuit board inspection method and inspection apparatus capable of simplifying the connection inspection of an IC component using the serial communication function of the IC component mounted on the wiring board. .

The typical sectional view showing the exemplary composition of the circuit board which is the inspection object of the inspection method which is one embodiment of the present invention. The exemplary schematic diagram which shows the connection and arrangement | positioning relationship of the pattern around mounted IC in the circuit board which is a test object of the test | inspection method which is one Embodiment of this invention. Protocol diagram for illustrating the ^{I 2 C (inter-integrated circuit} ) function to test object serving as a circuit board inspection method according to an embodiment includes the implementation of IC of the present invention. The block diagram which shows the structure of the test | inspection apparatus which concerns on one Embodiment of this invention. The flowchart which shows the operation | movement flow of the test | inspection apparatus shown in FIG. The block diagram which shows the structure of the test | inspection apparatus for standby current test | inspection. The block diagram which shows the aspect which enforces the inspection method which is one Embodiment of this invention. The block diagram which shows the aspect which enforces the inspection method which is another embodiment of this invention.

In one aspect of the present invention, the first IC of the circuit board further includes a current sink terminal, and the clock having the predetermined frequency is synchronized with the clock having the predetermined frequency at the first clock input terminal. As the third predetermined serial data different from the first and second predetermined serial data is input to the first serial data input / output terminal, respectively, the current sink terminal has a predetermined size toward the inside. The circuit board includes a third wiring pattern that is electrically connected to the current suction terminal of the IC, and is electrically connected to the third wiring pattern. A third inspection needle is abutted, the clock of the predetermined frequency is supplied to the first inspection needle, and the third predetermined serial data is supplied to the second inspection needle at the same time, It intends further rows that current of the predetermined magnitude through the test needle to determine whether or not detected.

That is , in the circuit board to be inspected, the first IC further has a current sink terminal, and a clock having a predetermined frequency is synchronized with the clock having the predetermined frequency at the first clock input terminal. As the predetermined serial data is input to the first serial data input / output terminal, the IC absorbs a predetermined amount of current from the current suction terminal toward the inside. The circuit board is provided with a third wiring pattern that conducts to the current sink terminal.

Therefore, the third inspection needle is brought into contact with the circuit board through the third wiring pattern, and then a clock having a predetermined frequency is supplied to the first inspection needle and at the same time, a third predetermined needle is supplied to the second inspection needle. Serial data is supplied, and it is determined whether or not a current of a predetermined magnitude has been detected via the third inspection needle. As a result, the connection inspection relating to the current sink terminal of the first IC is performed. Thus, if it has a specific function, such as that having a suction IC current terminal, it intends concisely line connection test for the terminal by using this.

Further, even if the state like as an inspection device, according to the above inspection method, the first IC of the circuit board further includes a current sink terminal, and the clock of the predetermined frequency is the first clock As the third predetermined serial data different from the first and second predetermined serial data, which is synchronized with the clock of the predetermined frequency, is input to the first serial data input / output terminal, An IC for sucking a current of a predetermined magnitude from a current suction terminal toward the inside, wherein the circuit board includes a third wiring pattern electrically connected to the current suction terminal of the IC; However, the third inspection needle is brought into contact with the circuit board by conducting to the third wiring pattern, and the clock having the predetermined frequency is supplied to the first inspection needle at the same time. A third signal generator for generating a signal to supply the third predetermined serial data to the second inspection needle, and whether or not the current of the predetermined magnitude can be detected via the third inspection needle Furthermore it and a third determination unit determines.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 is a schematic cross-sectional view showing an exemplary configuration of a circuit board to be inspected by an inspection method according to an embodiment of the present invention. The structure of the circuit board to be inspected is not limited to this example, but here, it will be described as an example of a specific structure that is currently available. This circuit board is a circuit board on which at least two ICs are mounted. Here, the “circuit board” is not a wiring board on which no parts are mounted, but a wiring board on which some parts are mounted (including the case where they are built in). This includes the case of a wiring board in a state (= semi-finished product) before all components are mounted.

  This circuit board 100 includes insulating layers 11, 12, 13, 14, 15 (which constitute an insulating plate), wiring layers (wiring patterns) 21, 22, 23, 24, 25, 26 (= 6 layers in total), Interlayer connectors 31, 32, 34, and 35, through-hole conductors 33, ICs 41 and 42, solders 51 and 52, and solder resists 61 and 62 are included.

  The ICs 41 and 42 are, for example, semiconductor components based on a wafer level chip scale package, and each includes at least a semiconductor chip and grid-shaped terminals 41a and 42a formed on the semiconductor chip. The terminals 41a and 42a are terminals provided by rearranging their positions while being electrically conducted through the rewiring layer from the terminal pads originally possessed by the semiconductor chip. The ICs 41 and 42 are mounted on the land pattern 22a of the inner wiring layer 22 via solders 51 and 52, respectively, by the same surface mounting technology as that for chip components.

  The wiring layers 21 and 26 are wiring layers on both main surfaces as circuit boards, and various components (not shown) can be mounted thereon. For such mounting, the wiring layers 21 and 26 include lands for component mounting, and also have land patterns for inspecting the connection state of the ICs 41 and 42. However, the latter land pattern may be omitted for the purpose only by diverting the component mounting land. Solder resists 61 and 62 functioning as protective layers are formed on both main surfaces of the wiring layers 21 and 26 excluding these land portions (thickness is about 20 μm, for example). An Ni / Au plating layer (not shown) with high corrosion resistance may be formed on the surface layer of the land portion.

  The wiring layers 22, 23, 24, and 25 are inner wiring layers, and the insulating layer 11 is disposed between the wiring layer 21 and the wiring layer 22, and the insulating layer 12 is disposed between the wiring layer 22 and the wiring layer 23, respectively. However, the insulating layer 13 is between the wiring layer 23 and the wiring layer 24, the insulating layer 14 is between the wiring layer 24 and the wiring layer 25, and the insulating layer 15 is between the wiring layer 25 and the wiring layer 26. The wiring layers 21 to 26 are spaced apart from each other. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil pattern having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, each having a thickness of 100 μm, for example, only the insulating layer 13 has a thickness of, for example, 300 μm, excluding the insulating layer 13. In particular, the insulating layer 13 has openings at positions corresponding to the built-in ICs 41 and 42, and provides a space for embedding the ICs 41 and 42. The insulating layers 12 and 14 are deformed so as to fill the space inside the through-hole conductor 33 of the insulating layer 13 and the opening of the insulating layer 13 for the built-in ICs 41 and 42, and become voids inside. There is no space.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer insulator 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 35 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  The interlayer connectors 31, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, respectively, and depend on the manufacturing process in the axial direction (shown in FIG. 1). The diameter changes in the upper and lower stacking directions). The diameter is, for example, 200 μm on the thick side.

  With the structure described above, the terminals 41a and 42a of the ICs 41 and 42 (from the terminals 41a and 42a) are connected via the wiring patterns by the wiring layers 21 to 26, the interlayer connectors or the through-hole conductors 31 to 35, respectively. Thus, electrical connection is possible from any other wiring layer (to the wiring layer) as necessary. The electrical connection between the terminals 41a and 42a of the ICs 41 and 42 can also be made as needed via the wiring pattern by the wiring layers 21 to 26, the interlayer connector or the through-hole conductors 31 to 35.

  Next, connection and arrangement relationships of patterns around the ICs 41 and 42 on the circuit board shown in FIG. 1 will be described with reference to FIG. FIG. 2 is an exemplary schematic diagram showing a connection and arrangement relationship of patterns around mounted ICs on a circuit board to be inspected by the inspection method according to the embodiment of the present invention. In FIG. 2, the same or equivalent components (ICs 41 and 42) as those shown in FIG.

The circuit board that is the target of the inspection method of the present embodiment is based on the premise that ICs corresponding to I ² C (inter-integrated circuit) are incorporated as ICs 41 and 42. First, general I ² C will be described with reference to FIG. FIG. 3 is a protocol diagram for explaining an I ² C function provided in an IC mounted on a circuit board to be inspected by an inspection method according to an embodiment of the present invention.

If the IC has an I ² C function, serial data communication can be performed between the ICs. Only two data lines (SDA) and a clock line (SCL) are necessary for data communication. The signal on SDA is output in synchronization with the clock on SCL. Among the ICs connected to each other, there is an IC as a master, and the rest are slaves. Each slave IC is given an address of 7 bits. The clock is always generated by the master.

  Addressing from the master to the slave is performed by a signal format on the SDA as shown in FIG. A6 to A0 are unique addresses for designating any one of the slaves, RW may be either R (= read) or W (= write) depending on the case, and ACK (= acknowledgement) is an acknowledge signal from the slave IC ( (Acknowledge signal) is a reply period.

  In the case of other data exchange between the master and the slave, the signal format on the SDA as shown in FIG. D7 to D0 are data, and ACK is a return period of the recognition signal from the IC of the transmission destination (slave or master).

  The flow in the case of transmitting data from the master to the slave is as shown in FIG. That is, first, when outputting from the master in the order of the slave address and W, the corresponding slave outputs ACK. Next, the master outputs data, and the corresponding slave outputs ACK. Thereafter, data and ACK are repeated as many times as the number of data to be output. Here, the “data” may be a command to the slave, narrowly defined data (numerical value), or the like.

The flow in the case of transmitting data from the slave to the master is as shown in FIG. That is, also in this case, if the master first outputs in the order of the slave address and R, the corresponding slave outputs ACK. Next, the slave outputs data corresponding to, for example, a command transmitted in advance, and the master outputs ACK in response to this. Thereafter, data and ACK are repeated as many times as the number of data to be output. As described above, I ² C has the initiative of communication on the side of the IC that is the master for both transmission and reception. The communication speed is 100 kbps or 400 kbps.

  Returning to FIG. 2, the IC 41 and the IC 42 are both implemented as slave ICs. The IC functioning as a master does not exist in this circuit board 100 (at least in the circuit board 100 at this stage).

The IC 41 is, for example, an EEPROM (electrical erasable programmable read only memory) compatible with I ² C. The terminal has a five-terminal configuration of terminals 1a to 1e (corresponding to the terminal 41a in FIG. 1). The breakdown includes a ground terminal (GND) 1a, a power supply terminal (VCC) 1b, an SCL terminal 1c, an SDA terminal 1d, and writing. Forbidden terminal (WP) 1e.

The IC 42 is, for example, a current output driver that supports I ² C. The terminals have a 6-terminal configuration of terminals 2a to 2f (corresponding to the terminal 42a in FIG. 1), and are broken down into a ground terminal (GND) 2a, a power supply terminal (VDD) 2b, an SCL terminal 2c, an SDA terminal 2d, A switch terminal (SW) 2e and a current output terminal (ISINK) 2f are provided. The current output terminal 2f is a terminal for generating a current having a predetermined magnitude in the direction of sucking into the IC 42 as a current output.

In the circuit board 100, the IC 41 and IC 42 are provided with wiring patterns 3a to 3g corresponding to the terminals 1a to 1e and the terminals 2a to 2f, respectively, as shown in FIG. Here, the wiring pattern 3d is a common pattern of SCL for I ² C, and the wiring pattern 3e is also a common pattern of SDA.

  In such a circuit board 100 with built-in IC41 and IC42, the SCL wiring pattern 3d and the SDA wiring pattern 3e are effective when the point of view is to perform a connection inspection of whether the IC41 and 42 are normally mounted. Available to: That is, these are patterns commonly connected to a plurality of ICs. If a function corresponding to the master is provided in the inspection device, an address is designated from the inspection device via the wiring patterns 3d and 3e, and the inspection device receives an ACK. Thus, the soundness of connection can be confirmed for each IC. At this time, the connection inspection of a plurality of ICs can be simplified without changing the contact position of the inspection needle for each IC to be inspected or complicating the configuration by pattern separation on the circuit board 100.

  Then, next, FIG. 4 is a block diagram showing a configuration of an inspection apparatus according to an embodiment of the present invention. 4 shows a block configuration of the inspection apparatus (main body) 70, inspection needles 9a to 9g to be abutted for inspection against the pattern around the IC shown in FIG. 2, and the inspection apparatus (main body) 70. And the connection relationship between the inspection needles 9a to 9g.

  As shown in FIG. 4, the inspection device (main body) 70 includes a signal generation unit 71, an ACK determination unit 72, a current value determination unit 73, an inspection device power supply unit 74, and a write protect setting unit 75. The signal generator 71 includes a clock generator 71a and a slave address (or command) generator 71b.

  The clock generation unit 71a can output a clock to the pattern 3d through the inspection needle 9d that is abutted against the SCL wiring pattern 3d. The slave address (or command) generation unit 71b can output a slave address (or command) to the pattern 3e through the inspection needle 9e that is abutted against the SDA wiring pattern 3e. The ACK determination unit 72 can detect the ACK signal output to the SDA wiring pattern 3e through the inspection needle 9e that is abutted against the pattern 3e. The current value determination unit 73 can detect the current value flowing through the pattern 3f (from the IC terminal 2f) via the inspection needle 9f that is abutted against the pattern 3f.

  The inspection device power supply unit 74 is an internal power supply device of the inspection device (main body) 70, and makes the potential of the pattern 3a and the GND potential inside the device common by the inspection needle 9a abutted against the GND wiring pattern 3a. Further, a power supply potential is supplied to the pattern 3b via the inspection needle 9b abutted against the power supply wiring pattern 3b, and a power supply potential is supplied to the pattern 3c via the inspection needle 9c abutted against the power supply wiring pattern 3c. can do. The write protect setting unit 75 can supply a potential indicating whether or not writing is prohibited to the pattern 3g through the inspection needle 9g that is abutted against the wiring pattern 3g.

  Hereinafter, the operation of the inspection apparatus 70 will be described with reference to FIG. FIG. 5 is a flowchart showing an operation flow of the inspection apparatus shown in FIG.

  First, the inspection needles 9a to 9g are probed with respect to the circuit board 100 (step 81). Specifically, as shown in FIG. 4, the test needles 9a to 9g are abutted against the wiring patterns 3a to 3g. A cable is connected between the inspection needles 9a to 9g and the inspection device (main body) 70, for example.

  Next, a clock is generated by the clock generation unit 71a, and an address of the IC 41 as predetermined serial data is generated by the slave address generation unit 71b (step 82). Thereby, if the connection state of the IC 41 is normal, the ACK determination unit 72 can receive the ACK issued by the IC 41 (step 83). When ACK cannot be received sufficiently, it is determined that the connection state of the IC 41 is bad. Strictly speaking, this inspection determines the quality of the connection state for the four terminals 1a to 1d. This is because ACK is not normally generated even when the connection of the power ground terminals 1a and 1b of the IC 41 is poor.

  In addition, it can respond separately after this to determine the quality of the connection state with respect to the terminal 1e (not shown in FIGS. 4 and 5 and omitted). That is, whether or not the write protection is performed from the write protection setting unit 75 can be confirmed by writing and reading data to and from the IC 41 using SCL and SDA.

  Further, the connection test for the IC 41 can be developed and advanced, and further the function test of the IC 41 can be performed (not shown in FIG. 5). That is, since the IC 41 is an EEPROM, data is written to and read from the IC 41 using the SCL and SDA following the above-described connection inspection. Both reading functions can be inspected. Note that since the inspection data generally needs to be erased after the inspection, the erase data is written and read, and finally, the coincidence is confirmed.

  Returning to FIG. 5, next, the clock generator 71a generates a clock, and the slave address generator 71b generates an address of the IC 42 as predetermined serial data (step 84). Thereby, if the connection state of the IC 42 is normal, the ACK determination unit 72 can receive the ACK issued by the IC 42 (step 85). When ACK cannot be received sufficiently, it is determined that the connection state of the IC 42 is defective. Strictly speaking, this inspection determines whether the connection state of the four terminals 2a to 2d is good or bad. This is because ACK is not normally generated even when the connection between the power ground terminals 2a and 2b of the IC 42 is poor.

  In addition, it can respond separately after that to judge the quality of the connection state of the power switch terminal 2e (not shown in FIG. 5, omitted). That is, in the case of the IC 42, when the power switch terminal 2e is in a poor connection (open), the current is not normally output from the current output terminal 2f. Therefore, the inspection in steps 86 and 87 described below is performed. Can be substituted.

  Therefore, next, a clock is generated by the clock generation unit 71a, and a command (command corresponding to the value of the output current to be generated by the IC 42) as predetermined serial data is generated by the command generation unit 71b (step 86). ). Thus, if the connection state of the current output terminal 2f of the IC 42 is normal, the current value determination unit 73 can detect the current corresponding to the command via the pattern 3f and the inspection needle 9f (step 87). . If the detected current does not correspond to the command, it is determined that the connection state of the current output terminal 2f of the IC 42 is defective (or the connection state of the power switch terminal 2e is poor).

  It is to be noted that the connection inspection for the IC 42 can be developed and advanced, and further the functional inspection of the IC 42 can be performed (not shown in FIG. 5). That is, the IC 42 is configured to input a command (digital value) corresponding to the current value to be output from the current output terminal 2d from the SDA terminal 2d. Several commands are generated in order from the unit 71 b, and each output current value is determined by the current value determination unit 73. Thereby, the function inspection (inspection of current output) of the IC 42 can be performed.

  As described above, the connection determination regarding the ICs 41 and 42 is completed. Thus, the probing of the inspection needles 9a to 9g with respect to the circuit board 100 is released (step 88), and the inspection is completed. As described above, when this inspection apparatus 70 is used, the serial communication function of the ICs 41 and 42 is used, so that the configuration is complicated by changing the contact position of the inspection needles 9d and 9e, pattern separation on the circuit board 100, and the like. It is possible to simplify the connection inspection of a plurality of ICs (ICs 41 and 42) without inviting them.

This effect is further increased when three or more I ² C compatible ICs are mounted (built-in mounting) on the circuit board 100 (that is, when the mounting is more complicated). Here, since I ² C is a standard that uses a frequency of 1 MHz or less at most, the high-speed response of the inspection device 70 is sufficient, and the connection between the inspection needles 9a to 9g and the inspection device (main body) 70 is so high. It does not have to be a communication cable.

  More generally, in addition to the inspection method shown in FIG. 5, the circuit board 100 is preliminarily inspected for open / short circuit of each pattern, and if it is defective at that time, the efficiency of the inspection is improved. Therefore, the subsequent inspection is not performed, and the circuit board 100 can be treated as a waste disposal. In addition, in the case where a surface-mount type passive element component other than the ICs 41 and 42 is built in the circuit board 100, after the pattern open / short inspection, the connection inspection is performed on the passive element component. And about what passed this, the test | inspection by the process of the said FIG. 5 is performed. According to the inspection in this order, the inspection is performed from the easier side, and the efficiency of the inspection is improved as a whole.

  Also, in general, inspecting IC components, there is one that determines whether or not the inside has been destroyed by static electricity or the like. In order to cope with this, for the purpose of reference, the configuration of the inspection apparatus 770 shown in FIG. 6 may be used. The inspection principle is that each IC (excluding the ground terminals 1a and 2a) is fixed to the potential on the power supply side (by the power supply devices 771 and 773) in each of the ICs 41 and 42, and the current between the power supply and ground (that is, standby current). ) Is measured by ammeters 772 and 774 provided in the inspection apparatus 770. If this current falls below a predetermined very small current value (for example, 0.5 μA or 0.1 μA), it is determined that the ICs 21 and 22 are normal without internal damage. In FIG. 6, reference numeral 775 denotes a switch that switches according to an object whose standby current is measured.

  In FIG. 6, since the wiring pattern 3c connected to the power switch terminal 2e and the power terminal 2b is shared in the IC 42, the power switch terminal 2e has only the same potential as the power terminal 2b. However, in the case of the IC 42, in the sense of measuring the standby current, it is possible to perform a more accurate measurement by measuring the power switch terminal 2e with the same potential as the ground. In order to cope with such measurement, on the circuit board 100 side, the wiring pattern connected to the power switch terminal 2e and the wiring pattern connected to the power supply terminal 2b are electrically separated. These are electrically connected when the circuit board 100 is actually used.

  Next, FIG. 7 is a block diagram showing a mode for carrying out the inspection method according to one embodiment of the present invention. In the figure, the same reference numerals are given to the same elements as those appearing in the already described figures. In FIG. 7, in particular, components to be provided between the circuit board 100 to be inspected and the inspection apparatus (main body) 70 will be described.

  As shown in the figure, the circuit board 100 has press parts 70b, 70c configured in a plate shape from above and below, and inspection needles provided at predetermined positions in the press parts 70b, 70c are provided on the circuit board 100. So that it can abut against the inspection lands on both main surfaces. The press portions 70b and 70c are made of a material whose main body material can be shrunk by, for example, a compressive force in the illustrated vertical direction. If the press parts 70b and 70c as a part of such a probe part are used, probing becomes very easy rather than contacting each test needle separately. Between the press portions 70b and 70c (inspection needles) and the inspection device (main body) 70, a cable portion 70a as another part of the probe portion is provided.

  Next, FIG. 8 is a block diagram showing a mode for carrying out an inspection method which is another embodiment of the present invention. In the figure, the same reference numerals are given to the same elements as those appearing in the already described figures. FIG. 8 particularly shows a case in which a circuit board 100A to be inspected is configured to have multiple impositions to be inspected.

  The circuit board 100A is a board (multi-faced circuit board) in which a plurality of boards configured like the circuit board 100 are provided side by side on the same large board. Such circuit board 100A is then separated into individual circuit boards by dicing. Manufacturing efficiency is improved by arranging and manufacturing them on the same large plate.

  This inspection mode is intended to perform the inspection as described above on such a multi-sided circuit board 100A at a time. That is, the press portions 70bA and 70cA also have an area capable of probing the entire surface corresponding to the multi-sided circuit board 100A. In the cable part 70aA, the number of communication lines is increased by the amount of multiple impositions. In addition to the inspection apparatus (main body) 70 described above, the inspection apparatus (main body) 70A is provided with a target switching unit 701. The object switching unit 701 performs route selection (that is, multiplexing and demultiplexing) to / from individual portions to be inspected on the circuit board 100A. Note that the target switching unit 701 can be provided on the side of the press units 70bA and 70cA. In this case, the cable portion 70aA does not increase so much from the case where the number of communication lines is shown in FIG.

  1a, 1b, 1c, 1d, 1e, 2a, 2b, 2c, 2d, 2e, 2f... IC terminals, 3a, 3b, 3c, 3d, 3e, 3f, 3g ... wiring patterns, 9a, 9b, 9c, 9d, 9e, 9f, 9g ... inspection needles, 11, 12, 13, 14, 15 ... insulating layer, 21 ... wiring layer (wiring pattern), 22 ... wiring layer (wiring pattern), 22a ... land pattern, 23 ... wiring layer ( Wiring pattern), 24 ... wiring layer (wiring pattern), 25 ... wiring layer (wiring pattern), 26 ... wiring layer (wiring pattern), 31, 32, 34, 35 ... interlayer connection (conducting by conductive composition printing) , 33 ... through-hole conductor, 41, 42 ... IC, 41a, 42a ... IC terminal, 51,52 ... solder, 61,62 ... solder resist, 70 ... inspection device (main body), 70A ... inspection device ( Body; many 70a ... cable part (part of the probe part), 70b, 70c ... press part (part of the probe part), 70aA ... cable part (part of the probe part; compatible with multi-faced circuit board), 70bA, 70cA ... Pressing part (part of probe part; corresponding to multi-faced circuit board), 71 ... Signal generating part, 71a ... Clock generating part, 71b ... Slave address (or command) generating part, 72 ... ACK determining part, 73 ... Current value determination unit, 74 ... Inspection device power supply unit, 75 ... Write protect setting unit, 100 ... Circuit board, 100A ... Circuit board (multi-sided), 701 ... Target switching unit, 770 ... Inspection device, 771,773 ... Inspection Device power supply, 772, 774 ... ammeter, 775 ... switch.

Claims (2)

A first clock input terminal and a first serial data input / output terminal; a clock having a predetermined frequency is connected to the first clock input terminal; and first predetermined serial data synchronized with the clock having the predetermined frequency is A first IC that outputs a first recognition signal from the first serial data input / output terminal, a second clock input terminal, and a second serial as they are respectively input to the first serial data input / output terminal A second predetermined serial data different from the first predetermined serial data, wherein the second clock input terminal is synchronized with the clock having the predetermined frequency. A second IC that outputs a second recognition signal from the second serial data input / output terminal as it is input to the second serial data input / output terminal; Is mounted, the first IC is a current sink terminal further and the a predetermined frequency of the clock is the first clock input terminal, synchronized to the the predetermined frequency clock, said first, second An IC that sucks in a predetermined amount of current from the current sink terminal inward as third predetermined serial data different from the predetermined serial data is input to the first serial data input / output terminal, A first wiring pattern that electrically connects the first clock input terminal and the second clock input terminal, and the first serial data input / output terminal and the second serial data input / output terminal are electrically connected. object and the second wiring pattern, the third circuit board and a wiring pattern electrically conductive to the current sink terminal of the first IC to connect the manner There is provided an inspection method for,
Conducting to the first wiring pattern and abutting the first inspection needle against the circuit board and conducting to the second wiring pattern and abutting the second inspection needle to the circuit board,
Supplying a clock of the predetermined frequency to the first inspection needle and simultaneously supplying the first predetermined serial data to the second inspection needle;
Determining whether the first recognition signal is detected by the second inspection needle;
Supplying the clock of the predetermined frequency to the first inspection needle and simultaneously supplying the second predetermined serial data to the second inspection needle;
Determining whether the second recognition signal is detected by the second inspection needle ;
Conducting the third wiring pattern and butting a third inspection needle against the circuit board,
Supplying the clock of the predetermined frequency to the first inspection needle and simultaneously supplying the third predetermined serial data to the second inspection needle;
A method for inspecting a circuit board, comprising: determining whether or not the current of the predetermined magnitude has been detected via the third inspection needle . A first clock input terminal and a first serial data input / output terminal; a clock having a predetermined frequency is connected to the first clock input terminal; and first predetermined serial data synchronized with the clock having the predetermined frequency is A first IC that outputs a first recognition signal from the first serial data input / output terminal, a second clock input terminal, and a second serial as they are respectively input to the first serial data input / output terminal A second predetermined serial data different from the first predetermined serial data, wherein the second clock input terminal is synchronized with the clock having the predetermined frequency. A second IC that outputs a second recognition signal from the second serial data input / output terminal as it is input to the second serial data input / output terminal; Is mounted, the first IC is a current sink terminal further and the a predetermined frequency of the clock is the first clock input terminal, synchronized to the the predetermined frequency clock, said first, second An IC that sucks in a predetermined amount of current from the current sink terminal inward as third predetermined serial data different from the predetermined serial data is input to the first serial data input / output terminal, A first wiring pattern that electrically connects the first clock input terminal and the second clock input terminal, and the first serial data input / output terminal and the second serial data input / output terminal are electrically connected. object and the second wiring pattern, the third circuit board and a wiring pattern electrically conductive to the current sink terminal of the first IC to connect the manner There is provided an inspection apparatus for,
Conducting to the first wiring pattern and abutting a first inspection needle against the circuit board, conducting to the second wiring pattern and abutting a second inspection needle to the circuit board, and further to the third a probe portion which conducts the wiring pattern Ru abuts the third test needle to the circuit board,
A first signal generator for generating a signal to supply the first predetermined needle to the first inspection needle and simultaneously supply the first predetermined serial data to the second inspection needle;
A first determination unit that determines whether or not the first recognition signal can be detected by the second inspection needle;
A second signal generator for generating a signal to supply the second predetermined serial data to the second inspection needle at the same time as supplying the clock of the predetermined frequency to the first inspection needle;
A second determination unit that determines whether or not the second recognition signal can be detected by the second inspection needle ;
A third signal generator for generating a signal to supply the first predetermined frequency to the first inspection needle and simultaneously supply the third predetermined serial data to the second inspection needle;
A circuit board inspection apparatus comprising: a third determination unit configured to determine whether or not the current of the predetermined magnitude has been detected via the third inspection needle .

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