JP5359858B2 - Information code and information code generation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information code which can secure high correcting capability while ensuring a further large data area by reducing the data volume required for error correction. <P>SOLUTION: A two-dimensional code 1 includes a plurality of data code blocks 11 having a plurality of information display unit cells C aligned therein, the data code block expressing a data code word by a predetermined number of information display unit cells C; and a plurality of error correction code blocks 12 which expresses an error correction code word used for error correction of each data code word. An error detection parity to be used for the error detection of each data code word is assigned in association with each data code word, and the bit number of the error detection parity is smaller than the bit number of the data code word. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to an information code and an information code generation method.

  Conventionally used two-dimensional codes such as QR Code (registered trademark) have a structure in which a plurality of cells are arranged in a matrix, and a plurality of data code blocks representing data code words in a code area. And a plurality of error correction code blocks representing error correction code words used for error correction of each data code block are generally provided.

In this type of two-dimensional code, for example, a data code word represents a unit element that constitutes data with several bits (for example, 8 bits) of information as one unit, and an error correction code word includes the data For example, a code representing error correction of a code word represented by information of several bits (for example, 8 bits) is used. As the error correction code word, for example, a code (RS code) for performing error correction by the Reed-Solomon method is widely used.

JP-A-7-254037

  By the way, when reading a two-dimensional code as described above, even if one of the data code words is read incorrectly, the error occurrence position is not specified at the initial stage of reading. It is necessary to identify the data code word in which the error occurs and to determine the magnitude of the error and correct the error. However, when error correction (so-called “detection correction”) is performed in a state where the error occurrence position is not specified in this way, it is compared with error correction (so-called “erasure correction”) performed with the error position specified. Therefore, the size of data (error correction code) necessary for error correction tends to increase.

  For example, in the conventional QR code system, error correction of one data code word is performed using two error correction code words (RS code words) having the same number of bits as the data code word. However, when error correction is performed by such a method, there is a problem that the total number of correctable data codewords is half of the total number of error correction codewords (RS codewords), and data that can be recorded in the code area There is also a problem that the data size of (decryption target data) is limited to half the data size of the error correction codeword (RS codeword). On the other hand, a method for ensuring a large data amount of the data code word by suppressing the data amount of the error correction code word (RS code word) is also conceivable, but in this case, the correction capability is unavoidable.

  The present invention has been made in order to solve the above-described problems. An information code that ensures a high correction capability while ensuring a larger data area while suppressing the amount of data required for error correction is provided. The purpose is to provide.

The invention of claim 1 is an information code in which a plurality of two types of information display unit cells having different colors, densities or luminances are arranged in a matrix,
A plurality of data code blocks representing a data code word by a predetermined number of the information display unit cells;
A plurality of error correction code blocks representing error correction code words used for error correction of each data code word;
With
Corresponding to each data code word, an error detection parity used for error detection of each data code word is attached, and the number of bits of the error detection parity is smaller than the number of bits of the data code word It is in,
The data code block and the error detection parity are both represented by two types of the information display unit cells, and the data code block and the error detection parity are arranged in separate areas,
One type of the information display unit cell is associated with a data value of 0, and another type of the information display unit cell is associated with a data value of 1,
The parity for error detection is generated based on a value obtained by adding 1 to the total value of the bit values of the associated data codewords, and the plurality of information indications of the data codewords When the values indicated by the unit cells are all 0, 1 is included in the error detection parity assigned to the data codeword .

The invention of claim 2 is characterized in that the data code word is represented by 8 bits and the error detection parity is represented by 2 bits.

The invention of claim 3 is characterized in that the number of error correction codewords is less than twice the number of data codewords.

The invention according to claim 4 is an information code generation method for generating the information code according to any one of claims 1 to 3 by using an information processing apparatus, and acquires the decoding target data to be encoded. A first generation step for generating each data code word based on the data to be decoded acquired in the acquisition step, and each error detection corresponding to each data code word generated by the first generation step A second generation step for generating a parity; and a third generation step for generating the error correction code word corresponding to each data code word generated by the first generation step.

  In the first aspect of the present invention, a plurality of data code blocks expressing a data code word by a predetermined number of information display unit cells and a plurality of error correction code blocks expressing an error correction code word used for error correction of each data code word Are associated with each data code word, and an error detection parity used for error detection of each data code word is attached, and the number of bits of the error detection parity is the number of bits of the data code word. It is less than the number. In this way, it is possible to detect whether or not an error has occurred in each data code word with a smaller number of bits than the number of bits of the data code word. Based on the detection of such an error position, the erasure correction can be performed with the error correction code block being suppressed to a smaller data amount.

In addition, error detection parity is generated based on a value obtained by adding 1 to the total value of the bit values of the associated data codewords. In this way, for example, even when the data code blocks are all stained with a dark color (for example, black) or when all the data code blocks are stained with a light color (for example, white), it is easy to prevent detection errors from being detected.

According to the second aspect of the present invention, the data code word is represented by 8 bits and the error detection parity is represented by 2 bits. In this way, each data element is suitably expressed by an 8-bit data code word, and a data code word error can be detected well with a number of bits that is significantly less than the number of bits of the data code word. Become.

In the invention of claim 3 , the number of error correction codewords is less than twice the number of data codewords. In this way, the amount of data required for error correction can be suppressed as compared with a method in which error correction of one data code word is performed using two error correction code words.

According to the invention of claim 4 can satisfactorily generate an information code to achieve the same effect as the information code as claimed in any one of claims 4.

FIG. 1 is an explanatory diagram schematically illustrating an information code according to the first embodiment. FIG. 2 is an explanatory diagram illustrating a specific cell configuration of the data code block and the error detection parity assigned to the data code block. FIG. 3 is an explanatory diagram illustrating a data code word and error detection parity assigned to the data code word. FIG. 4 is a block diagram schematically illustrating an optical information reader that reads an information code according to the first embodiment. FIG. 5 is an explanatory diagram illustrating a plurality of combinations of data code words and error detection parity.

[First embodiment]
Hereinafter, a first embodiment of an information code according to the present invention will be described with reference to the drawings.
(Configuration of two-dimensional code)
First, the configuration of the information code according to the present embodiment will be described with reference to FIGS.
FIG. 1 is an explanatory diagram schematically illustrating an information code according to the first embodiment. FIG. 2 is an explanatory diagram illustrating a specific cell configuration of the data code block and the error detection parity assigned to the data code block. FIG. 3 is an explanatory diagram illustrating a data code word and error detection parity assigned to the data code word.

  As shown in FIG. 1, the information code 1 according to the present embodiment includes a plurality of information display unit cells (hereinafter also simply referred to as “cells”) C arranged in a matrix, and includes a plurality of code blocks. 10, a first specific pattern 2, a second specific pattern 3, 4, and a third specific pattern 5. This information code 1 is configured as a cell aggregate in which cells C whose outer shape is formed in a square shape are aggregated and arranged in a matrix. In the example of FIG. 1, the number of cells is the same in the vertical and horizontal directions (11 cells × 11 cells). Further, the code area (area where the cell C is arranged) constituting the information code 1 is a rectangular area having a rectangular outer shape, and in the representative example of FIG. 1, the outer shape is a square area having a square shape. . In FIG. 1, only some of the cells are denoted by reference symbol C, and the other cells are omitted.

  The information code 1 is formed by arranging a plurality of types of cells having different colors, densities, or luminances. In the representative example shown in FIG. 1, two types of cells having different colors, densities, or luminances (specifically, A black cell and a white cell) are used to form the information code 1. In FIG. 1 and the like, the black cell is indicated by a symbol Cb, and the white cell is indicated by a symbol Cw.

  The code block 10 is a set of a plurality of cells C. In the information code 1 of FIG. 1, the code block 10 is divided into a data code block 11 and an error correction code block 12. In FIG. 1, the areas of the data code block 11, the error correction code block 12, and the error correction parity block 15 are conceptually indicated by hatching, a broken line frame, and hatching, respectively. Specifically, as shown in FIG. 2, the black cells Cb or the white cells Cw are arranged.

  The data code block 11 has a configuration as shown in FIG. 2, for example, and is configured as a block in which encoded data (data code word) obtained by encoding each data element of data to be decoded is expressed by a plurality of cells. Has been. As each cell constituting the data code block 11, one type of cell is selected from a plurality of predetermined types of cells (two types of black cell Cb and white cell Cw in the example of FIG. 2). In the example of FIG. 2, a plurality of (eight in FIG. 2) cells are assembled in a matrix. The cell arrangement and the block shape are not limited to the configuration shown in FIG. 2, and various arrangements and shapes can be used. Further, some data code blocks 11 may be formed across two or more areas.

  Each data code block 11 as a whole is configured by an array of cells corresponding to encoded data (data code words) to be decoded. In the present embodiment, the color of the cell is associated with a numerical value. For example, a white cell is associated with the data value “0” and a black cell is associated with the data value “1”. In the example of FIG. 2, an 8-bit value “00000011” is expressed by eight cells by the data code block 11.

  In this embodiment, an error detection parity used for error detection of each data code word is attached in association with each data code word constituting each data code block. The number of bits of the error detection parity is smaller than the number of bits of the data code word. In the typical examples shown in FIGS. 1 and 2, the data code word is represented by 8 bits. Is represented by 2 bits (that is, the data code block 11 representing the data code word is composed of 8 cells, and the block 15 representing the error detection parity is composed of 2 cells. ). In FIG. 1, the combination of the data code block 11 and the corresponding error detection parity is conceptually shown by a thick line frame.

  The error correction code block 12 is a code block used for error correction of each data code word represented by each data code block 11. For example, one error correction code block 12 is provided corresponding to each data code block 11. The error correction code block 12 is an encoded error correction code word generated by a predetermined method based on the data code word of the corresponding data code block 11, and data obtained by encoding the error correction code word. Is expressed by a plurality of cells C.

  In the present embodiment, a data code block 11 in which an error has occurred is specified by an error correction method to be described later, and error correction is performed by one error correction code block 12 corresponding to the data code block 11 in which the error has occurred. It is assumed that (erasure correction) is performed, and the contents of the error correction code block 12 (that is, error correction codewords) use codes of various known methods as long as such a configuration capable of erasure correction is possible. Can do. In the representative example of this embodiment, a known Reed-Solomon error correction method is used as an example. Specifically, a Reed-Solomon code (RS code) is used for each data code word with the same number of bits as each data code word. ) And each RS code corresponding to each data code word is represented by an error correction code block 12.

(Contents of parity for error detection)
Next, the error detection parity that characterizes the present embodiment will be described.
As described above, in the information code 1, an error detection parity used for error detection of each data code block 11 is attached to each data code block 11. This error detection parity is expressed by adding a predetermined value (specifically, for example, the number of bits of error detection parity to the sum of the bit values of the associated data codewords). It is the value of the remainder divided by the number.

  For example, as shown in FIGS. 1 and 2, when the data code word is represented by 8 bits and the error detection parity is represented by 2 bits, the number that can be represented by the detection parity is 4, “4” can be suitably used as the “predetermined number”. In this case, for example, if the value of the data code word is “00000001”, the sum of the bit values of the data code word is “1”, and the value obtained by adding 1 to this is 2 . Accordingly, since a value obtained by dividing this by “4” is 2, a value “10” in which “2” is expressed in binary is added as an error detection parity. Similarly, if the value of the data code word is “00000011”, the total value obtained by adding the bit values of the data code word is “2”, and the value obtained by adding 1 to this is 3. Accordingly, since a value obtained by dividing this by “4” is 3, a value “11” in which “3” is expressed in binary is added as an error detection parity. The same applies to the middle example of FIG. 3. In this example, the value of the data code word is “0011111”, and the total value obtained by summing up the respective bit values of the data code word is “5”. The value obtained by adding is 6. Accordingly, since a value obtained by dividing this by “4” is 2, a value “10” in which “2” is expressed in binary is added as an error detection parity.

  Further, in this embodiment, 1 is added to the total value obtained by summing up the respective bit values of the data codeword. However, by using such a method, error detection can be performed more accurately. In other words, when an error occurs due to contamination of the information code 1, all the cells C of any data code block 11 are often stained in dark colors or all the cells C are stained in light colors. In this case, since the data code word is “00000000”, if the total value itself of the bit values of the data code word is used as error detection parity, “00” is obtained, and the error can be detected. It will disappear. On the other hand, in this embodiment, since the value obtained by adding 1 to the total value of the bit values of the data code word is used as the error detection parity, all the cells C are stained in light color as described above. However, it is difficult to achieve matching.

  In the above embodiment, a configuration in which a 2-bit error detection parity is assigned to an 8-bit data code word is illustrated. However, as shown in the upper part of FIG. 3, a 1-bit data code word is assigned to an 8-bit data code word. Error detection parity may be assigned. In this case, since the number that can be expressed by the number of bits of the error detection parity is “2”, “2” is used as the “predetermined number”, and the error detection parity is the associated data codeword. A value obtained by adding 1 to the total value obtained by summing up the respective bit values can be obtained as a remainder value obtained by dividing by “2”. For example, in the case of an 8-bit data code word “00011111” as shown in the upper part of FIG. 3, the total value of each bit is “5”, and the value obtained by adding 1 to this is “6”. A value obtained by dividing “6” by “2” which is the “predetermined number” (that is, “0”) can be used as an error detection parity. In this case, if the value obtained by adding 1 to the total value of each bit value of the data code word is an even number, the error detection parity is “0”, and if it is an odd number, the error detection parity is “1”.

  Alternatively, as shown in the lower part of FIG. 3, a 3-bit error detection parity may be assigned to an 8-bit data codeword. In this case, since the number that can be expressed by the number of bits of the error detection parity is “8”, “8” is used as the “predetermined number”, and the error detection parity is the associated data codeword. A value obtained by adding 1 to the total value obtained by summing up the respective bit values can be obtained as a remainder value obtained by dividing by “8”. For example, in the case of an 8-bit data code word “00011111” as shown in the lower part of FIG. 3, the total value of each bit is “5”, and the value obtained by adding 1 to this is “6”. A value “110” in which a value obtained by dividing “6” by “8” which is the “predetermined number” (that is, “6”) is expressed as a 3-bit binary number can be used as an error detection parity.

(How to create an information code)
The information code 1 is created by the following method using, for example, an information processing device (such as a personal computer) equipped with a CPU, memory, input device (mouse, keyboard), communication unit (such as a LAN interface), and the like. be able to.

  First, in the information processing apparatus, an acquisition step for acquiring data to be decoded to be encoded is performed. In this acquisition step, for example, data to be encoded is acquired by a method such as input from a keyboard, external input via a communication unit, or reading data already stored in the information processing apparatus.

  And the 1st production | generation step which produces | generates each data code word based on the decoding object data acquired at the acquisition step is performed. In the first generation step, each data element (for example, each character, each number, etc.) constituting the data to be decoded is encoded according to a predetermined method. In the present embodiment, each data code word is generated as binary data.

  Thereafter, a second generation step of generating each error detection parity corresponding to each data codeword generated in the first generation step is performed. In this second generation step, each error detection parity corresponding to each data codeword is generated by the above-described method. The error detection parity is also generated as binary data. Further, a third generation step of generating an error correction code word corresponding to each data code word by a prescribed method (for example, Reed-Solomon method) is performed. In this embodiment, the error correction code word is also generated as binary data. Then, the binary data for each data code word, each error detection parity, and each error correction code word generated in this way is expressed by black cells and white cells, and these are expressed in a prescribed manner as shown in FIG. According to the format, the drawing data of the information code 1 is acquired by arranging in a prescribed order. Such drawing data may be printed by a printing device or the like, or may be displayed on a display device such as a portable terminal.

(Example of reading information code)
Next, an example of reading the information code 1 according to the present embodiment will be outlined.
The information code 1 according to the present embodiment can be read by an optical information reader 20 as shown in FIG. 4, for example. 4 mainly includes an optical system such as an illumination light source 21, a light receiving sensor 23, a filter 25, and an imaging lens 27, a memory 35, a control circuit 40, an operation switch 42, and a liquid crystal display device. And a power supply system such as a power switch 41 and a battery 49.

  The optical system includes an illumination light source 21, a light receiving sensor 23, a filter 25, an imaging lens 27, and the like. The illumination light source 21 functions as an illumination light source capable of emitting the illumination light Lf, and includes, for example, an LED and a diffusing lens, a condensing lens, and the like provided on the emission side of the LED. In the present embodiment, illumination light sources 21 are provided on both sides of the light receiving sensor 23 so that the illumination light Lf can be irradiated toward the reading object R through a reading port (not shown in FIG. 4) of the housing. It is configured. The reading object R corresponds to a display medium such as a packaging container, packaging paper, or label, and the information code 1 according to the present embodiment is printed on the reading object R by printing or direct marking. Is formed.

  The light receiving sensor 23 is configured to receive the reflected light Lr irradiated and reflected on the reading object R and the information code 1. For example, the light receiving sensor 23 includes two light receiving elements which are solid-state imaging elements such as C-MOS and CCD. An area sensor arranged in a dimension corresponds to this. The light receiving sensor 23 is mounted on a printed wiring board (not shown) so that incident light incident through the imaging lens 27 can be received by the light receiving surface 23a. The filter 25 is an optical low-pass filter that allows passage of light that is less than or equal to the wavelength of the reflected light Lr and can block passage of light that exceeds that of the reflected light, and is unnecessary for exceeding the wavelength of the reflected light Lr. Light is prevented from entering the light receiving sensor 23. The imaging lens 27 functions as an imaging optical system capable of condensing incident light incident from the outside via a reading port and forming an image on the light receiving surface 23a of the light receiving sensor 23. For example, A lens barrel and a plurality of condensing lenses housed in the lens barrel are configured.

  Next, a configuration outline of the microcomputer system will be described. The microcomputer system includes an amplification circuit 31, an A / D conversion circuit 33, a memory 35, an address generation circuit 36, a synchronization signal generation circuit 38, a control circuit 40, an operation switch 42, an LED 43, a buzzer 44, a liquid crystal display device 46, and a communication interface 48. Etc. As the name suggests, this microcomputer system is composed mainly of a control circuit 40 and a memory 35 that can function as a microcomputer (information processing apparatus). The microcomputer system captures the image signal of the information code 1 captured by the optical system described above. It can perform signal processing in terms of hardware and software. The control circuit 40 also performs control related to the entire system of the optical information reading device 20.

  An image signal (analog signal) output from the light receiving sensor 23 of the optical system is input to the amplification circuit 31 and amplified by a predetermined gain, and then input to the A / D conversion circuit 33. Converted into a digital signal. When the digitized image signal, that is, image data (image information) is input to the memory 35, it is stored in the image data storage area. The synchronization signal generation circuit 38 is configured to generate a synchronization signal for the light receiving sensor 23 and the address generation circuit 36. The address generation circuit 36 is based on the synchronization signal supplied from the synchronization signal generation circuit 38. Thus, the storage address of the image data stored in the memory 35 can be generated.

  The memory 35 is a semiconductor memory device, and corresponds to, for example, a RAM (DRAM, SRAM, etc.) or a ROM (EPROM, EEPROM, etc.). In addition to the above-described image data storage area, the RAM of the memory 35 is configured to be able to secure a work area and a reading condition table that are used by the control circuit 40 in each processing such as arithmetic operation and logical operation. . The ROM stores in advance a predetermined program that can execute reading processing, analysis processing, and the like, which will be described later, and a system program that can control each piece of hardware such as the illumination light source 21 and the light receiving sensor 23.

  The control circuit 40 is a microcomputer that can control the entire optical information reading device 20 and includes a CPU, a system bus, an input / output interface, and the like. . The control circuit 40 is configured to be connectable to various input / output devices (peripheral devices) via a built-in input / output interface. In this embodiment, the control circuit 40 includes a power switch 41, an operation switch 42, an LED 43, a buzzer. 44, a liquid crystal display device 46, a communication interface 48, and the like are connected to the control circuit 40. The communication interface 48 is connected to a host computer HST corresponding to the host system of the optical information reader 20. The power supply system includes a power switch 41, a battery 49, and the like. When the power switch 41 is turned on and off by the control circuit 40, the conduction of the drive voltage supplied from the battery 49 to each device and each circuit described above is performed. Shut-off is controlled.

In the optical information reader 20 configured as described above, the reading process is performed as follows.
The reading process is started, for example, when an operator performs a predetermined operation (for example, an operation of turning on the operation switch 42). First, a process of imaging the information code 1 is performed. In this imaging process, image data including the image of the information code 1 is acquired and stored in the memory 35.

  Thereafter, in the image data, the position and orientation of the code area are specified, the position of each cell included in the code area is specified, and decoding processing is performed based on the code area (rectangular area). In the present embodiment, for example, the format of the information code 1 is registered in the optical information reader 20, and each data code word recorded in each data code block 1 is decoded according to the format.

  When each data code word is decoded, the corresponding error detection parity is referred to, and consistency with the data code word is taken (that is, the above-described generation based on the value of the recognized data code word). When the error detection parity is generated by the method, it is determined whether or not it matches the recognized error detection parity value). If it is determined in this determination process that the data is consistent, the data code word of the data code block 11 is output as a normal code word. On the other hand, when it is determined that the alignment is not achieved, the data code word of the data code block 11 is treated as an error code word, and the code word (RS code) of the error correction code block 12 corresponding to the data code block 11 is concerned. Erasure correction using a word).

(Main effects of this embodiment)
The information code 1 according to the present embodiment includes a plurality of data code blocks 11 expressing a data code word by a predetermined number of information display unit cells C and a plurality of error correcting code words used for error correction of each data code word. The error correction code block 12 is provided, and an error detection parity used for error detection of each data code word is attached in association with each data code word. The number of bits of error detection parity is smaller than the number of bits of the data code word. In this way, it is possible to detect whether or not there is an error in reading each data code word with a smaller number of bits than the number of bits of the data code word. Based on the detection of such an error position, the erasure correction can be performed with the error correction code block being suppressed to a smaller data amount.

  The above effect can also be specifically described with an explanatory diagram as shown in FIG. In the example of FIG. 5, the error pattern when the correct value (correct value) of the data code word is “00000001” and the correct value (correct value) of the error detection parity (hereinafter also referred to as parity) is “10”. Are listed as examples. Pattern 1 is a pattern in which both the data code word and the error detection parity indicate correct values (correct values). For example, pattern 2 is an example in which the correct value (correct value) of the data code word is “00000001” and the parity is incorrect. In this case, it is determined that the data code word is correct but the data code word is correct. become. In this case, erasure correction is performed assuming that an error has occurred in the data code word.

  On the other hand, pattern 3 is an example in which the data code word is erroneously recognized as “00000011” and the parity is correctly recognized as “10”. In this case, the value obtained by adding 1 to the bit sum due to the erroneously recognized data code word is 2 + 1 = 3. On the other hand, since the parity indicates 2, the mismatch occurs and the error can be detected. Therefore, erasure correction can be performed using one error correction code block 12 corresponding to the data code word. Since the conventional general method uses two error correction code blocks in such a case, it can be read that this pattern 3 can be accurately restored with a smaller amount of data compared to the conventional method.

  Pattern 4 is an example in which the data code word is erroneously recognized as “00011111” and the parity is erroneously recognized as “11”. In this example, the parity is erroneously recognized, but the consistency between the data code word and the parity cannot be obtained and an error is detected. Therefore, erasure correction can be performed using one error correction code block 12 corresponding to the data code word. In the conventional general method, error correction is performed using two error correction code blocks in such a case. Therefore, even this pattern 4 can be accurately restored with a smaller amount of data compared to the conventional method. I can read.

  In the pattern 2, the data code word is correct, but it is determined as an error by the parity, and one error correction code word which does not need to be used is used. However, since this pattern 2 is a case in which only the parity is wrong without the data code word being erroneous, the probability that the pattern 2 is generated in consideration of the length of the data code word and the length of the parity (8: 2 in this example). Is extremely low.

  Further, in the information code 1 according to the present embodiment, the error detection parity is generated based on a value obtained by adding 1 to the total value obtained by adding the bit values of the associated data codewords. In this way, for example, even if the data code block 11 is all stained with a dark color (for example, black) or all the data code block 11 is stained with a light color (for example, white), it becomes easy to prevent detection errors from being detected.

  In the information code 1 according to the present embodiment, the data code word is represented by 8 bits, and the error detection parity is represented by 2 bits. In this way, each data element is suitably expressed by an 8-bit data code word, and a data code word error can be detected well with a number of bits that is significantly less than the number of bits of the data code word. Become.

  In the information code 1 according to the present embodiment, the number of error correction code words is less than twice the number of data code words. In this way, the amount of data required for error correction can be suppressed as compared with a method in which error correction of one data code word is performed using two error correction code words.

[Other Embodiments]
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

  In the above embodiment, the information code arranged in 11 rows and 11 columns is illustrated as an example of the information code, but the cell arrangement is not limited to this, and the number of rows may be increased or decreased, and the number of columns may be increased or decreased. Good.

  In the above embodiment, the data code word and the error correction code word are both configured by 8-bit binary data, and the error correction parity is configured by 2-bit binary data. All the number of bits may be changed. For example, the error correction parity may be composed of binary data of 1 bit or 3 bits or more as described above. Alternatively, the data code word and the error correction code word may be composed of binary data larger than 8 bits (for example, 16-bit binary data).

  In the above-described embodiment, the configuration in which one error correction code block 12 is assigned to each data code block 11 is exemplified. However, two errors are detected for any one of the data code blocks 11 (for example, a data code block regarded as important). A correction code block may be assigned and one error correction code block may be assigned to the other data code blocks 11 as in the above embodiment. In this case, for any one of the data code blocks 11, when an error occurs in the data code block 11, an error detection is attempted using the error detection parity, and erasure correction is performed when an error is detected. be able to. On the other hand, when an error cannot be detected, “detection and correction” can be performed using two error correction code blocks. Therefore, the error correction level of a specific data code block can be increased.

DESCRIPTION OF SYMBOLS 1 ... Information code 11 ... Data code block 12 ... Error correction code block C ... Information display unit cell

Claims (4)

An information code saturation, hue, or two types of information display unit cells having different luminance, which are arrayed in a matrix,
A plurality of data code blocks representing a data code word by a predetermined number of the information display unit cells;
A plurality of error correction code blocks representing error correction code words used for error correction of each data code word;
With
Corresponding to each data code word, an error detection parity used for error detection of each data code word is attached, and the number of bits of the error detection parity is smaller than the number of bits of the data code word It is in,
The data code block and the error detection parity are both represented by two types of the information display unit cells, and the data code block and the error detection parity are arranged in separate areas,
A value of 0 is associated with one type of the information display unit cell, and a value of 1 is associated with the other type of the information display unit cell;
The parity for error detection is generated based on a value obtained by adding 1 to the total value of the bit values of the associated data codewords, and the plurality of information indications of the data codewords An information code characterized in that when the values indicated by the unit cells are all 0, 1 is included in the error detection parity assigned to the data code word . 2. The information code according to claim 1 , wherein the data code word is represented by 8 bits, and the error detection parity is represented by 2 bits. 3. The information code according to claim 1, wherein the number of the error correction code words is less than twice the number of the data code words. An information code generation method for generating the information code according to any one of claims 1 to 3 using an information processing apparatus,
An acquisition step of acquiring data to be decoded to be encoded;
A first generation step of generating each data codeword based on the data to be decoded acquired in the acquisition step;
A second generation step of generating each error detection parity corresponding to each of the data codewords generated by the first generation step;
A third generation step of generating the error correction codeword corresponding to the data codeword generated by the first generation step;
An information code generation method characterized by comprising:

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