JP5353475B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, research has been conducted on a p-channel transistor in which a channel is distorted in order to improve charge mobility. For example, research on a p-channel transistor in which a SiGe film is formed on a source and a drain has been conducted. Note that if a SiGe layer is formed on the source and drain of an n-channel transistor, the charge mobility is lowered. Therefore, when the p-channel transistor and the n-channel transistor are included in one semiconductor device, the SiGe layer is formed only in the p-channel transistor.

  Here, an outline of a conventional method for manufacturing a semiconductor device will be described. 1A to 1C are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device in order of steps.

  First, as shown in FIG. 1A, an element isolation insulating film 102 is formed on the surface of a semiconductor substrate 101. Next, the gate insulating film 103 and the gate electrode 104 are formed on the semiconductor substrate 101 in the element active region partitioned by the element isolation insulating film 102. Impurity introduction regions 105p are formed on the surface of the semiconductor substrate 101 on both sides of the gate electrode 104 in the p-channel transistor formation region, and the semiconductor substrate is formed on both sides of the gate electrode 104 in the n-channel transistor formation region. An impurity introduction region 105 n is formed on the surface of 101.

  Thereafter, as shown in FIG. 1A (b), a sidewall insulating film 106 is formed on the entire surface.

  Subsequently, as shown in FIG. 1A (c), the sidewall 106a is formed on the side of each gate electrode 104 by etching back the insulating film. Next, a resist pattern 107 is formed that covers a region where an n-channel transistor is to be formed (n-channel transistor formation region) and exposes a region where a p-channel transistor is to be formed (p-channel transistor formation region).

  Thereafter, ion implantation of p-type impurities is performed using the resist pattern 107 as a mask, thereby forming an impurity introduction region 108p in the p-channel transistor formation planned region as shown in FIG. 1B (d). Then, the resist pattern 107 is removed.

  Subsequently, as shown in FIG. 1B (e), a hard mask insulating film 120 is formed on the entire surface.

  Next, as shown in FIG. 1B (f), a resist pattern 121 is formed to cover the n-channel transistor formation planned region and expose the p-channel transistor formation planned region. Then, using the resist pattern 121 as a mask, the insulating film 120 in the p-channel transistor formation scheduled region is removed.

  Thereafter, as shown in FIG. 1C (g), a trench 109 that aligns with the sidewall 106a is formed in the p-channel transistor formation region. Such a groove 109 can be formed by dry etching and wet etching.

  Subsequently, as shown in FIG. 1C (h), the SiGe layer 110 is formed in the groove 109, and the Si layer 111 is formed thereon. The SiGe layer 110 is selectively grown only on the exposed Si. Therefore, the SiGe layer 110 and the Si layer 111 are also formed on the gate electrode 104.

  Thereafter, the insulating film 120 is removed, and a resist pattern is formed to cover the p-channel transistor formation region and expose the n-channel transistor formation region. Then, n-type impurity ions are implanted into the n-channel transistor formation scheduled region. Thereafter, an interlayer insulating film and a wiring are formed to complete the semiconductor device.

  According to such a method, an appropriate strain can be generated in the channel of the p-channel transistor, and high charge mobility can be obtained.

  However, with the miniaturization of semiconductor devices, it has become difficult for conventional methods to generate appropriate distortion.

JP 2007-214362 A

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of generating appropriate strain even if miniaturization proceeds.

In one embodiment of a method for manufacturing a semiconductor device, a first gate electrode is formed in a first region of a semiconductor substrate, and a second gate electrode is formed in a second region. An insulating film is formed to cover the first region and the second region. Forming a mask layer covering the insulating film on the second region, exposing the insulating film on the first region, and etching the insulating film using the mask layer as a mask; A first sidewall is formed on the side of the electrode. In the first region, a p-type impurity introduction region is formed by introducing a p-type impurity into the surface of the semiconductor substrate using the first sidewall as a mask. Grooves are formed in the surface of the p-type impurity introduction region using the first sidewall as a mask. A SiGe layer is grown in the trench. After the mask layer is removed, the insulating film is etched to form a second sidewall on the side of the second gate electrode. In the second region, an n-type impurity introduction region is formed by introducing an n-type impurity into the surface of the semiconductor substrate using the second sidewall as a mask. When the SiGe layer is grown in the groove, a SiGe layer is also grown on the first gate electrode, and when the second sidewall is formed, the SiGe layer is grown on the first gate electrode. The SiGe layer is removed.

  According to the above method for manufacturing a semiconductor device, the insulating film that covers the second region when the trench is formed is used for forming the first sidewall in the first region. It is possible to suppress the formation of the groove remaining in the region.

It is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. FIG. 1B is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes following FIG. 1A. FIG. 2B is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes following FIG. 1B. It is sectional drawing which shows the problem of the conventional method which this inventor discovered. FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 3B is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes following FIG. FIG. 3B is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes following FIG. 3B. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment to process order. FIG. 4B is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes following FIG. 4A. FIG. 4B is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes, following FIG. 4B. FIG. 4D is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes following FIG. 4C. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment in order of a process. FIG. 5B is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes following FIG. 5A. It is a figure which shows the preferable conditions of the thickness of an insulating film.

  The inventor of the present application has conducted intensive studies on the reason why it is difficult to manufacture a semiconductor device as designed by the conventional method. As a result, the hard mask insulating film 120 is removed from the p-channel transistor formation region. Found that is insufficient. That is, since the interval between the gate electrodes 104 is reduced with the miniaturization, the insulating film 120 is likely to remain as a residue between the adjacent gate electrodes 104 as illustrated in FIG. is there. If the insulating film 120 is not sufficiently removed, the groove 109 cannot be formed there, and the SiGe layer 110 cannot be formed. Therefore, sufficient distortion does not occur in the channel.

  If the time required for etching the insulating film 120 is lengthened, it is easy to avoid the remaining of the insulating film 120, but the side wall 106a, the element isolation insulating film 102, etc. recede by that amount, and the leakage current increases accordingly. Etc. are caused.

  Further, even if the insulating film 120 is formed thin, it is easy to avoid the remaining of the insulating film 120, but the protection of the n-channel transistor formation scheduled region is lessened accordingly. As a result, as shown in FIG. 2B, the SiGe layer 110 and the Si layer 111 are formed on the gate electrode 104 and the semiconductor substrate 101 in the n-channel transistor formation scheduled region. Then, it becomes difficult to form an appropriate silicide layer thereafter, the resistance increases, or the gate electrode 104 is depleted.

  For this reason, in the conventional method, even if the thickness of the insulating film 120 is adjusted, it is difficult to manufacture a semiconductor device as designed.

  Accordingly, the inventors of the present application have made extensive studies to avoid the remaining of the insulating film in the p-channel transistor formation scheduled region, and as a result, have come up with various embodiments as shown below.

  Hereinafter, embodiments will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. 3A to 3C are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment in the order of steps.

  In the first embodiment, first, as shown in FIG. 3A (a), an element isolation insulating film 2 is formed on the surface of a semiconductor substrate 1 such as a single crystal silicon substrate. Next, the gate insulating film 3 and the gate electrode 4 are formed on the semiconductor substrate 1 in the element active region partitioned by the element isolation insulating film 2. Further, on both sides of the gate electrode 4 in a region where a p-channel transistor is to be formed (p-channel transistor formation planned region 51p), an impurity introduction region 5p is formed on the surface of the semiconductor substrate 1 to form an n-channel transistor. Impurity introduction regions 5n are formed on the surface of the semiconductor substrate 1 on both sides of the gate electrode 4 in a predetermined region (n-channel transistor formation planned region 51n).

  Thereafter, as shown in FIG. 3A (b), a sidewall insulating film 6 is formed on the entire surface.

  Subsequently, as shown in FIG. 3A (c), a resist pattern 7 is formed to cover the n-channel transistor formation planned region 51n and expose the p-channel transistor formation planned region 51p. Then, the insulating film 6 is etched back using the resist pattern 7 as a mask, thereby forming the sidewalls 6a on the sides of the gate electrodes 4 in the p-channel transistor formation planned region 51p.

  Next, as shown in FIG. 3B (d), the resist pattern 7 is removed. Thereafter, only a region where a p-channel transistor to be embedded in the SiGe layer later is to be formed is opened, and a resist pattern 17 covering the other region is formed. Then, by performing ion implantation of p-type impurities using the resist pattern 17 as a mask, an impurity introduction region 8p is formed in the p-channel transistor formation planned region 51p. Then, the resist pattern 17 is removed.

  Thereafter, as shown in FIG. 3B (e), a groove 9 aligned with the sidewall 6a is formed in the p-channel transistor formation planned region 51p. Such a groove 9 can be formed by, for example, dry etching and wet etching. Since the n channel transistor formation planned region 51n is covered with the insulating film 6, the trench 9 is not formed in the n channel transistor formation planned region 51n.

  Subsequently, as shown in FIG. 3B (f), the SiGe layer 10 is formed in the groove 9, and the Si layer 11 is formed thereon. The SiGe layer 10 is selectively grown only on the exposed Si. Therefore, the SiGe layer 10 and the Si layer 11 are also formed on the gate electrode 4. Since the n-channel transistor formation planned region 51n is covered with the insulating film 6, the SiGe layer 10 and the Si layer 11 are not formed in the n-channel transistor formation planned region 51n.

  Next, as shown in FIG. 3C (g), the insulating film 6 is etched back to form the sidewalls 6b on the sides of the gate electrodes 4 in the n-channel transistor formation region 51n. At this time, since the sidewall 6a in the p-channel transistor formation scheduled region is exposed, the sidewall 6a becomes thin. Further, the SiGe layer 10 and the Si layer 11 on the gate electrode 4 in the p-channel transistor formation scheduled region and the Si layer 11 on the SiGe layer 10 in the trench 9 are removed.

  Thereafter, ion implantation of an n-type impurity is performed using a resist pattern that covers the p-channel transistor formation region and exposes the n-channel transistor formation region, thereby forming an n-channel transistor as shown in FIG. An impurity introduction region 8n is formed in the planned region 51n. Then, annealing for activating impurities in the impurity introduction regions 5n and 8n is performed. As this annealing, for example, millisecond level annealing or RTP (rapid thermal processing) is performed. Further, this annealing may be followed by RTP or millisecond annealing.

  Subsequently, the silicide layer 12 is formed on the surface of the gate electrode 4, the surface of the SiGe layer 10, and the surface of the impurity introduction region 8n.

  Thereafter, an interlayer insulating film and a wiring are formed to complete the semiconductor device.

  In such a first embodiment, the n-channel transistor formation scheduled region is protected by the insulating film 6 when the trench 9 is formed. Further, since this insulating film 6 is also used for forming the sidewall 6a in the p-channel transistor formation scheduled region, it hardly remains between the gate electrodes 4. That is, since the insulating film 6 is etched back in the absence of the sidewall 6a, it is removed from a wide gap as compared with the conventional method. For this reason, even if the insulating film 6 is formed so thick that the SiGe layer 10 or the like is not formed in the n-channel transistor formation scheduled region, it is not necessary to lengthen the etching time as the element isolation insulating film 2 recedes. The semiconductor device can be manufactured.

  Further, the SiGe layer 10 and the Si layer 11 are formed on the gate electrode 4 in the p-channel transistor formation scheduled region, and these are removed when the insulating film 6 in the n-channel transistor formation planned region is etched back. Therefore, it is not necessary to form a film or the like for preventing these formations on the gate electrode 4.

(Second Embodiment)
Next, a second embodiment will be described. 4A to 4D are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the second embodiment in the order of steps.

  In the second embodiment, first, as shown in FIG. 4A (a), in the p-channel transistor formation planned region 71p and the n-channel transistor formation planned region 71n, for example, a semiconductor such as a silicon substrate whose surface is a (001) plane An element isolation insulating film 22 is formed on the surface of the substrate 21. Next, a gate insulating film 23 and a gate electrode 24 are formed on the semiconductor substrate 21 in the element active region partitioned by the element isolation insulating film 22. As the gate insulating film 23, for example, a thermal oxide film or SiON film having a thickness of about 1.2 nm is formed. As a material of the gate electrode 24, for example, polycrystalline silicon is used. Thereafter, an offset film 33 is formed on the side of the gate electrode 24. The thickness (width) of the offset film 33 is 5 nm to 10 nm (for example, 8 nm). Subsequently, impurity introduction regions 25p are formed on the surface of the semiconductor substrate 21 on both sides of the gate electrode 24 in the p-channel transistor formation planned region 71p, and on both sides of the gate electrode 24 in the n-channel transistor formation planned region 71n. An impurity introduction region 25 n is formed on the surface of the semiconductor substrate 21. In the formation of the impurity introduction region 25p, for example, Sb ions, F ions, Ge ions, and B ions are introduced, and then annealing for activating these impurities is performed. In forming the impurity introduction region 25n, In ions, N ions, and As ions are introduced.

  The gate length of the gate electrode 24 is, for example, 35 nm or less, and the pitch of the adjacent gate electrodes 24 is, for example, 140 nm or less.

  Next, as shown in FIG. 4A (b), a silicon oxide film 26a and a silicon nitride film 26b are formed in this order by, for example, a CVD (chemical vapor deposition) method. The silicon oxide film 26a is formed using, for example, BTBAS (Bistal Butylaminosilane) as a silicon raw material, and the thickness thereof is 3 nm to 10 nm (for example, 5 nm). The silicon nitride film 26b is formed using BTBAS as a silicon raw material, for example, and the thickness thereof is 25 nm to 35 nm (for example, 30 nm).

  Thereafter, as shown in FIG. 4A (c), a resist pattern 27 is formed to cover the n-channel transistor formation planned region 71n and expose the p-channel transistor formation planned region 71p. Then, the silicon nitride film 26b and the silicon oxide film 26a are etched back using the resist pattern 27 as a mask. As a result, a sidewall including the offset film 33, the silicon oxide film 26a, and the silicon nitride film 26b is formed on the side of each gate electrode 24 in the p-channel transistor formation region 71p. In the etch back of the silicon nitride film 26b and the silicon oxide film 26a, for example, the silicon nitride film 26b is etched using the silicon oxide film 26a as an etching stopper, and then the silicon oxide film 26a is etched.

  Subsequently, by implanting p-type impurities, for example, B ions, using the resist pattern 27 as a mask, an impurity introduction region 28p is formed in the p-channel transistor formation planned region 71p, as shown in FIG. 4B (d). . Then, the resist pattern 27 is removed. The resist pattern 27 is removed after the sidewalls are formed, and a resist pattern that covers the n-channel transistor formation planned region 71n and exposes the p-channel transistor formation planned region 71p is newly formed before the impurity introduction region 28p is formed. May be.

  Next, as shown in FIG. 4B (e), a trench 29 that matches the outer edge of the silicon nitride film 26b is formed in the p-channel transistor formation planned region 71p. For example, the side surface of the groove 29 on the channel region side is a <111> plane. Such a groove 29 can be formed in a self-aligned manner by performing wet etching using an organic alkali solution such as TMAH (Tetra Methyl Ammonium Hydroxide) after forming a groove having a predetermined depth by dry etching. it can. The depth of the groove 29 is, for example, 20 nm to 70 nm (for example, 60 nm). Since the n channel transistor formation region 71n is covered with the silicon nitride film 26b and the silicon oxide film 26a, the groove 29 is not formed in the n channel transistor formation region 71n.

  Thereafter, as shown in FIG. 4B (f), the SiGe layer 30 is grown from the bottom of the groove 29, and the Si layer 31 is grown thereon. The thickness of the SiGe layer 30 is, for example, 30 nm to 90 nm (for example, 70 nm), and the thickness of the Si layer 31 is, for example, 5 nm to 20 nm (for example, 10 nm). The SiGe layer 30 and the Si layer 31 are also formed on the gate electrode 24. Since the n channel transistor formation planned region 71n is covered with the silicon nitride film 26b and the silicon oxide film 26a, the SiGe layer 30 and the Si layer 31 are not formed in the n channel transistor formation planned region 71n.

  Subsequently, as shown in FIG. 4C (g), the silicon nitride film 26b and the silicon oxide film 26a are etched back. As a result, a sidewall including the offset film 33, the silicon oxide film 26a, and the silicon nitride film 26b is formed on the side of each gate electrode 24 in the n channel transistor formation planned region 71n. At this time, since the silicon nitride film 26b in the p channel transistor formation scheduled region is exposed, the silicon nitride film 26b becomes thin. Further, part or all of the SiGe layer 30 and the Si layer 31 on the gate electrode 24 in the p channel transistor formation region and the Si layer 31 on the SiGe layer 30 in the trench 29 are removed. In the etch back of the silicon nitride film 26b and the silicon oxide film 26a, for example, the silicon nitride film 26b is etched using the silicon oxide film 26a as an etching stopper, and then the silicon oxide film 26a is etched.

Next, by performing ion implantation of an n-type impurity, for example, As using a resist pattern that covers the p-channel transistor formation region and exposes the n-channel transistor formation region, as shown in FIG. 4C (h) An impurity introduction region 28n is formed in the channel transistor formation planned region 71n. The formation of the impurity introduction region 28n is effective for further reducing the parasitic resistance of the source and drain of the n-channel transistor. In the formation of the impurity introduction region 28n, for example, the implantation energy is set to 10 keV to 14 keV (for example, 12 keV), and the dose amount is set to 1 × 10 ¹⁵ cm ^{−2 to} 3 × 10 ¹⁵ cm ⁻² (for example, 2 × 10 ¹⁵ cm ⁻² ). As ions are implanted. The formation of the impurity introduction region 28n may be omitted.

  Thereafter, as shown in FIG. 4C (i), an insulating film 34 is formed on the entire surface. As the insulating film 34, for example, a silicon oxide film is formed by CVD using BTBAS, and the thickness thereof is 10 nm to 25 nm (for example, 20 nm).

  Subsequently, as shown in FIG. 4D (j), the insulating film 34 is etched back. As a result, a sidewall including the offset film 33, the silicon oxide film 26a, the silicon nitride film 26b, and the insulating film 34 is formed on the side of each gate electrode 24 in the n channel transistor formation planned region 71n.

  Next, by performing ion implantation of an n-type impurity, for example, P using a resist pattern that covers the p-channel transistor formation region and exposes the n-channel transistor formation region, as shown in FIG. An impurity introduction region 35n is formed in the channel transistor formation planned region 71n. Then, annealing for activating impurities in the impurity introduction regions 25n, 28n, and 35n is performed. As this annealing, for example, millisecond level annealing or RTP is performed. Further, this annealing may be followed by RTP or millisecond annealing.

  Subsequently, a silicide layer 32 is formed on the surface of the gate electrode 24, the surface of the SiGe layer 30, and the surface of the impurity introduction region 35n. In the formation of the silicide layer 32, for example, after a pretreatment using hydrofluoric acid, a NiPt film is formed, and then a heat treatment is performed. Then, the unreacted NiPt film is removed.

  Thereafter, an interlayer insulating film and a wiring are formed to complete the semiconductor device.

  In such a second embodiment, when the trench 29 is formed, the n-channel transistor formation planned region is protected by the silicon nitride film 26b and the silicon oxide film 26a. In addition, since the silicon nitride film 26b and the silicon oxide film 26a are also used for forming the sidewalls of the p-channel transistor formation region, they are unlikely to remain between the gate electrodes 24. That is, since the silicon nitride film 26b and the silicon oxide film 26a are etched back in the absence of sidewalls, they are removed from a wide gap as compared with the conventional method. For this reason, even if the silicon nitride film 26b and the silicon oxide film 26a are formed so thick that the SiGe layer 40 or the like is not formed in the n channel transistor formation scheduled region, it is necessary to increase the etching time as the element isolation insulating film 22 recedes. In addition, a desired semiconductor device can be manufactured.

  In addition, the SiGe layer 30 and the Si layer 31 are formed on the gate electrode 24 in the p-channel transistor formation scheduled region, and these are etched back of the silicon nitride film 26b and the silicon oxide film 26a in the n-channel transistor formation planned region. Therefore, it is not necessary to form a film or the like for preventing the formation on the gate electrode 24.

  Further, in the present embodiment, since the insulating film 34 is located outside the silicon nitride film 26b in the n channel transistor formation scheduled region, the formation position of the impurity introduction region 35n is adjusted by adjusting the thickness of the insulating film 34. It can be controlled as the source / drain offset spacer of the n-channel transistor independently of the formation position of the silicon nitride film 26b which is the source / drain offset spacer (side wall insulating film) of the p-channel transistor. Generally, P used as an impurity implanted into the source / drain of an n-channel transistor has a high diffusion rate. Therefore, by increasing the thickness of the offset spacer for the source and drain of the n-channel transistor, a preferable spacer can be set for each of the p-channel transistor and the n-channel transistor even in a region where the pitch is short. Therefore, it is easier to adjust the impurity profile at the source and drain of the n-channel transistor than in the first embodiment. Further, the insulating film 34 in the p-channel transistor formation scheduled region can suppress the spread of the silicide layer 32 to the vicinity of the gate electrode 24.

(Third embodiment)
Next, a third embodiment will be described. FIG. 5A to FIG. 5B are cross-sectional views showing a method of manufacturing a semiconductor device according to the third embodiment in the order of steps.

  In the third embodiment, first, similarly to the second embodiment, the processes up to the formation of the SiGe layer 30 and the Si layer 31 are performed (FIG. 4B (f)). Next, as shown in FIG. 5A (a), an insulating film 41 is formed on the entire surface. As the insulating film 41, for example, a silicon nitride film or a silicon oxide film is formed by CVD using BTBAS, and the thickness thereof is 5 nm to 20 nm (for example, 10 nm).

  Thereafter, as shown in FIG. 5A (b), the insulating film 41 is etched back. As a result, a sidewall including the offset film 33, the silicon oxide film 26a, the silicon nitride film 26b, and the insulating film 34 is formed on the side of each gate electrode 24 in the n channel transistor formation planned region 71n. At this time, part or all of the SiGe layer 30 and the Si layer 31 on the gate electrode 24 in the p-channel transistor formation scheduled region and the Si layer 31 on the SiGe layer 30 in the trench 29 are removed.

  Subsequently, by performing ion implantation of an n-type impurity, for example, P using a resist pattern that covers the p-channel transistor formation region and exposes the n-channel transistor formation region, as shown in FIG. Impurity introduction region 35n is formed in n channel transistor formation planned region 71n. Then, annealing for activating impurities in the impurity introduction regions 25n and 35n is performed. As this annealing, for example, millisecond level annealing or RTP is performed. Further, this annealing may be followed by RTP or millisecond annealing.

  Next, the silicide layer 32 is formed on the surface of the gate electrode 24, the surface of the SiGe layer 30, and the surface of the impurity introduction region 35n. In the formation of the silicide layer 32, for example, after a pretreatment using hydrofluoric acid, a NiPt film is formed, and then a heat treatment is performed. Then, the unreacted NiPt film is removed.

  Thereafter, an interlayer insulating film and a wiring are formed to complete the semiconductor device.

  The effect similar to 2nd Embodiment is acquired also by such 3rd Embodiment. Further, since the insulating film 41 is located outside the silicon nitride film 26b in the n channel transistor formation planned region, the formation position of the impurity introduction region 35n is adjusted by adjusting the thickness of the insulating film 41. It can be controlled as an offset spacer for the source / drain of the n-channel transistor independently of the formation position of the silicon nitride film 26b which is a drain offset spacer (side wall insulating film). Generally, P used as an impurity implanted into the source / drain of an n-channel transistor has a high diffusion rate. Therefore, by increasing the thickness of the offset spacer for the source and drain of the n-channel transistor, a preferable spacer can be set for each of the p-channel transistor and the n-channel transistor even in a region where the pitch is short. Therefore, it is easier to adjust the impurity profile at the source and drain of the n-channel transistor than in the first embodiment. Further, the insulating film 41 in the p channel transistor formation scheduled region can suppress the spread of the silicide layer 32 to the vicinity of the gate electrode 24.

  In any of the embodiments, the thickness of the insulating film that covers the surface of the semiconductor substrate in the n-channel transistor formation region when the trench is formed in the surface of the semiconductor substrate in the p-channel transistor formation region is particularly limited. Not. However, as shown in FIG. 6, it is preferable that the extraction width H of the insulating film 81 is larger than zero. For example, when the pitch of the gate electrode 82 is P, the gate length is Lg, the width of the already formed spacer is Ls, and the thickness of the insulating film 81 is T, “P−Lg−2 × (Ls + T)”. It is preferable that the represented punching width H is greater than zero. Here, it is assumed that the thickness T of the insulating film 81 is the same in each direction (a direction parallel to the surface of the semiconductor substrate, a direction perpendicular to the surface, etc.). The thickness T is, for example, about 28 nm to 45 nm.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
Forming a first gate electrode in the first region of the semiconductor substrate and a second gate electrode in the second region;
Forming an insulating film covering the first region and the second region;
Forming a mask layer covering the insulating film on the second region, exposing the insulating film on the first region, and etching the insulating film using the mask layer as a mask; Forming a first sidewall on the side of the electrode;
Forming a p-type impurity introduction region by introducing p-type impurities into the surface of the semiconductor substrate using the first sidewall as a mask in the first region;
Forming a groove in the surface of the p-type impurity introduction region using the first sidewall as a mask;
Growing a SiGe layer in the trench;
Forming a second sidewall on the side of the second gate electrode by etching the insulating film after removing the mask layer;
A step of introducing an n-type impurity into the surface of the semiconductor substrate to form an n-type impurity introduction region in the second region using the second sidewall as a mask;
A method for manufacturing a semiconductor device, comprising:

(Appendix 2)
In the step of growing the SiGe layer in the trench, a SiGe layer is also grown on the first gate electrode,
The method for manufacturing a semiconductor device according to appendix 1, wherein the step of forming the second sidewall includes a step of removing the SiGe layer grown on the first gate electrode.

(Appendix 3)
The step of forming the insulating film includes
Forming a silicon oxide film;
Forming a silicon nitride film thicker than the silicon oxide film on the silicon oxide film;
The method for manufacturing a semiconductor device according to appendix 1 or 2, wherein:

(Appendix 4)
The step of forming the second sidewall includes
Etching the silicon nitride film using the silicon oxide film as an etching stopper;
Etching the silicon oxide film after etching the silicon nitride film;
The method for manufacturing a semiconductor device according to appendix 3, wherein:

(Appendix 5)
The silicon oxide film has a thickness of 3 nm to 10 nm,
The method of manufacturing a semiconductor device according to appendix 3 or 4, wherein the silicon nitride film has a thickness of 25 nm to 35 nm.

(Appendix 6)
Forming a second insulating film covering the insulating film at least in the second region between the step of growing the SiGe layer in the trench and the step of forming the second sidewall; Have
The method of manufacturing a semiconductor device according to any one of appendices 1 to 5, wherein the step of forming the second sidewall includes a step of etching the second insulating film together with the insulating film. .

(Appendix 7)
After the step of forming the n-type impurity introduction region,
Forming a third insulating film covering the insulating film at least in the second region;
Forming a third sidewall including the second sidewall and the third insulating film by etching the third insulating film;
Forming a second n-type impurity introduction region by introducing an n-type impurity into the surface of the semiconductor substrate using the third sidewall as a mask in the second region;
The method for manufacturing a semiconductor device according to any one of appendices 1 to 5, wherein:

(Appendix 8)
Between the step of forming the first gate electrode and the second gate electrode and the step of forming the insulating film,
A p-type impurity is introduced into the surface of the semiconductor substrate in the first region to form a second p-type impurity introduction region, and an n-type impurity is introduced into the surface of the semiconductor substrate in the second region. The method for manufacturing a semiconductor device according to any one of appendices 1 to 7, further comprising a step of forming a third n-type impurity introduction region.

(Appendix 9)
Between the step of forming the first gate electrode and the second gate electrode and the step of forming the second p-type impurity introduction region and the third n-type impurity introduction region,
9. The method according to claim 8, further comprising a step of forming a fourth sidewall on a side of the first gate electrode and forming a fifth sidewall on a side of the second gate electrode. A method for manufacturing a semiconductor device.

(Appendix 10)
10. The method of manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein the insulating film has a thickness of 28 nm to 45 nm.

3: Gate insulating film 4: Gate electrode 6: Insulating film 6a, 6b: Side wall 8p, 8n: Impurity introduction region 9: Groove 10: SiGe layer 51p: P channel transistor formation region 51n: N channel transistor formation region

Claims (4)

Forming a first gate electrode in the first region of the semiconductor substrate and a second gate electrode in the second region;
Forming an insulating film covering the first region and the second region;
Forming a mask layer covering the insulating film on the second region, exposing the insulating film on the first region, and etching the insulating film using the mask layer as a mask; Forming a first sidewall on the side of the electrode;
Forming a p-type impurity introduction region by introducing p-type impurities into the surface of the semiconductor substrate using the first sidewall as a mask in the first region;
Forming a groove in the surface of the p-type impurity introduction region using the first sidewall as a mask;
Growing a SiGe layer in the trench;
Forming a second sidewall on the side of the second gate electrode by etching the insulating film after removing the mask layer;
A step of introducing an n-type impurity into the surface of the semiconductor substrate to form an n-type impurity introduction region in the second region using the second sidewall as a mask;
I have a,
In the step of growing the SiGe layer in the trench, a SiGe layer is also grown on the first gate electrode,
Said step of forming a second sidewall, a method of manufacturing a semiconductor device which is characterized in that have a step of removing the SiGe layer grown on said first gate electrode. The step of forming the insulating film includes
Forming a silicon oxide film;
Forming a silicon nitride film thicker than the silicon oxide film on the silicon oxide film;
The method of manufacturing a semiconductor device according to claim 1, wherein: The step of forming the second sidewall includes
Etching the silicon nitride film using the silicon oxide film as an etching stopper;
Etching the silicon oxide film after etching the silicon nitride film;
The method of manufacturing a semiconductor device according to claim 2 , wherein: Forming a second insulating film covering the insulating film at least in the second region between the step of growing the SiGe layer in the trench and the step of forming the second sidewall; Have
The step of forming the second sidewall, the manufacture of a semiconductor device according to the any one of claims 1 to 3, comprising a step of etching the second insulating film with the insulating film Method.

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