JP5351863B2 - Nonvolatile semiconductor memory device and control method of nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively prevent a deterioration in a variable resistive element of an RRAM by suppressing variations of resistive states. <P>SOLUTION: A memory cell array 10 provided with a plurality of memory cells M provided with a variable resistive element R whose electric resistance changes to two or more different resistive states, a determination circuit for partitioning the range of resistance values, which the variable resistive element R can take, into a plurality of target ranges and a plurality of middle ranges and determining whether the resistance value of the memory cell M is within any range among the plurality of target ranges and the plurality of middle ranges, and a write circuit 13 for applying a voltage pulse to the variable resistive element R so as to make a resistance value be within one range among the target ranges and writing information in the memory cells M are provided. Two or more middle ranges exist between two adjacent target ranges. In the determination circuit, a voltage pulse is applied to a memory cell M in which the resistance value of the memory cell M is not determined to be within a predetermined target range on a first application condition set differently at least in each middle range. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention includes a plurality of memory cells including variable resistance elements capable of storing information by changing an electric resistance to two or more different resistance states by application of a voltage pulse and holding the resistance state in a nonvolatile manner. The present invention relates to a nonvolatile semiconductor memory device including a memory cell array.

  Conventionally, flash memories have been widely used as large-capacity and inexpensive nonvolatile memories. However, in recent years, the limit of miniaturization of flash memory has become apparent, and as a next-generation non-volatile random access memory (NVRAM) capable of high-speed operation instead of flash memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM) ), OUM (Ovonic Unified Memory), RRAM (resistance change memory: RRAM is a registered trademark), etc., are actively developed.

  Among these nonvolatile memories, the RRAM can be rewritten at high speed, and can be easily manufactured because a simple binary transition metal oxide can be used as a material, and has high compatibility with an existing CMOS process. It is attracting attention because of its advantages.

  As shown in FIG. 7, the RRAM is composed of a variable resistance element R including a first electrode 101, a second electrode 102, and a variable resistor 102 interposed between the first electrode 101 and the second electrode 103. Has been. By applying a voltage pulse as an electrical stress between the first electrode 101 and the second electrode 102, the electric resistance of the variable resistor 102 is reversibly and non-volatilely changed to two or more resistance states (switching operation) This allows information to be stored in a nonvolatile manner.

As a material of the variable resistor 102, for example, there is a perovskite material known for its supergiant magnetoresistance effect (see, for example, Patent Document 1 and Non-Patent Document 1). As the perovskite material, for example, there is a crystalline praseodymium / calcium / manganese oxide Pr _1-X Ca _X MnO ₃ (PCMO) film which is a perovskite oxide (see Patent Document 1). Examples of other materials of the variable resistor 102 include a titanium oxide (TiO ₂ ) film, a nickel oxide (NiO) film, a zinc oxide (ZnO) film, and niobium oxide (Nb ₂ O), which are transition metal oxides. ₅ ) There is a film (for example, see Patent Document 2 and Non-Patent Document 2). Note that when a transition metal oxide such as titanium oxide or nickel oxide is used as the variable resistor 102, a region in which the resistivity is locally reduced in the oxide due to a heat increase due to a current flowing into the variable resistance element R (hereinafter, referred to as “the variable resistor 102”) It is considered that a resistance change is caused by forming or disassembling (referred to as “filament path” as appropriate) (see Non-Patent Document 3).

US Pat. No. 6,204,139 JP 2002-537627 A

Liu, S .; Q. Et al., “Electric-pulse-induced reversible resistance change effect in magnetosensitive films”, Applied Physics Letters, 2000, Vol. 76, p. 2749-2751 H. Pagna, et al., “Bistable Switching in Electroformed Metal-Insulator-Metal Devices”, Phys. Stat. Sol. (A), 1988, vol. 108, p. 11-65 G. Dearnaley et al., “Electrical phenomena in amorphous oxide films”, Rep. Prog. Phys., 1970, Vol. 33, p.1129-1191

  Here, FIG. 8 shows IV characteristics when the variable resistance element R changes between two resistance states, that is, a high resistance state and a low resistance state.

  More specifically, FIG. 8A shows the IV characteristics when the resistance state is in the target range which is the target resistance value range when the writing process to the high resistance state is performed. FIG. 8B shows the IV characteristics when the resistance state is in the target range when the writing process to the low resistance state is performed, and FIG. 8C shows the case when the writing process to the high resistance state is performed. FIG. 8D shows the IV characteristics when the resistance state is not within the target range when the writing process to the low resistance state is performed, respectively. .

  In the case of a memory cell written in a high resistance state, when the resistance state is in the target range, as shown in FIG. 8A, the non-linearity is strong, but when the resistance state is not in the target range, That is, when the writing is insufficient, the nonlinear characteristic is weak as shown in FIG. Similarly, in the case of the memory cell written in the low resistance state, as shown in FIG. 8B, when the resistance state is in the target range, the characteristic exhibits strong linearity, and the resistance state is not in the target range. That is, when the writing is insufficient, as shown in FIG. 8D, a characteristic with low linearity is exhibited.

  Such variation in the resistance state after the writing process affects the deterioration of the variable resistance element R. For example, as shown in FIG. 8C, a memory cell whose resistance state is not in the target range when writing to the high resistance state is changed to the low resistance state under the same voltage condition as other memory cells whose resistance state is in the target range. When the above writing process is performed, writing becomes excessive and the variable resistance element R may be deteriorated. Here, FIG. 9 and FIG. 10 show changes in the resistance state when the resistance state is transitioned between the high resistance state and the low resistance state, and RESET is when the writing process to the high resistance state is performed. , SET indicates the resistance state when the writing process to the low resistance state is performed. FIG. 9 shows a transition of a memory cell whose resistance state is within a target range, that is, a non-degraded memory cell, and FIG. 10 shows a transition of a degraded memory cell for two samples. Compared to FIG. 9, in FIG. 10, one sample cannot obtain a desired resistance state after the writing process to the low resistance state of SET 2, especially in the writing process to the high resistance state of RESET 3. I understand that. Similarly, for the other sample, it can be seen that a desired resistance state cannot be obtained after the writing process to the low resistance state of SET3, especially in the writing process to the high resistance state of RESET4.

  Accordingly, it is important to suppress variations in the resistance state of the memory cell in the RRAM from the viewpoint of the reliability of the nonvolatile semiconductor memory device, and the nonvolatile semiconductor memory device capable of suppressing the variation in the resistance state of the memory cell. Is desired.

  As a method for suppressing variation in the resistance state of the memory cell, for example, the writing process to the high resistance state is performed again on the memory cell whose resistance state does not reach the target range in the writing process to the high resistance state. Can be considered. However, depending on the setting of the voltage value and the pulse width of the voltage pulse of the writing process, there is a possibility that the memory cell having a small difference in resistance value from the target range becomes overwritten. FIG. 11 shows the relationship between the number of times of overwriting and the deterioration of the variable resistance element R, and shows that the overwriting may lead to the deterioration of the variable resistance element R and cause erroneous writing.

  The present invention has been made in view of the above problems, and an object of the present invention is to effectively prevent deterioration of the variable resistance element of the RRAM by suppressing variation in resistance state.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention changes its electric resistance to two or more different resistance states by applying a voltage pulse, and stores information by holding the resistance state in a nonvolatile manner. A memory cell array including a plurality of memory cells each including a variable resistance element, and a resistance value range of the variable resistance element is divided into a plurality of target ranges and a plurality of intermediate ranges; Is a determination circuit that performs a determination process for determining which one of the plurality of target ranges and the plurality of intermediate ranges is within, and a resistance value of the variable resistance element is 1 in the target range. And a writing circuit for writing information to the memory cell by applying a voltage pulse so as to be within one range, wherein there are two or more intermediate ranges between two adjacent target ranges, To said memory cell resistance is determined to be in the intermediate range in the determination circuit, and applying a voltage pulse in the first application condition set by the intermediate range.

  Furthermore, the nonvolatile semiconductor memory device having the above characteristics includes a plurality of resistance values for determining whether the resistance value of the variable resistance element is within the plurality of the target ranges or the plurality of the intermediate ranges. Preferably, a reference circuit having a reference level is provided, and the determination circuit compares the resistance value of the variable resistance element or its converted value with each of the reference levels to perform the determination process.

  Further, in the nonvolatile semiconductor memory device having the above characteristics, the write circuit applies a voltage pulse to the variable resistance element of the selected memory cell to be written under a predetermined second application condition during a write operation. The determination circuit performs the determination process on the selected memory cell after the write process, and the write circuit has a resistance value in one of the intermediate ranges after the determination process in the write operation. Preferably, a voltage pulse is applied to the variable resistance element of the selected memory cell determined to be under the first application condition.

  Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, the determination circuit performs the determination process on a selected memory cell to be read during a read operation, and the resistance value of the variable resistance element is one in the intermediate range. Output the information value corresponding to the target range closest to the intermediate range, and the write circuit has a resistance value after the determination process in the read operation, for the selected memory cell determined to be in the intermediate range Preferably, a voltage pulse is applied to the variable resistance element of the selected memory cell determined to be in one of the above conditions under the first application condition.

  Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, the determination circuit performs the determination process on the selected memory cell to be refreshed during the refresh operation, and the write circuit performs the determination process in the refresh operation, Preferably, a voltage pulse is applied under the first application condition to the variable resistance element of the selected memory cell that has been determined to have a resistance value in one of the intermediate ranges.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention changes its electric resistance to two or more different resistance states by applying a voltage pulse, and stores information by holding the resistance state in a nonvolatile manner. A method for controlling a nonvolatile semiconductor memory device including a memory cell array including a plurality of memory cells each including a variable resistance element, wherein a resistance value range that the variable resistance element can take is set to a plurality of target ranges and a plurality of target ranges. The intermediate range is divided into two or more intermediate ranges between two adjacent target ranges, and the resistance value of the memory cell is within any range of the plurality of target ranges and the plurality of intermediate ranges. A determination step for performing a determination process for determining whether or not the resistance value is in the intermediate range for the memory cell in which the resistance value is determined to be in the intermediate range in the determination step. And executes a voltage applying step of applying a voltage pulse in the first application condition.

  According to the nonvolatile semiconductor memory device having the above characteristics, when the resistance value of the variable resistance element is in the intermediate range, the voltage pulse is applied under the first application condition set for each intermediate range. Alternatively, a voltage pulse corresponding to the difference between the resistance value corresponding to the upper limit value and the resistance value of the variable resistance element can be applied. As a result, the possibility that the variable resistance element is overwritten is reduced, so that the deterioration of the variable resistance element can be more effectively prevented.

  Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, when configured to output an information value corresponding to the closest target range for a selected memory cell in which the resistance value of the variable resistance element is in the intermediate range during a read operation, The read operation can be performed more appropriately for the selected memory cell whose resistance value of the variable resistance element is outside the target range. Further, in the nonvolatile semiconductor memory device having the above characteristics, if the voltage pulse is applied to the selected memory cell having the resistance value of the variable resistance element in the intermediate range during the read operation, the read disturb is achieved. Thus, the resistance value of the selected memory cell in which the resistance value of the variable resistance element is out of the target range can be set within the target range, so that deterioration of the variable resistance element can be more effectively prevented.

  In the nonvolatile semiconductor memory device having the above characteristics, for example, the first application condition is applied to a selected memory cell in which the resistance value of the variable resistance element is not within the target range as a refresh operation during a period in which no write operation or read operation is performed. If the voltage pulse is applied at the same time, the resistance value of the selected resistance memory cell whose resistance value is outside the target range due to deterioration over time can be set within the target range. Can be more effectively prevented.

1 is a schematic block diagram illustrating a schematic configuration example of a nonvolatile semiconductor memory device according to the present invention. 1 is a schematic block diagram showing a schematic configuration example of a memory cell array of a nonvolatile semiconductor memory device according to the present invention. It is a schematic block diagram shown about an example of the setting of a target range and an intermediate range. 3 is a flowchart showing an example of a method for controlling a nonvolatile semiconductor memory device according to the present invention. 3 is a flowchart showing an example of a method for controlling a nonvolatile semiconductor memory device according to the present invention. 3 is a flowchart showing an example of a method for controlling a nonvolatile semiconductor memory device according to the present invention. It is a schematic block diagram which shows the schematic structural example of the memory cell of RRAM. It is a graph which shows the IV characteristic of the variable resistance element of RRAM. It is a graph which shows the change of a resistance state at the time of changing the resistance state of the variable resistance element of RRAM between a high resistance state and a low resistance state. It is a graph which shows the change of a resistance state at the time of changing the resistance state of the variable resistance element of RRAM between a high resistance state and a low resistance state. It is a graph which shows the relationship between the frequency | count of overwriting and deterioration of the variable resistance element of RRAM.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a nonvolatile semiconductor memory device and a method for controlling the nonvolatile semiconductor memory device according to the present invention (hereinafter simply referred to as “device of the present invention” and “method of the present invention” as appropriate) will be described below with reference to the drawings.

  First, the configuration of the device of the present invention will be described with reference to FIGS. 1 and 2.

  As shown in FIG. 1 and FIG. 2, the device 1 of the present invention changes its electric resistance to two or more different resistance states by applying a voltage pulse, and can store information by holding the resistance state in a nonvolatile manner. A memory cell array 10 including a plurality of memory cells M each including a resistance element R, a control circuit 11 for controlling the operation of the device 1 of the present invention, and a plurality of types of voltages or a plurality of types of currents applied to the memory cells M are generated. A voltage pulse is applied to the selected memory cell M to be processed through the voltage generation circuit 12, the sense circuit 16 that compares the output from the memory cell array 10 using the reference circuit 17, and the word line decoder 14 and the bit line decoder 15. Thus, a write circuit 13 for performing a write operation is provided.

  As shown in FIG. 2, the memory cell array 10 includes m × n memory cells M. However, m and n are integers of 1 or more. The memory cell Mij (i = 1 to m, j = 1 to n) includes a MOS transistor T having a gate terminal connected to the word line WLj, a source terminal connected to the source line SLj, and one end connected to the bit line BLi. The variable resistor element R is connected to the drain terminal of the MOS transistor T.

  The configuration of the variable resistance element R is the same as that of the conventional variable resistance element R shown in FIG. 7. In this embodiment, the variable resistance body 102 is HfOx, and the first electrode 101 and the second electrode 103 are both TiN. A case where the resistance value of the variable resistance element R is configured and changes between two resistance states of a high resistance state and a low resistance state will be described. In the present embodiment, it is assumed that the resistance value of the variable resistance element R changes between two resistance states, ie, a high resistance state and a low resistance state. It may be a variable resistance element R that changes between resistance states.

  Furthermore, in the present embodiment, the case where the variable resistor 102 is composed of HfOx and the first electrode 101 and the second electrode 103 are both composed of TiN will be described. However, the present invention is not limited to this. As a material of the variable resistor 102, not only HfOx but also a known variable resistance material whose resistance is changed by voltage application with a metal oxide such as CoO, NiO, TaOx, TiOx, ZrOx, AlOx, CuOx, and NbOx, for example. Can be used. The material of the first electrode 101 varies depending on whether the metal oxide constituting the variable resistor 102 is an n-type semiconductor or a p-type semiconductor. When the variable resistor 102 is an n-type semiconductor such as TiOx or TaOx, a metal having a work function larger than 4.5 eV such as Pt or TiN is used as the material of the first electrode 101, and the variable resistor 102 is CoO. In the case of a p-type semiconductor such as NiO, a metal such as Ti or Ta having a work function smaller than 4.5 eV is used, and a Schottky is interposed between the first electrode 101 and the metal oxide constituting the variable resistor 102. By using a combination that can provide a barrier, it is desirable that the variable resistance element R can obtain good switching characteristics (transition characteristics of a resistance state between a high resistance state and a low resistance state). As a material of the second electrode 103, for example, a metal oxide or a metal nitride containing any of metals selected from Ti, Ta, Hf, or Zr can be considered.

  Although not shown, the control circuit 11 includes an address buffer that stores an externally input address signal, and a data buffer that stores an externally input data signal during a write operation and stores a data signal output externally during a read operation. In this configuration, a control signal indicating a write operation or a read operation is received from the outside, and a write operation, a write verify operation, a read operation, and a self-refresh operation, which will be described later, are controlled. Also, the refresh operation is controlled based on the internal instruction. Note that the writing operation and the reading operation may be controlled by an internal instruction.

  The word line decoder 14 is connected to the word lines WL1 to WLn and separated into a selected word line and a non-selected word line, and each of a write operation, a write verify operation, a read operation, a self-refresh operation, and a refresh operation described later is performed. For each operation, the selected word line voltage VWL1 and the unselected word line voltage VWL0 are applied. The MOS transistor T of the memory cell M connected to the word line to which the selected word line voltage VWL1 is applied is turned on, and the MOS transistor T of the memory cell M connected to the word line to which the unselected word line voltage VWL0 is applied is turned off. It becomes a state.

  The bit line decoder 15 is connected to the bit lines BL1 to BLm and separated into a selected bit line and a non-selected bit line, and a write operation, a write verify operation, a read operation, a self-refresh operation, For each refresh operation, the selected bit line voltage VBL1 and the unselected bit line voltage VBL0 are applied under a first application condition described later. The bit line to which the selected bit line voltage VBL1 is applied is selected, and the bit line to which the unselected bit line voltage VBL0 is applied is not selected.

  The voltage generation circuit 12 is configured to select the selected word line voltage VWL1 and non-voltage under a first application condition set for each of a write operation, a write verify operation, a read operation, a self-refresh operation, and a refresh operation for a memory cell M to be described later. Voltages such as a selected word line voltage VWL0, a selected bit line voltage VBL1, and a non-selected bit line voltage VBL0 are generated.

  The write circuit 13 is connected to the voltage generation circuit 12, the word line decoder 14, the bit line decoder 15, a sense circuit 16 and a reference circuit 17 which will be described later, and the voltage generated by the voltage generation circuit 12 is transferred to the word line decoder 14 and the bit line. The information is supplied to the decoder 15 and receives information on the resistance value of the variable resistance element R of the selected memory cell M from a sense circuit 16 to be described later.

  The sense circuit 16 (determination circuit) is connected to the source lines SL1 to SLn, and the source lines SL1 to SLn are read in a write verify operation, a read operation, a self-refresh operation, and a refresh operation for a memory cell M described later. Is detected separately for the selected source line and the non-selected source line, and the level (converted value of the resistance value of the variable resistance element R) obtained by converting the current value of the current into a voltage is determined by the plurality of reference circuits 17. Compared with a reference level (here, a voltage value), the resistance value of the variable resistance element R of the selected memory cell M is detected. The sense circuit 16 of the present embodiment is assumed to be a voltage differential sense circuit. However, the current value is a converted value of the resistance value of the variable resistance element R, and the current differential sense circuit is configured. You may do it. Further, the reference circuit 17 of the present embodiment is configured by a resistance element having a resistance value corresponding to the resistance value of the variable resistance element R.

  More specifically, the sense circuit 16 of the present embodiment divides the range of resistance values that can be taken by the variable resistance element R into a plurality of target ranges and a plurality of intermediate ranges, and the resistance values of the memory cells M are plural. A determination process for determining which of the target range and the plurality of intermediate ranges are within the range is performed.

  Here, FIG. 3 shows an example of setting of the target range and the intermediate range, and there are two or more intermediate ranges between two adjacent target ranges. In the present embodiment, as described above, since the resistance value of the variable resistance element R changes between the two resistance states of the high resistance state and the low resistance state, the target range A1 corresponding to the high resistance state, the low resistance state And an intermediate range A2 to A5 obtained by dividing the range between the target range A1 and the target range A6 into four. In the reference circuits 17a to 17e, reference levels corresponding to the resistance values Ref1 to Ref5 at the boundaries of the target ranges A1 and A6 and the intermediate ranges A2 to A5, respectively, are set here as voltage values as converted resistance values. Has been. The sense circuit 16 performs a determination process by comparing the output from the memory cell array 10 indicating the resistance value of the variable resistance element R with each of the reference levels Ref1 to Ref5.

  Next, the method of the present invention will be described with reference to FIGS.

<Control method during write operation>
The method of the present invention during the write operation will be described with reference to FIG.

  When a control signal instructing a write operation is input from the outside, the control circuit 11 receives an address signal and a data signal, and the write circuit 13 is a variable resistance element of the selected memory cell M to be written that is specified by the address signal. A write process is performed on R by applying a voltage pulse under a predetermined second application condition via the word line decoder 14 and the bit line decoder 15 (step # 100). Here, the case where the expected value of the selected memory cell M indicated by the data signal is a value corresponding to the high resistance state, and the selected memory cell M is written from the low resistance state to the high resistance state (RESET operation) will be described.

  Subsequently, the device 1 of the present invention performs a write verify process (step # 110). Specifically, in the write verify process, first, the sense circuit 16 compares the level of the output signal from the memory cell array 10 with the reference level of the reference circuit 17 and performs a determination process on the selected memory cell M (step # 111). ).

  Here, the level of the output signal is a level obtained by converting the current value flowing according to the resistance value of the selected memory cell into a voltage, and the voltage level of the output signal increases as the resistance value increases. The reference level is a value obtained by converting resistance values corresponding to the upper limit value and the lower limit value of the intermediate range into voltage values in the same manner.

  The determination process here is performed by comparing the level of the output signal from the memory cell array 10 with the five reference levels Ref1 to Ref5 shown in FIG. When the level of the output signal from the memory cell array 10 is higher than the reference levels Ref1 to Ref5, and H when the level is low, the resistance value of the variable resistance element R of the selected memory cell M is determined when the determination result is (HHHHH). It can be determined that the target range is A1. Similarly, if the determination result is (LHHHH), it is in the intermediate range A2, if the determination result is (LLHHH), it is in the intermediate range A3, if the determination result is (LLLLHH), it is in the intermediate range A4, and the determination result is (LLLLH). ) Can be determined to be in the intermediate range A5, and if the determination result is (LLLLLL), it can be determined to be in the target range A6.

  Subsequently, when the device 1 of the present invention determines that the resistance value of the variable resistance element R of the selected memory cell M is within the target range A1 as a result of the determination processing (“YES” branch in step # 112), the write processing is performed. It is determined that the processing has been completed normally, and the write verify process is terminated.

  Furthermore, as a result of the determination process, the device 1 of the present invention applies a first application condition to the variable resistance element R of the selected memory cell M in which the resistance value is determined to be outside the target range corresponding to the expected value. Apply a voltage pulse. In the present embodiment, the first application condition is set for the target range A6 in addition to each of the intermediate ranges A2 to A5. Specifically, when the device 1 of the present invention determines that the resistance value of the variable resistance element R of the selected memory cell M is not within the target range A1 (“NO” branch at step # 112), the writing process is performed normally. The write circuit 13 determines that it has not been completed, and applies a voltage pulse to the variable resistance element R of the selected memory cell M under the first application condition set for each of the intermediate ranges A2 to A5 and the target range A6 (step) # 113). Here, as the first application condition, the voltage value of the voltage pulse is set for each of the intermediate ranges A2 to A5 and the target range A6. More specifically, a voltage pulse having a voltage V1 pulse width T1 in the intermediate range A2, a voltage pulse having a voltage V2 pulse width T2 in the intermediate range A3, and a voltage pulse having a voltage V3 pulse width T3 in the intermediate range A4. If the voltage pulse is a voltage pulse having a voltage V4 pulse width T4 in the case of the intermediate range A5 and a voltage pulse having a voltage V5 pulse width T5 in the case of the target range A6, then the difference in resistance value from the target range A1 is It is set to | V1 | <| V2 | <| V3 | <| V4 | <| V5 | so that the voltage value of the voltage pulse increases as the value increases. The first application condition is that | T1 | <| T2 | <| T3 | <| T4 | <| T5 so that the pulse width of the voltage pulse increases as the difference in resistance value from the target range A1 increases. It may be set to |, or both the pulse width and the voltage value may be set for each of the intermediate ranges A2 to A5 and the target range A6. Note that the first application condition of the target range A6 may be the same as the second application condition.

  Subsequently, the device 1 of the present invention again executes the write verify process from step # 111 on the selected memory cell M to which the voltage pulse has been applied under the first application condition (step # 110).

  Here, the case where a write instruction is given from the outside has been described, but the method of the present invention at the time of a write operation can be similarly applied to the case where a write instruction is given internally.

  Further, the case where the selected memory cell M is written from the low resistance state to the high resistance state (RESET operation) has been described, but the same applies to the case where the selected memory cell M is written from the high resistance state to the low resistance state (SET operation). Specifically, if a voltage pulse having a voltage V0 pulse width T0 is used in the case of the target range A1, writing is performed so as to become the target range A6. Therefore, as the difference in resistance value from the target range A6 increases, the voltage pulse voltage | V0 |> | V1 |> | V2 |> | V3 |> | V4 | is set so as to increase the value. Note that | T0 |> | T1 |> | T2 |> | T3 |> | T4 | may be set so that the pulse width of the voltage pulse increases as the difference in resistance value from the target range A6 increases. Both the voltage value and the pulse width may be set separately for the intermediate range A2 to A5 and the target range A1.

<Control method during read operation>
The method of the present invention during the read operation will be described with reference to FIG.

  When a control signal for instructing a read operation is input from the outside, the control circuit 11 receives an address signal and performs a read process of reading data in the selected memory cell M indicated by the address (step # 200).

  Specifically, when the device 1 of the present invention starts the reading process, the sense circuit 16 compares the level of the output signal from the memory cell array 10 with the reference level of the reference circuit 17 to determine the selected memory cell M. Is performed (step # 201). Here, as in the case of the writing process, the level of the output signal from the memory cell array 10 is compared with the five reference levels Ref1 to Ref5 shown in FIG.

  Subsequently, when it is determined by the sense circuit 16 that the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate range A2 to A5 (the “intermediate range” branch in step # 202), the device 1 of the present invention. The control circuit 11 outputs an information value corresponding to the target range closest to the determined intermediate range as the information value of the selected memory cell M (step # 203). Here, if the resistance value of the variable resistance element R of the selected memory cell M is larger than Ref0 (= Ref3) shown in FIG. 3, it is determined as the high resistance state, and an information value corresponding to the high resistance state is output. If it is smaller, it is judged as a low resistance state and an information value corresponding to the low resistance state is output. That is, if the sense circuit 16 determines that the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate ranges A2 and A3, the control circuit 11 outputs an information value corresponding to the target range A1 to the outside, When the sense circuit 16 determines that the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate ranges A4 and A5, the control circuit 11 outputs an information value corresponding to the target range A6 to the outside.

  Further, when the sense circuit 16 determines that the resistance value of the variable resistive element R of the selected memory cell M is within the target range A1 (the “target range” branch in step # 202), the device 1 of the present invention performs control. When the circuit 11 outputs the information value corresponding to the target range A1 to the outside (step # 204) and the sense circuit 16 determines that the resistance value is in the target range A6 ("target range" branch in step # 202) ) The information value corresponding to the target range A6 is externally output (step # 204), and the reading process (step # 200) for the selected memory cell M is completed.

  Subsequently, the device 1 of the present invention performs a self-refresh process for the selected memory cell M in which the resistance value is determined to be in one of the intermediate ranges in the previous determination process (step # 210). Specifically, the write circuit 13 of the device 1 of the present invention applies a voltage pulse under the first application condition to the variable resistance element R of the selected memory cell M whose resistance value is determined to be in one of the intermediate ranges. (Step # 211).

  More specifically, when the resistance value of the variable resistance element R of the selected memory cell M is in the intermediate ranges A2 and A3, the voltage pulse is applied under the first application condition set to be the target range A1. Here, the first application condition is that when a voltage pulse having a voltage V6 pulse width T6 is used in the case of the intermediate range A2, and a voltage pulse having a voltage V7 pulse width T7 is used in the case of the intermediate range A3, | V6 | <| V7 | is set so that the voltage value of the voltage pulse increases as the difference in resistance value increases. The first application condition may be set to | T6 | <| T7 | so that the pulse width of the voltage pulse increases as the resistance value difference from the target range A1 increases. Both voltage values may be set separately for the intermediate ranges A2 and A3.

  Further, when the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate ranges A4 and A5, the voltage pulse is applied under the first application condition set to be the target range A6. Here, if the first application condition is to use a voltage pulse with a voltage V8 pulse width T8 in the case of the intermediate range A4 and a voltage pulse with a voltage V9 pulse width T9 in the case of the intermediate range A5, respectively, | V8 |> | V9 | is set so that the voltage value of the voltage pulse increases as the difference in resistance value increases. The first application condition may be set to | T8 |> | T9 | so that the pulse width of the voltage pulse increases as the difference in resistance value from the target range A6 increases. Both voltage values may be set separately for the intermediate ranges A4 and A5.

  Subsequently, the device 1 of the present invention performs a determination process on the selected memory cell M to which the voltage pulse has been applied under the first application condition (step # 212). When the resistance value of the variable resistance element R is in the target range A1 or A6, the process ends (the “target range” branch in step # 213), and the resistance value of the variable resistance element R is in the intermediate range A2 to A5 Performs the self-refresh process again from step # 211 ("intermediate range" branch in step # 213).

  Here, the case where a read instruction is given from the outside has been described, but the method of the present invention at the time of a read operation can be similarly applied to the case where a read instruction is given internally.

<Control method during refresh operation>
The method of the present invention during the refresh operation will be described with reference to FIG.

  In the present embodiment, the device 1 of the present invention is configured to automatically perform a refresh operation at regular time intervals when a write operation and a read operation are not instructed for a constant time.

  In the device 1 of the present invention, when the refresh operation is started, the sense circuit 16 reads the selected memory cell M to be refreshed and performs a determination process (step # 301).

  When it is determined that the resistance value of the variable resistive element R of the selected memory cell M is within the target range A1 or A6 (the “target range” branch in Step # 302), the device 1 of the present invention 1 applies to the selected memory cell M. The refresh process ends.

  When it is determined that the resistance value of the variable resistive element R of the selected memory cell M is in one of the intermediate ranges A2 to A5 (the “intermediate range” branch in step # 302), the device 1 of the present invention 1 However, a voltage pulse is applied to the variable resistance element R of the selected memory cell M under the first application condition. More specifically, when the resistance value of the variable resistance element R of the selected memory cell M is in the intermediate ranges A2 and A3, the voltage pulse is applied under the first application condition set to be the target range A1. Here, when the first application condition is that a voltage pulse having a voltage V10 pulse width T10 is used in the case of the intermediate range A2, and a voltage pulse having a voltage V11 pulse width T11 is used in the case of the intermediate range A3, | V10 | <| V11 | is set so that the voltage value of the voltage pulse increases as the difference in resistance value increases. The first application condition may be set to | T10 | <| T11 | so that the pulse width of the voltage pulse increases as the difference in resistance value from the target range A1 increases. Both voltage values may be set separately for the intermediate ranges A2 and A3.

  Further, when the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate ranges A4 and A5, the voltage pulse is applied under the first application condition set to be the target range A6. Here, if the first application condition is to use a voltage pulse having a voltage V12 pulse width T12 in the case of the intermediate range A4 and a voltage pulse having a voltage V13 pulse width T13 in the case of the intermediate range A5, respectively, | V12 |> | V13 | is set so that the voltage value of the voltage pulse increases as the difference in resistance value increases. The first application condition may be set to | T12 |> | T13 | so that the pulse width of the voltage pulse increases as the resistance value difference from the target range A6 increases. Both voltage values may be set separately for the intermediate ranges A4 and A5.

  Subsequently, the device 1 of the present invention executes the determination process of step # 301 for the selected memory cell M to which the voltage pulse has been applied under the first application condition.

  Although the refresh operation has been described here, it may be applied to an operation other than the read operation and the refresh operation and the expected value is unknown. Further, although the case where the refresh operation is executed based on the internal instruction has been described, the refresh operation may be executed based on the external instruction.

<Another embodiment>
In the above embodiment, the case where a plurality of reference circuits 17 are provided has been described. However, the present invention is not limited to this. For example, when the reference circuit 17 capable of arbitrarily changing the reference level is provided, the reference level is appropriately changed to determine which of the plurality of target ranges and the plurality of intermediate ranges are within the range. It may be configured.

DESCRIPTION OF SYMBOLS 1 Nonvolatile semiconductor memory device 10 concerning this invention Memory cell array 11 Control circuit 12 Voltage generation circuit 13 Write circuit 14 Word line decoder 15 Bit line decoder 16 Sense circuit (determination circuit)
Reference circuit 101 First electrode 102 Variable resistor 103 Second electrode M Memory cell R Variable resistance element T MOS transistor WL Word line BL Bit line SL Source line

Claims (6)

A memory cell array including a plurality of memory cells each including a variable resistance element capable of storing information by changing the electrical resistance to two or more different resistance states by applying a voltage pulse and holding the resistance state in a nonvolatile manner;
A range of resistance values that the variable resistance element can take is divided into a plurality of target ranges and a plurality of intermediate ranges, and the resistance value of the memory cell is any one of the plurality of target ranges and the plurality of intermediate ranges. A determination circuit for performing a determination process for determining whether or not it is within a range;
A write circuit that writes information into the memory cell by applying a voltage pulse so that the resistance value of the variable resistance element is within one of the target ranges, and
There are two or more intermediate ranges between two adjacent target ranges,
A nonvolatile semiconductor memory device, wherein a voltage pulse is applied to the memory cell whose resistance value is determined to be in the intermediate range by the determination circuit under a first application condition set for each intermediate range. A reference circuit having a plurality of reference levels for determining which of a plurality of the target ranges and a plurality of intermediate ranges the resistance value of the variable resistance element is in;
The nonvolatile semiconductor memory device according to claim 1, wherein the determination circuit performs the determination process by comparing a resistance value of the variable resistance element or a converted value thereof with each of the reference levels. The write circuit performs a write process by applying a voltage pulse to the variable resistance element of the selected memory cell to be written under a predetermined second application condition during a write operation,
The determination circuit performs the determination process on the selected memory cell after the write process,
After the determination process in the write operation, the write circuit applies a voltage pulse to the variable resistance element of the selected memory cell in which the resistance value is determined to be in one of the intermediate ranges under the first application condition. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is applied. The determination circuit performs the determination process on a selected memory cell to be read during a read operation, and the selected memory cell in which the resistance value of the variable resistance element is determined to be in one of the intermediate ranges. Outputting an information value corresponding to the target range closest to the intermediate range;
After the determination process in the read operation, the write circuit applies a voltage pulse under the first application condition to the variable resistance element of the selected memory cell determined to have a resistance value in one of the intermediate ranges. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is applied. The determination circuit performs the determination process on a selected memory cell to be refreshed during a refresh operation,
After the determination process in the refresh operation, the write circuit applies a voltage pulse under the first application condition to the variable resistance element of the selected memory cell in which the resistance value is determined to be in one of the intermediate ranges. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is applied. A memory cell array including a plurality of memory cells each including a variable resistance element capable of storing information by changing an electric resistance to two or more different resistance states by applying a voltage pulse and holding the resistance state in a nonvolatile manner. A method for controlling a nonvolatile semiconductor memory device, comprising:
A range of resistance values that the variable resistance element can take is divided into a plurality of target ranges and a plurality of intermediate ranges,
There are two or more intermediate ranges between two adjacent target ranges,
A determination step of performing a determination process for determining which of the plurality of target ranges and the plurality of intermediate ranges the resistance value of the memory cell is within;
Performing a voltage application step of applying a voltage pulse to the memory cells determined to have a resistance value in the intermediate range in the determination step under a first application condition set for each of the intermediate ranges. A method for controlling a nonvolatile semiconductor memory device.

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