JP5237600B2 - Display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a display device and a manufacturing method thereof, and particularly relates to a display device including a light emitting element and a manufacturing method thereof.

  An organic EL (Electro Luminescence) display device is known as one of display devices including a light emitting element (for example, Patent Document 1). The organic EL display device is a self-luminous display device in which the organic EL itself emits light. Unlike a liquid crystal display device, an organic EL display device does not require a backlight, and thus display with low power consumption is possible.

  In an organic EL display device, a plurality of light emitting elements serving as pixels, that is, organic EL elements are arranged in a matrix. The organic EL element emits light by current drive, and the light emission intensity changes according to the magnitude of the supplied current. In the organic EL display device, gradation expression is performed by changing the light emission intensity of the organic EL element.

  In general, in an active matrix organic EL display device, a plurality of thin film transistors (TFTs) are formed in each pixel. These TFTs function as a drive circuit, a switching element, a correction circuit, or the like. Thereby, the electric current of a desired magnitude | size can be sent through an organic EL element. In the conventional bottom emission method, these TFTs are provided on the viewing side of the organic EL element. For this reason, the ratio of the light emitting area to the display area is reduced due to TFT limitations.

  In the active matrix organic EL display device, as described above, the area of the light emitting pixel is restricted by the TFT. Therefore, various techniques for securing a wide light emitting region without being restricted by TFTs have been developed. One of them is the top emission method.

  FIG. 7 is a schematic cross-sectional view showing a pixel configuration of a conventional organic EL display device using a top emission method. As shown in FIG. 7, in the top emission type organic EL display device, a TFT 13 is formed on a substrate 1 made of a transparent insulating substrate such as glass via a base insulating film 3. The TFT 13 includes a semiconductor layer 4, a gate insulating film 5, a gate electrode 6, an interlayer insulating film 7, and a signal wiring electrode 9. A semiconductor layer 4 made of polysilicon is formed in an island shape on the base insulating film 3. A gate insulating film 5 is formed so as to cover the semiconductor layer 4, and a gate electrode 6 is disposed on the opposite side of the semiconductor layer 4 via the gate insulating film 5.

  An interlayer insulating film 7 is formed so as to cover the gate electrode 6. A contact hole 8 that penetrates the interlayer insulating film 7 and the gate insulating film 5 is provided on the semiconductor layer 4. The signal wiring electrode 9 is electrically connected to the semiconductor layer 4 through the contact hole 8. A passivation film 10 is formed so as to cover the signal wiring electrode 9. An organic planarization film 26 is provided on the passivation film 10. The organic flattening film 26 flattens the unevenness on the passivation film 10 generated by the TFT 13.

  An organic EL element 22 is formed on the TFT 13 via the organic planarizing film 26. The organic EL element 22 includes an anode electrode 19, an organic light emitting layer 20, and a transparent electrode 21. The anode electrode 19 is formed on the organic planarization film 26 so as to be connected to one of the signal wiring electrodes 9 of the TFT 13 through a contact hole that penetrates the organic planarization film 26 and the passivation film 10. On the anode electrode 19, an organic light emitting layer 20 and a transparent electrode 21 are sequentially laminated.

  Further, a sealing substrate 24 is fixed on the organic planarizing film 26 via a sealing material 23. The sealing material 23 is formed so as to surround the pixel. The sealing material 23 fixes the sealing substrate 24 and the substrate 1 and seals the space including the pixels. That is, the organic EL element 22 is disposed in an airtight space formed by the substrate 1, the sealing substrate 24, and the sealing material 23.

  As described above, the top emission method has a structure in which an organic EL element is formed on a TFT provided on a substrate and light emitted from the organic EL element is extracted in a direction opposite to the substrate. That is, since the TFT is provided on the non-viewing side of the organic EL element, a wide light emitting region can be ensured regardless of the arrangement of the TFT.

  On the other hand, Patent Documents 2 and 3 disclose a technique for widening the light emitting region using a method different from the top emission method. Patent Documents 2 and 3 have a bottom emission structure in which a TFT is formed on an organic EL element provided on a substrate and light emitted from the organic EL element is extracted in a direction opposite to the substrate. The TFT is formed on the organic EL element by embedding or bonding using a printing method. In Patent Documents 2 and 3, since the TFT is provided on the non-viewing side of the organic EL element as in the top emission method, it is possible to ensure a wide light emitting region regardless of the arrangement of the TFT.

JP 2005-283661 A JP 2005-266616 A JP 2003-297974 A

  In the top emission method, the surface of the passivation film 10 is uneven due to the TFT 13. The organic EL element 22 is much thinner than the TFT 13. Therefore, when the organic EL element 22 is formed directly on the passivation film 10, a step break or a short circuit occurs due to the uneven step. Therefore, an organic flattening film 26 is formed under the organic EL element 22 in order to flatten the unevenness caused by the TFT 13. The organic planarizing film 26 is formed of an organic insulating material such as an acrylic resin, an epoxy resin, or a polyimide resin.

  However, the organic planarization film 26 tends to retain moisture remaining or adsorbed during the manufacturing process. Therefore, the organic light emitting layer 20 of the organic EL element 22 formed on the upper part absorbs the moisture held in the organic planarizing film 26. The organic light emitting layer 20 deteriorates when it absorbs moisture and stops emitting light. Furthermore, the anode electrode 19 has a patterning shape separated for each pixel, and is formed through photolithography, etching, and cleaning processes. Therefore, the organic planarization film 26 is damaged in the process of forming the anode electrode 19. For example, the organic planarization film 26 may be roughened by dry etching or the like, and the organic EL element 22 formed thereon may be disconnected or short-circuited. Further, the organic planarizing film 26 is swollen by the etching solution or cleaning water and retains moisture.

  As described above, the organic planarization film 26 easily promotes the deterioration of the organic EL element 22. As a result, the display life of the display device is shortened and the reliability is lowered.

  In Patent Documents 2 and 3, a TFT is formed on an organic EL element by embedding or bonding using a printing method. However, overlaying TFTs and organic EL elements requires a high accuracy of several microns, which is a major limitation in the design of display devices. For this reason, when the TFT and the organic EL element are overlapped so as to deviate beyond the error range, the light emitting area decreases.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device with high reliability and a large number of light-emitting pixels and a method for manufacturing the same.

A display device according to the present invention is a display device provided with a plurality of light-emitting pixels, and includes a substrate having an opening at least in a region to be the light-emitting pixels, an insulating film formed on the substrate, and the insulation A thin film transistor formed on a film; a light emitting element formed on a surface of the insulating film opposite to a surface on which the thin film transistor is provided; and a substrate surrounding the light emitting pixel. And the metal film formed between the insulating film and the light emitting pixel, the light emission of the light emitting element is emitted from a viewing side opposite to the side where the thin film transistor is provided. .

The display device manufacturing method according to the present invention is a method for manufacturing a display device provided with a plurality of light emitting pixels, comprising: forming an insulating film on a substrate; and forming a thin film transistor on the insulating film. Forming the thin film transistor, removing the substrate at least in a region to be the light emitting pixel, and forming an opening in the substrate; and providing the thin film transistor of the insulating film in the opening. Forming a light emitting element on a surface opposite to the formed surface, and forming a metal film on the substrate before forming the insulating film, and forming an opening in the substrate in step, the after the substrate by etching the metal film as an etching stopper to form the opening, manufacturing of a display device for removing the metal film in a region comprising at least the light emitting pixel Method.

  According to the present invention, it is possible to provide a display device with high reliability and a large number of light emitting pixels and a method for manufacturing the same.

  The preferred embodiments of the present invention will be described below. The following description explains the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. For the sake of clarification, duplicate explanation is omitted as necessary. In addition, what attached | subjected the same code | symbol in each figure has shown the same element, and description is abbreviate | omitted suitably.

  First, a display device according to the present invention will be described with reference to FIG. FIG. 1 is a front view showing a configuration of a TFT array substrate used in a display device. The display device according to the present invention will be described using an organic EL display device as an example. However, the display device is merely an example, and a light emitting layer other than the organic EL can be used.

  The display device according to the present invention has a substrate 1. The substrate 1 is, for example, an array substrate such as a TFT array substrate. The substrate 1 is provided with a display area 41 and a frame area 42 provided so as to surround the display area 41. In the display area 41, a plurality of scanning signal lines 43 and a plurality of display signal lines 44 are formed. The plurality of scanning signal lines 43 are provided in parallel. Similarly, the plurality of display signal lines 44 are provided in parallel. The scanning signal line 43 and the display signal line 44 are formed so as to cross each other. The scanning signal line 43 and the display signal line 44 are orthogonal to each other. A region surrounded by adjacent scanning signal lines 43 and display signal lines 44 is a pixel 47. Therefore, on the substrate 1, the pixels 47 are arranged in a matrix.

  Further, a scanning signal driving circuit 45 and a display signal driving circuit 46 are provided in the frame region 42 of the substrate 1. The scanning signal line 43 extends from the display area 41 to the frame area 42. The scanning signal line 43 is connected to the scanning signal driving circuit 45 at the end of the substrate 1. Similarly, the display signal line 44 extends from the display area 41 to the frame area 42. The display signal line 44 is connected to the display signal drive circuit 46 at the end of the substrate 1. An external wiring 48 is connected in the vicinity of the scanning signal driving circuit 45. In addition, an external wiring 49 is connected in the vicinity of the display signal driving circuit 46. The external wirings 48 and 49 are wiring boards such as an FPC (Flexible Printed Circuit).

  Various external signals are supplied to the scanning signal driving circuit 45 and the display signal driving circuit 46 via the external wirings 48 and 49. The scanning signal drive circuit 45 supplies a scanning signal to the scanning signal line 43 based on a control signal from the outside. The scanning signal line 43 is sequentially selected by this scanning signal. The display signal drive circuit 46 supplies a display signal to the display signal line 44 based on an external control signal or display data. As a result, a display voltage corresponding to the display data can be supplied to each pixel 47. The scanning signal driving circuit 45 and the display signal driving circuit 46 are not limited to the configuration arranged on the substrate 1. For example, the drive circuit may be connected by TCP (Tape Carrier Package).

  In the case of an organic EL display device, in addition to the scanning signal line 43 and the display signal line 44, a common wiring (not shown) for supplying a common potential and a power supply voltage wiring (not shown) for supplying a power supply voltage are provided. ) Is provided. Similarly to the scanning signal lines 43 and the display signal lines 44, the common wiring and the power supply voltage wiring also extend from the display area 41 to the frame area 42. Accordingly, a common potential and a power supply voltage can be supplied to the pixel 47 from the outside.

  In the pixel 47, at least one TFT 13 is formed. For example, when the TFT 13 is a driving TFT that supplies a driving current to the organic EL element, the organic EL element is connected to the source of the TFT 13. Specifically, an anode electrode (pixel electrode) is connected to the source of the TFT 13. A display signal is supplied to the gate of the TFT 13 via a switching TFT (not shown). Further, a power supply voltage is supplied to the drain of the TFT 13. A transparent electrode is disposed opposite to the anode electrode. An organic EL element is configured by disposing an organic light emitting layer between the anode electrode and the transparent electrode. A common potential is supplied to the transparent electrode. Thus, the anode electrode and the transparent electrode are arranged with the organic light emitting layer interposed therebetween. Accordingly, the TFT 13 serves as a control element that controls the drive current flowing through the organic light emitting layer. Detailed configurations of the TFT 13 and the organic EL element will be described later.

  When the switching TFT is turned on by the scanning signal, the display voltage is supplied to the gate of the driving TFT 13 via the switching TFT. Here, a display voltage based on the display data is supplied via the display signal line 44. Thereby, the driving TFT 13 can supply a driving current corresponding to the display voltage to the organic EL element. Here, the scanning signal sequentially selects the scanning signal lines 43 one by one. Only the switching TFTs of the pixels connected to the selected scanning signal line 43 are turned on. Then, at the timing when the switching TFT is turned on, a display voltage corresponding to the pixel is supplied from the display signal line 44. Thereby, a predetermined drive current corresponding to the display data is supplied for each pixel. As a result, the organic EL element emits light with a luminance corresponding to the display data. A desired image can be displayed in the display area 41 by sequentially scanning the scanning signal lines 43 with the scanning signal.

  Next, the configuration in the pixel 47 of the display device according to the present embodiment will be described in detail with reference to FIG. FIG. 2 is a schematic cross-sectional view illustrating the configuration of the display device according to the present embodiment. FIG. 2 shows one of the pixels 47 on the substrate 1. FIG. 2 shows two TFTs 13, for example, a TFT 13 a and a TFT 13 b. Here, it is assumed that the TFT 13a is a driving TFT and the TFT 13b is a switching TFT. A plurality of such pixels 47 are arranged in a matrix on the substrate 1.

In FIG. 2, a base insulating film 3 is formed on an insulating substrate 1 such as glass. The base insulating film 3 is an inorganic insulating film such as SiO ₂ or SiN. The base insulating film 3 prevents impurities from the substrate 1 from diffusing into each element formed on the substrate 1, and is not limited to the above-described configuration. The base insulating film 3 has a function of insulating a TFT and an organic EL element described later.

  In the present embodiment, an opening 1a from which the substrate 1 is partially removed is formed in the substrate 1. The opening 1a is provided so as to include at least a region to be a light emitting pixel. For example, as shown in FIG. 2, each pixel 47 is provided with one opening 1a. Accordingly, a plurality of openings 1a are formed in a matrix in the display area 41. The thickness of the substrate 1 is, for example, about 0.1 mm. A metal film 2 is formed between the substrate 1 and the base insulating film 3. The metal film 2 is disposed between the adjacent pixels 47. That is, the metal film 2 is formed so as to surround the pixel 47. Accordingly, although not shown here, the display region 41 is provided with the metal film 2 in a lattice pattern. The metal film 2 protrudes inside the opening 1a. Further, in the frame region 42, the metal film 2 is arranged in a frame shape so as to surround the display region 41. The metal film 2 is preferably made of a material having a high specific resistance. Here, the metal film 2 is formed with a film thickness of, for example, 20 to 50 nm using Mo, Cr, or the like.

  Then, the TFT 13 is formed on the base insulating film 3. Specifically, an island-shaped semiconductor layer 4 is provided on the base insulating film 3. The semiconductor layer 4 is formed of polysilicon (polycrystalline silicon). Although not shown in FIG. 2, the semiconductor layer 4 has a source / drain region and a channel region. Impurities are introduced into the source / drain regions. The channel region is disposed between the source region and the drain region. When the TFT 13 is an NMOS, it is preferably an LDD (Lightly Doped Drain) structure in which a low concentration impurity is introduced into a region in contact with the channel region of the source / drain region.

A gate insulating film 5 is provided on the semiconductor layer 4. The gate insulating film 5 is, for example, SiO ₂ with a film thickness of 70 to 100 nm. A gate electrode 6 is formed on the opposite side of the semiconductor layer 4 with the gate insulating film 5 interposed therebetween. The gate electrode 6 is formed of Mo having a film thickness of 300 nm, for example. An interlayer insulating film 7 is provided so as to cover the gate electrode 6. The interlayer insulating film 7 is formed of, for example, a SiO ₂ film having a thickness of about 500 to 1000 nm.

  The signal wiring electrode 9 constituting the circuit is electrically connected to the source / drain region of the semiconductor layer 4 through the contact hole 8. The signal wiring electrode 9 is a source electrode or a drain electrode. The signal wiring electrode 9 is formed of, for example, Mo, Cr, W, Al, Ta, an alloy film containing these as a main component, or a multilayer laminated film in which these are laminated. Here, it is formed by stacking a Mo film having a thickness of 50 to 150 nm, an Al film having a thickness of 200 to 400 nm, and a Mo film having a thickness of 50 to 150 nm. Further, a passivation film 10 is provided so as to cover these signal wiring electrodes 9. The passivation film 10 is made of, for example, SiN.

  On the passivation film 10, a sealing substrate 12 is attached via a sealing material 11. The sealing substrate 12 is a glass substrate, a flexible substrate, a metal substrate, or the like. The sealing substrate 12 is used for maintaining the mechanical strength of the display device. The sealing material 11 fixes the passivation film 10 and the sealing substrate 12 to each other. Thus, the TFT 13 is blocked from the outside by the passivation film 10, the sealing material 11, and the sealing substrate 12.

  In the present embodiment, the organic EL element 22 is formed on the surface of the base insulating film 3 opposite to the surface on which the TFT 13 is provided. Specifically, an anode electrode (pixel electrode) 19 is provided so as to be in contact with the flat surface (the lower surface in FIG. 2) of the base insulating film 3 exposed in the opening 1a. Here, a via hole 15 that penetrates the base insulating film 3, the gate insulating film 5, and the interlayer insulating film 7 and reaches one of the signal wiring electrodes 9 is provided in the opening 1 a. The via hole 15 has a side wall surface tapered. The anode electrode 19 is formed so as to cover the via hole 15. That is, the source electrode of the signal wiring electrode 9 of the driving TFT 13 a and the anode electrode 19 of the organic EL element 22 are connected via the via hole 15. The anode electrode 19 is a pixel electrode, and a predetermined driving current corresponding to display data is supplied through the signal wiring electrode 9.

  The anode electrode 19 is provided apart from the metal film 2. That is, the metal film 2 is formed outside the anode electrode. Then, the anode electrode 19 overlaps the TFT 13 through the base insulating film 3. The anode electrode 19 is made of a conductive material having light reflectivity, preferably a metal having a small work function that facilitates electron injection. Here, the film is formed of Cr with a film thickness of, for example, 100 nm.

  An organic light emitting layer 20 is formed in the opening 1 a so as to be in contact with the anode electrode 19. The organic light emitting layer 20 has a general structure in which a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like are sequentially stacked. Further, the transparent electrode 21 is formed in the opening 1 a so as to contact the organic light emitting layer 20. Therefore, the anode electrode 19 and the transparent electrode 21 are disposed to face each other with the organic light emitting layer 20 interposed therebetween.

  At this time, the transparent electrode 21 is formed so as not to be electrically connected to the anode electrode 19. For example, as shown in FIG. 2, the patterns of the anode electrode 19, the organic light emitting layer 20, and the transparent electrode 21 are arranged at different positions. Thereby, since the organic light emitting layer 20 is always interposed between the anode electrode 19 and the transparent electrode 21, insulation can be maintained.

  Further, at this time, as shown in FIG. 2, the transparent electrode 21 and the metal film 2 are formed so as to partially contact each other. A part of the transparent electrode 21 and a part of the metal film 2 are overlapped. Accordingly, the transparent electrodes 21 of the adjacent pixels 47 are connected via the metal film 2. A common potential is supplied to the transparent electrode 21. Thus, the organic light emitting layer 20 is sandwiched between the anode electrode 19 and the transparent electrode 21, and emits light when a current is supplied. For the transparent electrode 21, a transparent conductive film such as ITO or IZO is generally used. These transparent conductive films have a high specific resistance of about 200 μΩ · cm, which is 10 times or more that of other metal films (specific resistance 4 to 20 μΩ · cm). For this reason, when the display size is increased, the display size may be visually recognized as unevenness. By electrically connecting the metal film 2 and the transparent electrode 21, the resistance of the transparent electrode 21 can be reduced.

  Then, the sealing substrate 24 is fixed to the substrate 1 through the sealing material 23. The sealing material 23 is formed on the surface opposite to the surface on which the TFT 13 of the substrate 1 is provided so as to surround the organic EL element 22. The sealing material 23 fixes the sealing substrate 24 and the substrate 1 and seals the space including the pixels 47. That is, the organic EL element 22 is disposed in an airtight space formed by the base insulating film 3, the substrate 1, the sealing material 23, and the sealing substrate 24. A transparent substrate such as glass is used for the sealing substrate 24, but a color filter substrate may be used as the sealing substrate 24. Although the organic EL element 22 alone can express color, the chromaticity reproducibility can be improved by using a color filter together.

  As described above, in the present embodiment, the organic EL element 22 is formed on the surface of the base insulating film 3 opposite to the surface on which the TFT 13 is provided, and light emitted from the organic EL element 22 is extracted in the direction opposite to that of the TFT 13. It has become. In the light emitting pixel, light emitted from the organic EL element 22 is emitted from the viewing side opposite to the side where the TFT 13 is provided. That is, since the TFT 13 is provided on the non-viewing side of the organic EL element 22, a wide light emitting area can be ensured regardless of the arrangement of the TFT 13.

  Subsequently, a manufacturing method of the display device according to the present embodiment will be described in detail with reference to FIGS. 3-6 is sectional drawing which shows the manufacturing process of the display apparatus based on this Embodiment. 3 to 6 show one pixel 47 on the substrate 1 as in FIG.

First, a metal film 2 is formed on the entire surface of a transparent insulating substrate 1 such as glass. As the metal film 2, it is preferable to use a material having a low electrical specific resistance value. Here, for example, a Mo film or a Cr film having a film thickness of 20 to 50 nm is formed on the entire surface of the substrate 1 by sputtering. Next, the base insulating film 3 is formed on the metal film 2, and the semiconductor layer 4 is further formed thereon. As the base insulating film 3, an inorganic insulating film such as SiO ₂ or SiN can be used. Here, an inorganic insulating film to be the base insulating film 3 and an amorphous silicon thin film to be the semiconductor layer 4 are continuously formed on the entire surface of the substrate 1 by a CVD method or the like. Thereafter, excimer laser or the like is irradiated to convert amorphous silicon into polysilicon. As a result, the configuration shown in FIG.

Next, a desired resist pattern is formed on the semiconductor layer 4 by photolithography. The semiconductor layer 4 is etched through this resist pattern. Here, dry etching is performed using a mixed gas of a fluorinated gas (such as CF ₄ or SF ₆ ) and oxygen (O ₂ ). As a result, the island-shaped semiconductor layers 4 are patterned in the formation region of the TFT 13. Then, after removing the resist pattern, a gate insulating film 5 is formed on the semiconductor layer 4. For example, the SiO ₂ film is formed on the entire surface of the substrate 1 by CVD so as to have a film thickness of 70 to 100 nm. As a result, the semiconductor layer 4 is covered with the gate insulating film 5 as shown in FIG.

  After the formation of the gate insulating film 5, a gate electrode 6 is formed. Specifically, a material to be the gate electrode 6 is formed on the gate insulating film 5. Here, Mo having a film thickness of 300 nm is formed by sputtering on the entire surface of the substrate 1. Then, a desired resist pattern is formed on the gate insulating film 5 by photolithography. The gate electrode 6 is etched through this resist pattern.

  Subsequently, with the resist pattern formed on the gate electrode 6, impurities are introduced into the semiconductor layer 4 using these as a mask. An impurity element such as boron (B) is introduced into the PMOS TFT 13, and an impurity element such as phosphorus (P) is introduced into the NMOS TFT 13. As the introduction method here, either ion implantation for performing mass separation or ion doping without performing mass separation may be used. At this time, by performing patterning of the gate electrode 6 in two steps, the PMOS TFT 13 and the NMOS TFT 13 can be formed on the same substrate 1. After the introduction of impurities, the resist pattern is removed. As a result, source / drain regions are formed in the semiconductor layer 4 in a self-aligned manner, resulting in the configuration shown in FIG.

  Note that a low-concentration impurity may be introduced into a region in contact with the channel region of the source / drain region to form an LDD structure. In particular, the NMOS desirably has an LDD structure in order to improve the performance as transistor performance.

An interlayer insulating film 7 is formed so as to cover the gate electrode 6. For example, a SiO ₂ film having a thickness of 500 to 100 nm is formed on the entire surface of the substrate 1 by a CVD method or the like. Then, through the steps of photoengraving, etching, and resist removal, contact holes 8 for establishing electrical connection with the source / drain regions are formed. Here, dry etching is performed. Thereby, as shown in FIG. 3D, a contact hole 8 is formed on the semiconductor layer 4, and a part of the surface of the semiconductor layer 4 in the source / drain region is exposed. Although not shown, a contact hole for conducting with the gate electrode 6 is also formed at the same time.

After the contact hole 8 is formed, a material to be the signal wiring electrode 9 is formed on the interlayer insulating film 7. As a material for the signal wiring electrode 9, Mo, Cr, W, Al, Ta, an alloy film containing these as a main component, or a laminated film thereof is used. Here, a Mo film with a thickness of 50 to 150 nm, an Al film with a thickness of 200 to 400 nm, and a Mo film with a thickness of 50 to 150 nm are stacked over the entire surface of the substrate 1 by sputtering or the like. A resist pattern is formed thereon by photolithography and etching is performed through this resist pattern. Here, dry etching is performed using a mixed gas of SF ₆ and O ₂ or a mixed gas of Cl ₂ and O ₂ . Thereby, as shown in FIG. 3E, the signal wiring electrode 9 connected to the source / drain region of the semiconductor layer 4 through the contact hole 8 is formed. Although not shown, a signal wiring electrode connected to the gate electrode 6 is also formed at the same time.

  Next, a passivation film 10 is formed on the entire surface of the substrate 1 on the signal wiring electrode 9. For the passivation film 10, SiN or the like can be used. As a result, the signal wiring electrode 9 is covered with the passivation film 10 as shown in FIG. Thereafter, in order to activate the impurities introduced into the semiconductor layer 4, annealing is performed in a nitrogen atmosphere heated to 450 ° C. for 1 hour. After annealing, although not shown here, openings such as terminals are made in the frame region 42.

  After the TFT 13 is formed through such steps, a sealing layer is formed on the passivation film 10. A sealing substrate 12 is bonded onto the passivation film 10 via the sealing material 11. As the sealing substrate 12, for example, a glass substrate is used. Moreover, as the sealing material 11, an epoxy resin can be used, and the function of bonding the substrate 1 and the sealing substrate 12 is achieved. Thereby, as shown in FIG. 4G, the TFT 13 is held in a state of being sandwiched between the sealing substrate 12 and the substrate 1. In this way, after the TFT 13 is formed, the TFT 13 is not exposed to the outside by sealing the TFT 13 with the sealing substrate. Therefore, production in another place and substrate cutting are possible, and productivity can be advantageously led.

  Subsequently, the substrate 1 is processed thinly to a desired thickness. For example, using a polishing agent such as cerium oxide, the surface of the substrate 1 on which the TFT 13 is not provided is completely polished. Here, the substrate 1 is polished to a thickness of about 0.1 mm to reduce the thickness of the substrate 1. It is desirable that the thickness of the substrate 1 after processing is not thinner than the thickness of the organic EL element 22 formed in a later step. As a result, the configuration shown in FIG.

  Thereafter, an opening 1 a is formed in the substrate 1. Chemical etching is performed using a hydrofluoric acid mixture. At this time, the metal film 2 provided between the substrate 1 and the base insulating film 3 serves as an etching stopper. Therefore, the metal film 2 is prevented from being etched up to the base insulating film 3. That is, the substrate 1 is selectively etched. Here, a masking film 14 having resistance to hydrofluoric acid is pasted on the surface of the substrate 1 in advance so as to surround the pixels. In the region covered with the masking film 14, the substrate 1 remains without being removed. As a result, the substrate 1 is removed in a region where the surface of the substrate 1 is exposed without being covered with the masking film 14. Then, as shown in FIG. 4I, the exposed opening 1a of the metal film 2 is formed. The plurality of openings 1a are formed in a matrix.

  After forming the opening 1 a, the masking film 14 is peeled off from the substrate 1. Then, a resist mask is formed on the surface where the metal film 2 in the opening 1a is exposed by photolithography or printing. The metal film 2 is etched through this resist mask. As a result, the metal film 2 is patterned as shown in FIG. 5J, and the metal film 2 in the region to be the light emitting pixel is removed. At this time, the metal film 2 in a region slightly smaller than the opening 1a is removed so that the metal film 2 protrudes inside the opening 1a. In addition, it is preferable to perform patterning so that the metal film 2 remains as much as possible in a portion that becomes a non-light emitting region such as between adjacent pixels. Thus, the flat surface of the base insulating film 3 is exposed.

  Then, a via hole 15 is formed from the surface of the base insulating film 3 exposed in the opening 1a. For example, a resist mask is formed by photolithography or printing. By dry etching through the resist mask, the base insulating film 3, the gate insulating film 5, and the interlayer insulating film 7 are removed, and a via hole 15 is formed. Or you may irradiate a laser beam and open the via hole 15 directly. At this time, the side wall surface of the via hole 15 is formed so as to have a taper angle such that the anode electrode 19 is not cut off in the step of forming the anode electrode 19 described later. That is, the opening of the via hole 15 is widened. Thereby, as shown in FIG. 5K, the via hole 15 is formed, and the surface of the signal wiring electrode 9 is exposed.

  Next, a portion to be the organic EL element 22 is formed. The subsequent steps are performed in a vacuum. First, the substrate 1 is cleaned to remove dust and the like attached to the surface. After cleaning, moisture adsorbed on the surface of the substrate 1 is removed. As methods for removing moisture, there are spin drying, oven drying, and the like, but heating in a vacuum is particularly effective. For removing water, a heating temperature of 180 ° C. or higher is preferable. However, if the temperature is too high, the sealing material 11 and the TFT 13 may be deteriorated, and therefore heating is performed at a temperature of about 200 ° C. here.

  After sufficiently removing the water, the anode electrode 19 is formed in a vacuum. A material to be the anode electrode 19 is formed on the surface of the base insulating film 3 in the opening 1a by sputtering or the like. In order to form the anode electrode 19 in each pixel 47, the film is formed through the vapor deposition mask 16 in which a desired region is opened. At this time, the anode electrode 19 is formed so as not to contact the metal film 2. Here, for example, Cr is deposited with a film thickness of 100 nm. The thickness of the substrate 1 is processed so as to be thinner than the thickness of the organic EL element 22. That is, the thickness of the organic EL element 22 is smaller than the thickness of the substrate 1 outside the opening 1a. Therefore, the vapor deposition mask 16 can be installed in contact with the substrate 1 at the outer portion of the opening 1 a and can be held on the substrate 1. As a result, as shown in FIG. 5L, the anode electrode 19 connected to the signal wiring electrode 9 through the via hole 15 is formed.

  Then, the organic light emitting layer 20 is formed from the surface of the anode electrode 19. The organic light emitting layer 20 can be formed by a mask vapor deposition method, an ink jet method, a printing method, or the like. Here, the organic light emitting layer 20 is formed by a mask vapor deposition method. A hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and the like are sequentially stacked using the vapor deposition mask 17 in which a desired region is opened to form the organic light-emitting layer 20. Similar to the vapor deposition mask 16 when forming the anode electrode 19, the vapor deposition mask 17 can be held on the substrate 1. The mask opening of the vapor deposition mask 17 is disposed at a position slightly shifted from the position of the mask opening of the vapor deposition mask 16. Accordingly, the pattern end portion of the organic light emitting layer 20 is formed to be shifted from the pattern end portion of the anode electrode 19. Thereby, as shown in FIG. 6M, the organic light emitting layer 20 is formed in the opening 1a.

  Further, the transparent electrode 21 is formed from the surface of the organic light emitting layer 20. Using the vapor deposition mask 18, a material to be the transparent electrode 21 is formed by sputtering or the like. For example, ITO or IZO is used as a material for the transparent electrode 21. The vapor deposition mask 18 can be held on the substrate 1 like the vapor deposition masks 16 and 17. The mask opening of the vapor deposition mask 18 is disposed at a position slightly deviated from the positions of the mask openings of the vapor deposition masks 16 and 17. That is, the pattern end portion of the transparent electrode 21 is formed to be shifted from the pattern end portion of the organic light emitting layer 20 in the same direction as the displacement direction of the organic light emitting layer 20 from the anode electrode 19. At this time, it is desirable to form the transparent electrode 21 so that the metal film 2 and the part are in contact with each other. As a result, the transparent electrode 21 is formed in the opening 1 a as shown in FIG. 6 (n), and the organic light emitting layer 20 is sandwiched between the anode electrode 19 and the transparent electrode 21.

  Thus, by forming the opening 1 a in the substrate 1, the organic EL element 22 is formed on the exposed flat surface of the base insulating film 3, so that no disconnection or short circuit occurs. That is, it is not necessary to provide an organic planarizing film under the organic EL element 22. Therefore, problems caused by the organic flattening film, such as the organic light emitting layer 20 being deteriorated by adsorbing moisture held in the organic flattening film, can be avoided. Moreover, a normal production process can be used for forming the organic EL element 22. Since there is no need to use a special production method, there is no concern that the yield will be reduced.

  After the organic EL element 22 is formed in the opening 1a, a sealing layer for sealing the opening 1a is formed. The sealing substrate 24 is bonded to the substrate 1 through the sealing material 23. As the sealing substrate 24, a transparent substrate such as glass is used. A sealing material 23 is formed on the surface of the substrate 1 opposite to the TFT 13 so as to surround the organic EL element 22. The sealing material 23 fixes the sealing substrate 24 and the substrate 1 and seals the space including the pixels 47. As a result, as shown in FIG. 6 (o), the organic EL element 22 is sealed in an airtight space formed by the base insulating film 3, the substrate 1, the sealing material 23, and the sealing substrate 24. After sealing the organic EL element 22, it may be released into the atmosphere. Through the above steps, the display device according to this embodiment is completed.

  Thus, in this embodiment, after forming the TFT 13, the opening 1 a is formed from the back surface of the substrate 1 to expose the base insulating film 3. Thereafter, the organic EL element 22 is formed in the opening 1a, that is, on the surface opposite to the surface on which the TFT 13 of the base insulating film 3 is provided. Then, the light emitted from the organic EL element 22 is extracted in the direction opposite to that of the TFT 13. Thereby, since the TFT 13 can be provided on the non-viewing side of the organic EL element 22, a wide light emitting region can be ensured regardless of the arrangement of the TFT 13. Further, since the organic EL element 22 is formed on the flat surface of the base insulating film 3 exposed by forming the opening 1a in the substrate 1, flattening with an organic flattening film is unnecessary. Thereby, the problem which arises with an organic planarization film | membrane can be avoided. For example, deterioration of the organic light emitting layer 20 due to water absorption from the organic planarizing film can be prevented. Therefore, the reliability of the display device can be improved. Therefore, it is possible to provide a display device with high reliability and a large light emitting pixel and a manufacturing method thereof.

  In the present embodiment, the metal film 2 is provided between the substrate 1 and the base insulating film 3. Thereby, when opening 1a by chemical etching etc., the metal film 2 can be used as an etching stopper. Thereafter, the metal film 2 is patterned to remove a region to be a light emitting pixel and to be connected to a part of the transparent electrode 21. Thereby, the specific resistance value of the transparent electrode 21 can be reduced, and display unevenness can be suppressed. Accordingly, the display performance is improved.

  In the above description, the TFT 13a is a driving TFT and the TFT 13b is a switching TFT. However, the TFT 13a may be a switching TFT and the TFT 13b may be a TFT different from the switching TFT. In this case, the TFT 13 a functions as a switching element for the organic EL element 22.

  Although the case where the sealing substrate is used as the sealing layer for sealing the TFT 13 or the organic EL element 22 is described as an example, the present invention is not limited to this. An inorganic insulating film, an organic insulating film, a transparent substrate, a metal plate, or the like may be formed as the sealing layer. Moreover, although the sealing layer by the sealing material 11 and the sealing substrate 12 was formed on the passivation film 10 and the TFT 13 was sealed, the sealing layer may not be formed. Even if there is no sealing layer, the display performance is not impaired. Therefore, when there is no need for sealing, the display device may be formed without providing a sealing layer.

  In the present embodiment, the case where the opening 1a is formed for each pixel has been described as an example, but the present invention is not limited to this. It suffices if an opening is formed at least in a region to be the pixel 47. For example, a large opening including the entire display area 41 may be provided. In that case, the sealing material 23 is formed so as to surround the pixel 47, and the sealing substrate 24 and the base insulating film 3 or the metal film 2 are fixed. Alternatively, sealing is performed using the sealing substrate 24 in which a part of the sealing substrate 24 is dug in advance and a recess is formed. Further, the sealing material 11 may be directly formed on the entire organic EL element 22 and the sealing substrate 24 may be directly bonded. In this case, an airtight space is not formed around the organic EL element 22, and the organic EL element 22 is covered with the sealing material 11 and sealed.

  The display device according to the present invention has been described using an organic EL display device as an example, but may be a display device using a light emitting layer other than an organic EL, such as an inorganic EL display device. Further, the present invention can be applied to a display device such as electronic paper using colloidal particles or ultrafine particles as a display material.

  The above description describes the embodiment of the present invention, and the present invention is not limited to the above embodiment. Moreover, those skilled in the art can easily change, add, and convert each element of the above embodiment within the scope of the present invention.

It is a front view which shows the structure of the TFT array substrate used for the display apparatus which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the structure of the display apparatus which concerns on this Embodiment. It is sectional drawing which shows the manufacturing process of the display apparatus which concerns on this Embodiment. It is sectional drawing which shows the manufacturing process of the display apparatus which concerns on this Embodiment. It is sectional drawing which shows the manufacturing process of the display apparatus which concerns on this Embodiment. It is sectional drawing which shows the manufacturing process of the display apparatus which concerns on this Embodiment. It is a cross-sectional schematic diagram which shows the pixel structure of the conventional organic electroluminescent display apparatus using a top emission system.

Explanation of symbols

1 substrate, 1a opening, 2 metal film, 3 base insulating film, 4 semiconductor layer,
5 gate insulating film, 6 gate electrode, 7 interlayer insulating film, 8 contact hole,
9 signal wiring electrode, 10 passivation film, 11 sealing material,
12 sealing substrate, 13, 13a, 13b TFT, 14 masking film,
15 via hole, 16, 17, 18 evaporation mask, 19 anode electrode,
20 organic light emitting layer, 21 transparent electrode, 22 organic EL element, 23 sealing material,
24 sealing substrate, 26 organic planarization film, 41 display area, 42 frame area,
43 gate wiring, 44 source wiring, 45 scanning signal driving circuit,
46 Display signal drive circuit, 47 pixels, 48, 49 External circuit

Claims (10)

A display device provided with a plurality of light emitting pixels,
A substrate having an opening in at least a region to be the light emitting pixel;
An insulating film formed on the substrate;
A thin film transistor formed on the insulating film;
In the opening, a light emitting element formed on the surface of the insulating film opposite to the surface on which the thin film transistor is provided;
A metal film provided so as to surround the light emitting pixel, and formed between the substrate and the insulating film ;
In the light emitting pixel, the light emitting element emits light emitted from a viewing side opposite to a side where the thin film transistor is provided. The light emitting element is
A pixel electrode connected to the thin film transistor through a via hole penetrating the insulating film and reaching the signal wiring electrode of the thin film transistor;
A transparent electrode provided on the viewing side of the pixel electrode;
The display device according to claim 1, further comprising: a light emitting layer disposed between the pixel electrode and the transparent electrode. The display device according to claim 2 , wherein the metal film is connected to a part of the transparent electrode. Provided on the viewing side of the substrate, a display device according to any one of claims 1 to 3 further comprising a first sealing layer which prevents the ingress of moisture into the light-emitting element. Provided on the opposite viewing side of the substrate, a display device according to any one of claims 1 to 4 further comprising a second sealing layer for blocking the thin film transistor from the outside. A method of manufacturing a display device provided with a plurality of light emitting pixels,
A step of forming a metal film on a board,
Forming an insulating film on the metal film;
Forming a thin film transistor on the insulating film;
After forming the thin film transistor, removing at least the substrate in a region to be the light emitting pixel, and forming an opening in the substrate;
Forming a light emitting element on the surface of the insulating film opposite to the surface on which the thin film transistor is provided in the opening;
With
In the step of forming an opening in the substrate, the display device is manufactured by removing the metal film at least in a region to be the light emitting pixel after forming the opening by etching the substrate using the metal film as an etching stopper. Method. In the step of forming the light emitting element,
Forming a pixel electrode connected to the thin film transistor on the surface of the insulating film in the opening through a via hole penetrating the insulating film and reaching the signal wiring electrode of the thin film transistor;
Forming a light emitting layer on the surface of the pixel electrode;
Forming a transparent electrode on a surface of the light emitting layer. The method for forming a display device according to claim 6 . The method for manufacturing a display device according to claim 7 , wherein in the step of forming the transparent electrode, the transparent electrode is formed so as to be connected to a part of the metal film. The method for manufacturing a display device according to claim 6 , further comprising a step of forming a first sealing layer that seals the opening after the light emitting element is formed. 10. The display device manufacturing method according to claim 6 , further comprising: forming a second sealing layer that shields the thin film transistor from the outside on the thin film transistor before forming the opening. 11. Method.

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