JP5223666B2 - Circuit board manufacturing method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a circuit board manufacturing method and a semiconductor device manufacturing method.

  A circuit board of a computer system in recent years is required to be able to cope with high speed and large scale. Therefore, flip-chip bonding using gold bumps is provided as a method for connecting semiconductor elements or a method for connecting a semiconductor element and a circuit board.

  In such flip chip mounting, solder is formed on a substrate electrode provided on a mounting surface of a circuit board, and then electrically connected by joining a terminal of a semiconductor element and solder on the substrate electrode. A joining method is used.

  Here, a conventional gold-solder joining process will be described with reference to FIG. FIG. 12 is an explanatory view of a conventional gold-solder joining process. As shown in FIG. 12A, a solder 63 containing tin is formed on a substrate electrode 62 provided on a circuit board 61, and a semiconductor element 71 is formed. Alignment with the formed gold terminal 72 is performed.

  Next, as shown in FIG. 12B, for example, a bonding heating head 64 heated to 280 ° C. to 320 ° C. is pressed against the semiconductor element 71, and heat is supplied from the gold terminal 72 so that the solder contains tin. Electrical conduction is obtained by melting 63.

Next, as shown in FIG. 12C, the basic configuration of the semiconductor mounting apparatus is completed by injecting the underfill resin 66 between the semiconductor element 71 and the circuit board 61 using the syringe 65.

  Since this method can be mounted with a low load at the time of bonding, it is possible to prevent a reduction in mounting accuracy when the semiconductor element 71 is mounted on the circuit board 61 and to refine the terminals due to the higher density of the semiconductor element 71. It is considered to be a technology that can cope with this.

Currently, as a technique for forming a solder containing tin on a substrate circuit, there is an electroplating method, an electroless plating method, or a super just method by forming an adhesive material on a substrate electrode and adhering solder powder. is there.
JP 2005-057245 A

  However, in the case of the electrolytic plating method, the plating thickness varies widely, and when the semiconductor element is joined, if the amount of tin or solder is large, a short circuit occurs between the terminals, while if the amount is small, the joining is performed. There is a problem that an open defect occurs in which the part breaks. Moreover, since it is essential to form a plated wire, the plated wire hinders miniaturization of the semiconductor package.

  Moreover, in the super just method, since solder powder is used as a raw material, there is a problem that the manufacturing cost is high in order to manufacture a fine powder when the terminals of the semiconductor element have a fine pitch. In addition, since the surface area of the powder is increased, there is a problem that it is difficult to obtain a stable shape due to the effect of surface oxidation.

  Furthermore, in the case of the electroless plating method, the amount of tin or solder can be manufactured with little variation, but only the substitutional plating method in which the copper constituting the wiring of the circuit board is formed by metal replacement can satisfy mass productivity. However, the film thickness is up to about 2 μm, and there is a problem that a sufficient thickness that can secure the strength of the terminal after mounting the semiconductor element cannot be secured.

  Therefore, an object of the present invention is to thicken a solder containing tin formed on a substrate wiring used for a gold-solder joining method while suppressing variations in film thickness.

From one aspect of the present invention, a step of providing a metal film that can be replaced with solder containing tin by metal substitution between a plurality of connection portion conductor patterns provided on a mounting surface of a circuit board; Substituting solder containing tin by substitution, melting the solder containing substituted tin, dividing between the connection part conductor patterns, and thickening the solder containing tin on the surface of the connection part conductor pattern A circuit board manufacturing method is provided.

According to another aspect of the present invention, a step of providing a metal film that can be replaced with solder containing tin by metal replacement between a plurality of connection portion conductor patterns provided on a mounting surface of a circuit board; A step of replacing the film with a solder containing tin by metal substitution, and melting the solder containing the substituted tin, dividing the connection part conductor pattern, and thickening the solder containing tin on the surface of the connection part conductor pattern There is provided a method of manufacturing a semiconductor device, including a step of attaching, and a step of electrically connecting the connection conductor pattern thickened with the solder containing tin and the connection terminal provided on the semiconductor element by flip chip bonding. .

  According to the disclosed circuit board manufacturing method and semiconductor device manufacturing method, it is possible to thicken the solder containing tin formed on the substrate wiring while suppressing variation in film thickness, thereby reducing the size of the semiconductor package. And reliable mounting using the terminals of the fine pitch semiconductor element.

  Here, with reference to FIG. 1 thru | or FIG. 5, the manufacturing method of the circuit board of embodiment of this invention is demonstrated. FIG. 1 is an explanatory diagram of a manufacturing process of a circuit board according to an embodiment of the present invention. First, as shown in FIG. 1A, a peripheral made of copper on a circuit board 1 with a plating seed layer 2 interposed therebetween. A substrate electrode 3 is provided.

  Next, as shown in FIG. 1B, a replacement metal film 4 having a thickness of 0.5 μm to 2.5 μm is provided in the region where the peripheral substrate electrode 3 is provided using an electroless plating method or a sputtering method. . In this case, the metal film 4 is made of a metal that can be replaced with a solder containing tin by metal substitution, and is made of, for example, Cu, Al, Cr, or an alloy thereof.

  Next, as shown in FIG. 1C, the replacement metal film 4 is replaced with solder 5 containing tin using a substitutional electroless plating bath containing Sn. Examples of the solder containing tin include Sn, Sn-Ag, Sn-Bi, Sn-Cu, Sn-Zn, Sn-Ag-Cu, and the like. The maximum is desirable, and the composition of the substitutional electroless plating bath containing Sn is changed according to the composition. Note that by adding Ag, Bi, or the like, the melting point of the solder becomes lower than the melting point of Sn.

Next, as shown in FIG. 1D, the solder 5 containing tin is melted by heat treatment.
At this time, since the contact angle of the molten solder on the surface of the peripheral substrate electrode 3 and the surface of the circuit substrate 1 is different, the molten solder gathers on the surface of the peripheral substrate electrode 3 due to surface tension to form the solder layer 6. Since this solder layer 6 is also a collection of solder 5 containing tin between the peripheral substrate electrodes 3, the thickness of the replacement metal film formed in the initial stage depends on the distance between the peripheral substrate electrodes 3. More than twice as thick.

  In this case, the solder layer 6 is etched so that the replacement metal remains only in the connection pad portion before the metal replacement step, or the solder containing tin is applied only to the connection pad portion after the metal replacement step. Etching is performed so that it remains.

  FIG. 2 is an explanatory diagram of the circuit board thus formed and a mounting structure using the circuit board. FIG. 2A is a conceptual plan view of the circuit board, in which the peripheral substrate electrode 3 is formed in alignment on the mounting surface of the circuit board 1, and tin or tin is the main component only on the surface of the connection pad as described above. A solder layer 6 made of the solder is formed. The other areas are covered with the solder resist 7.

  FIG. 2B is a conceptual cross-sectional view of a mounting structure using a circuit board. In the process as described in the conventional example, the gold bumps 9 provided on the semiconductor element 8 are brought into contact with the connection pads and heated. To form a gold-solder joint. Next, the mounting semiconductor device is completed by filling the underfill resin 10.

  In this embodiment of the present invention, since the replacement metal film is formed by the electroless plating method or the sputtering method with little variation, the variation in the thickness of the solder layer covering the connection pad is small, and the semiconductor It can be formed to a thickness that provides the terminal strength of the element. Thereby, the connection reliability of the semiconductor device corresponding to the fine pitch can be improved.

  The replacement metal film may be a plating seed layer in a semi-additive method that is widely known as a method for manufacturing a circuit board, which will be described with reference to FIGS. First, as shown in FIG. 3A, a Cu plating seed layer 12 having a thickness of, for example, 0.5 μm to 2 μm is provided on the surface of the substrate base layer 11, and a resist pattern 13 serving as a plating frame is provided.

Next, as shown in FIG. 3B, a Cu plating layer 14 is formed by electrolytic plating.
Next, the resist pattern 13 is removed as shown in FIG. Next, as shown in FIG. 4D, in the conventional semi-additive method, the exposed portion of the Cu plating seed layer 12 is removed with a sulfuric acid-based Cu etching solution and the remaining portion is used as a wiring pattern. However, in the embodiment of the present invention, the Cu plating seed layer around the Cu plating layer 14 to be the peripheral substrate electrode is left.

  Next, as shown in FIG. 4 (e), by performing electroless plating using an Sn substitutional electroless plating bath with only the peripheral portion of the Cu plating layer 14 serving as a peripheral substrate electrode exposed, Cu plating is performed. The plating seed layer 12 is replaced with the tin solder layer 15 and the surface of the Cu plating layer 14 is also replaced with the tin solder layer 15.

  Next, as shown in FIG. 4 (f), by melting the tin solder layer 15 by heating, a thick tin solder layer 16 is formed on the surface of the Cu plating layer 14 by the surface tension of the molten tin, Adjacent Cu plating layers 14 are electrically separated from each other. In this case, the process of forming the replacement metal film can be omitted, and therefore the process can be simplified.

  Further, since the metal substitution electroless plating process may be a two-stage process, the state will be described with reference to FIG. First, as shown in FIG. 5A, a peripheral substrate electrode 23 made of copper is provided on a circuit substrate 21 via a plating seed layer 22. Next, as shown in FIG. 5B, a replacement metal film 24 having a thickness of, for example, 2 μm is provided in the region where the peripheral substrate electrode 23 is provided using an electroless plating method.

  Next, as shown in FIG. 5 (c), for example, using a Sn substitution type electroless plating bath at 60 ° C., the surface of the replacement metal film 24 is 0.1 μm to 1.5 μm, for example, about 0.5 μm. The tin solder layer 25 is replaced.

  Next, as shown in FIG. 5D, the remaining portion of the replacement metal film 24 is replaced with a tin solder layer 26 using a Sn substitution type electroless plating bath at a higher temperature, for example, 70 ° C. The components of the first stage Sn-substitution type electroless plating bath and the second stage Sn-substitution type electroless plating bath are higher in the plating speed of the Sn-substitution type electroless plating in the second stage plating bath. Adjust so that

  In this case, since the first-stage Sn-substitution type electroless plating bath is slowly formed at a low temperature, a dense tin solder layer 25 can be formed. On the other hand, film quality is not good in the Sn substitution type electroless plating bath which forms the tin solder layer quickly at a high temperature as compared with the first stage. However, in the present embodiment, the dense tin solder layer 25 is formed in the first stage. Therefore, in the second stage, the formation speed of the tin solder layer is increased under the influence of the dense tin solder layer 25. Even the film quality can be maintained.

  Next, as shown in FIG. 5 (e), the tin solder layers 25 and 26 are melted by heat treatment, and a tin solder having a thickness of at least twice the thickness of the replacement metal film 24 on the surface of the peripheral substrate electrode 23. Cover with layer 27. As described above, by performing the two-stage metal replacement, the tin solder layers 25 and 26 do not pick up the film quality of the surface of the replacement metal film 24, and the high-quality tin solder layer 27 can be obtained.

  Based on the above, next, the manufacturing process of the circuit board according to the first embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 6A, 400 peripheral substrate electrodes 32 having a width of, for example, 25 μm are formed on the circuit substrate 31 at intervals of 25 μm, and a solder resist 33 is formed on the circuit substrate 31 in the semiconductor element mounting area. Form. The circuit board 31 is, for example, a BT resin board having a thickness of 0.35 mm, and can be mounted with, for example, an 8.5 mm square semiconductor element. Further, the figure shows a part near the connection pad as a perspective view.

  Next, as shown in FIG. 6B, a plating resist 34 is formed so as to match the solder resist 33, and the connection pad portion is opened. Next, as shown in FIG. 6C, an electroless Cu plating layer 35 having a thickness of, for example, 2 μm is formed by electroless copper plating. Next, as shown in FIG. 7D, the electroless Cu plating layer 35 deposited on the plating resist 34 is removed at the same time by peeling the plating resist 34.

  Next, as shown in FIG. 7E, for example, electroless plating treatment is performed at 60 ° C. for 30 minutes using a substitutional electroless tin plating bath 580MJ (Ishihara Pharmaceutical product model number). By this substitutional electroless tin plating process, the electroless Cu plating layer 35 is replaced with almost pure Sn to become a Sn solder layer 36.

  Next, as shown in FIG. 7 (f), a flux is applied to the plating processing section, and a reflow process is performed using a reflow furnace set so that the surface temperature of the circuit board 31 is 260 ° C. at the maximum, Perform flux cleaning. In this reflow processing step, the Sn solder layer 36 is melted, and a thick Sn solder layer 37 covers the surface of the connection pad by the surface tension of the melted Sn.

  As a result of measuring the height of the Sn solder layer 37 using a fluorescent X-ray apparatus, the maximum thickness of the Sn solder layer 37 is 4.7 μm on average, and when plating is performed by a conventional method, Since the maximum thickness was 2.1 μm, it was confirmed that the thickness could be twice or more.

  Thereafter, as shown in FIG. 2 described above, an 8.5 mm square semiconductor element having gold terminals using wire-bonded gold balls on 400 terminals is mounted on the circuit board 31. The gold terminal formation conditions at this time were a ball bonder stage temperature of 200 ° C.

  After aligning the semiconductor element with the circuit board 31 using a flip chip bonder, bonding was performed by applying a load of 3 g / terminal at a temperature of 300 ° C./3 seconds from the semiconductor element side. Thereafter, an underfill material was injected and cured in a thermostatic bath at 150 ° C. for 2 hours.

  The joint portion of the semiconductor device completed after mounting was observed by cross-sectional polishing. At this time, in the conventional method, Sn solder was present only at the tip of the gold terminal, and cracks that were thought to be caused by bonding stress occurred at the bottom of the gold terminal. However, in Example 1 of the present invention, Sn solder was present. It existed in a form that sufficiently covered the outer periphery of the gold terminal, and no cracks were observed at the joint.

  Next, the manufacturing process of the circuit board according to the second embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 8A, 400 Cu plating layers 43 serving as peripheral substrate electrodes having a width of, for example, 25 μm are formed on the circuit substrate 41 via a Cu plating seed layer 42 by a semi-additive method at intervals of 25 μm. After the formation, the resist pattern (not shown) is removed.

  Next, as shown in FIG. 8B, an etching resist 44 is provided so as to cover the connection pad portion. Next, as shown in FIG. 8C, the exposed portion of the Cu plating seed layer 42 is removed by etching using the etching resist 44 as a mask, and then the etching resist 44 is removed.

  Next, as shown in FIG. 9D, a solder resist 45 is formed so as to expose the connection pad portion. Next, as shown in FIG. 9E, for example, an electroless plating treatment is performed at 60 ° C. for 30 minutes using a substitutional electroless tin plating bath 580MJ (product model number manufactured by Ishihara Pharmaceutical). By this substitutional electroless tin plating process, the Cu plating seed layer 42 and the Cu plating layer 43 are replaced with almost pure Sn to become the Sn solder layer 46.

  Next, as shown in FIG. 9 (f), flux is applied to the plating portion, and reflow treatment is performed using a reflow furnace set so that the surface temperature of the circuit board 41 is 260 ° C. at the maximum. Wash. In this reflow process, the Sn solder layer 46 is melted, and the thick Sn solder layer 47 covers the surface of the connection pad by the surface tension of the melted Sn.

  As a result of measuring the height of the Sn solder layer 47 using a fluorescent X-ray apparatus, the maximum thickness of the Sn solder layer 47 is an average of 4.6 μm, and when the plating process is performed by the conventional method, Since the maximum thickness was 2.1 μm, it was confirmed that the thickness could be twice or more.

  Thereafter, the semiconductor device was completed by mounting the semiconductor element on the circuit board 41 in the same manner as in the first embodiment. The joint portion of the semiconductor device completed after mounting was observed by cross-sectional polishing. Similar to Example 1, Sn solder was present in a form that sufficiently covered the outer periphery of the gold terminal, and no cracks were observed at the joint.

  Next, the manufacturing process of the circuit board according to the third embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 10A, 400 Cu plating layers 43 serving as peripheral substrate electrodes having a width of, for example, 25 μm are formed on the circuit substrate 41 via a Cu plating seed layer 42 by a semi-additive method at intervals of 25 μm. After the formation, the resist pattern (not shown) is removed.

  Next, as shown in FIG. 10B, for example, electroless plating treatment is performed at 60 ° C. for 30 minutes using a substitutional electroless tin plating bath 580MJ (product model number manufactured by Ishihara Pharmaceutical). By this substitutional electroless tin plating process, the Cu plating seed layer 42 and the Cu plating layer 43 are replaced with almost pure Sn to become the Sn solder layer 48.

  Next, as shown in FIG. 10C, an etching resist 49 is provided so as to cover the connection pad portion. Next, as shown in FIG. 11D, the exposed portion of the Sn solder layer 48 is removed by etching using the etching resist 49 as a mask, and then the etching resist 49 is removed.

  Next, as shown in FIG. 11E, a solder resist 50 is formed so as to expose the connection pad portion. Next, as shown in FIG. 11 (f), flux is applied to the plating portion, and reflow treatment is performed using a reflow furnace set so that the surface temperature of the circuit board 41 is 260 ° C. at the maximum. Wash. In this reflow process, the Sn solder layer 48 is melted, and the thick Sn solder layer 51 covers the surface of the connection pad by the surface tension of the melted Sn.

  As a result of measuring the height of the Sn solder layer 51 using a fluorescent X-ray apparatus, the maximum thickness of the Sn solder layer 51 is 4.8 μm on average, and when plating is performed by a conventional method, Since the maximum thickness was 2.1 μm, it was confirmed that the thickness could be twice or more.

  Thereafter, the semiconductor device was completed by mounting the semiconductor element on the circuit board 41 in the same manner as in the first embodiment. The joint portion of the semiconductor device completed after mounting was observed by cross-sectional polishing. Similarly to Example 1, in Example 3, Sn solder was present in a form that sufficiently covered the outer periphery of the gold terminal, and no crack was observed at the joint.

It is explanatory drawing of the manufacturing process of the circuit board of embodiment of this invention. It is explanatory drawing of the mounting structure using a circuit board and a circuit board. It is process explanatory drawing to the middle at the time of applying to a semi-additive construction method. It is process explanatory drawing after FIG. 3 at the time of applying to a semi-additive construction method. It is process explanatory drawing of a two-stage metal substitution process. It is explanatory drawing to the middle of the manufacturing process of the circuit board of Example 1 of this invention. It is explanatory drawing after FIG. 6 of the manufacturing process of the circuit board of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of the circuit board of Example 2 of this invention. It is explanatory drawing after FIG. 8 of the manufacturing process of the circuit board of Example 2 of this invention. It is explanatory drawing to the middle of the manufacturing process of the circuit board of Example 3 of this invention. It is explanatory drawing after FIG. 10 of the manufacturing process of the circuit board of Example 3 of this invention. It is explanatory drawing of the conventional gold-solder joining process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit board 2 Plating seed layer 3 Peripheral board electrode 4 Substitution metal film 5 Solder containing tin 6 Solder layer 7 Solder resist 8 Semiconductor element 9 Gold bump 10 Underfill resin 11 Substrate base layer 12 Cu plating seed layer 13 Resist pattern 14 Cu plating layer 15 Tin solder layer 16 Tin solder layer 21 Circuit board 22 Plating seed layer 23 Peripheral board electrode 24 Replacement metal film 25, 26, 27 Tin solder layer 31 Circuit board 32 Peripheral board electrode 33 Solder resist 34 Plating resist 35 None Electrolytic Cu plating layer 36 Sn solder layer 37 Sn solder layer 41 Circuit board 42 Cu plating seed layer 43 Cu plating layer 44, 49 Etching resist 45, 50 Solder resist 46, 48 Sn solder layer 47, 51 Sn solder layer 61 Circuit board 62 Base Plate electrode 63 Solder containing tin 64 Bonding heating head 65 Syringe 66 Underfill resin 71 Semiconductor element 72 Gold terminal

Claims (6)

A step of providing a metal film that can be replaced with solder containing tin by metal replacement between the plurality of connection portion conductor patterns provided on the mounting surface of the circuit board;
Replacing the metal film with solder containing tin by metal substitution;
A method of manufacturing a circuit board, comprising: melting the substituted tin-containing solder and dividing the solder between the connection portion conductor patterns to thicken the solder containing tin on the surface of the connection portion conductor pattern. The method for manufacturing a circuit board according to claim 1, wherein a substitutional electroless plating bath containing tin is used in the step of replacing with solder. The step of replacing the metal film with a solder containing tin by metal replacement includes a first metal replacement step of replacing a part of the surface of the metal film with metal, and a temperature of the metal film at a higher temperature than the first metal replacement step. The method for manufacturing a circuit board according to claim 1, further comprising a second metal replacement step of replacing the remainder with a metal. The method for manufacturing a circuit board according to claim 1, wherein a plating seed layer used in a process of forming a wiring pattern of the circuit board is used as the metal film. The step of providing a metal film that can be replaced with solder containing tin by metal replacement between the connection part conductor patterns provides the metal film with the surface of the connection part conductor pattern other than the connection pad part covered with a plating resist. The method for manufacturing a circuit board according to claim 1, wherein the method is a process. A step of providing a metal film that can be replaced with solder containing tin by metal replacement between the plurality of connection portion conductor patterns provided on the mounting surface of the circuit board;
Replacing the metal film with solder containing tin by metal substitution;
Melting the substituted tin-containing solder, dividing between the connection portion conductor patterns and thickening the solder containing tin on the connection portion conductor pattern surface; and
A method of manufacturing a semiconductor device, comprising: electrically connecting a connection portion conductor pattern thickened with solder containing tin and a connection terminal provided on a semiconductor element by flip chip bonding.

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