JP5212246B2 - Solid-state imaging device and manufacturing method of solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the solid-state imaging device. More specifically, the present invention relates to a solid-state imaging device and a method for manufacturing the same, in which diffusion of a remaining metal element is suppressed by performing a planarization process, and deterioration in sensitivity and image quality is suppressed.

  In recent years, with the demand for miniaturization, weight reduction, and low power consumption of products using solid-state image sensors, a processing circuit provided in the signal processing element is also formed around the light receiving portion of the solid-state image sensor. It has been practiced that all processing is possible with a solid-state imaging device and no signal processing device is required.

  As such a solid-state imaging device, a CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device is known to be advantageous in reducing the size, weight, cost, and power consumption. A single solid-state imaging device is formed by providing a peripheral circuit including a required circuit around the light-receiving portion in which the photoelectric conversion element having the above is formed.

  In addition, along with the progress of miniaturization technology of MOS process, it is possible to easily realize miniaturization of photoelectric conversion elements and increase in the number of pixels, as well as high integration of peripheral circuits. The number of pixels and the number of functions are increasing.

  For example, as one of the recent miniaturization techniques, it has been proposed to use copper wiring instead of conventional aluminum wiring for element wiring. That is, copper has a resistance value lower than that of aluminum and can reduce the wiring pitch and can be formed with a thinner wiring thickness. Therefore, it has been proposed to use copper wiring as one of the miniaturization techniques. However, at present, copper etching technology has not been established. After forming a wiring trench, a conductor such as metal (for example, copper) is embedded, and wiring and connection portions are polished by CMP (Chemical Mechanical Polishing). Dual damascene technology is used to simultaneously form the two (see, for example, Patent Document 1).

  On the other hand, there is a problem of how to incorporate a multifunctional circuit without impairing image quality performance as an image sensor.

  As an image sensor, it is necessary to suppress degradation in the image quality of the reproduced image (for example, so-called floating of the output value due to white spot defects, dark current, etc.). When the light diffuses through the film and the silicon substrate and reaches the light receiving portion of the photoelectric conversion element, it leads to image quality deterioration such as white spot defect as impurity contamination. Therefore, in order to suppress the factors of image quality deterioration and threshold fluctuation of the MOS transistor in the peripheral circuit, it is necessary to form a diffusion prevention film so as to cover the upper surface of the copper wiring after the copper wiring is formed by the dual damascene technology. is there.

  Hereinafter, with reference to the drawings, a method of manufacturing a CMOS solid-state imaging device in which copper wiring is formed by dual damascene technology will be described.

In the manufacturing method of the CMOS type solid-state imaging device in which the copper wiring is formed by the dual damascene technique, first, as shown in FIG. 5A, the element isolation film 102 is formed on the N-type silicon substrate 101 by STI (Shallow Trench Isolation). To do. Also, a well region (not shown) is formed, and phosphorus (P), arsenic (As), boron (B), and boron difluoride (BF) as impurities are formed in a region that becomes an N-type MOS transistor or a P-type MOS transistor. ₂ ) is selectively implanted, and then a gate oxide film 103 of the transistor is formed by a thermal oxidation technique, and then a gate electrode 104 of the transistor is formed.

  Next, a high concentration diffusion layer region 106 having a sidewall 105 and an LDD (Lightly Doped Drain) structure is formed by ion implantation and heat treatment, and impurities are implanted to form a light receiving portion 107.

  Further, a silicon nitride film 108 serving as a stopper layer is formed on the silicon substrate surface by a low pressure CVD method. Subsequently, in order to improve white spot defects or improve the driving capability of the MOS transistor, an opening 150 is formed in a part of the silicon nitride film by a general-purpose photolithography technique and etching technique. Thereafter, an interlayer insulating film 109 is formed on the silicon nitride film (see FIG. 5A).

  Next, as shown in FIG. 5B, a first connection hole that connects the high-concentration diffusion layer region 106 and a first wiring layer described later is opened in the silicon nitride film 108 and the interlayer insulating film 109. After the barrier metal layer 110A containing tantalum nitride and the tungsten electrode layer 110B are buried in the first connection hole, the first connection portion 110 is formed by polishing using a CMP technique.

  Also, a first inter-wiring insulating film 111 is formed, and this first inter-wiring insulating film is processed by a general-purpose photolithography technique and an etching technique, whereby the first inter-wiring insulating film 111 is formed in a region to be a copper wiring described later. Open the wiring trench. Subsequently, the barrier metal 112A and the copper 112B are embedded in the first wiring groove, and the first wiring layer 112 is formed by polishing excess copper and the barrier metal by a CMP technique. Further, a first diffusion prevention film (for example, a silicon carbide film) 113 for protecting the copper wiring is formed on the first wiring layer 112 (see FIG. 5B).

  Subsequently, as shown in FIG. 5C, a second inter-wiring insulating film 114 is formed on the first diffusion prevention film 113, and then becomes a second connection portion and a second wiring layer. The region is processed by general-purpose photolithography technology and etching technology, barrier metal 115A, 116A and copper 115B, 116B are embedded, and excess copper and barrier metal are polished by CMP technology to thereby form the second connection portion 115 and the second connection portion 115. The wiring layer 116 is formed. Further, a second diffusion preventing film (for example, silicon carbide film) 117 for protecting the copper wiring is formed on the second wiring layer 116 (see FIG. 5C).

  Thereafter, a color resist 118 and an on-chip lens 119 are formed, whereby a CMOS solid-state imaging device can be obtained (see FIG. 5D).

  In the CMOS type solid-state imaging device shown in FIG. 5, layers having different refractive indexes and absorptances are stacked on the light receiving unit 107, and the light receiving efficiency to the photoelectric conversion device is deteriorated due to light attenuation and interference. It is possible. Therefore, recently, a technique for opening a diffusion prevention film in a predetermined range in the upper region of the photoelectric conversion element has been proposed.

  That is, by selectively opening the upper part of the light receiving portion of the photoelectric conversion element, even if a material having a different refractive index or absorption rate of transmitted light is used for the diffusion prevention film for the purpose of preventing diffusion from the wiring material, A technique has been proposed in which light can be favorably incident on the light receiving portion and the deterioration of light receiving efficiency due to light attenuation and interference is suppressed.

  Specifically, as shown in FIG. 5C, after the diffusion prevention film 117 is formed to protect the copper wiring of the second wiring layer, the photoelectric conversion element is formed by a general-purpose photolithography technique and etching technique. The light receiving portion area is opened to form an opening area 120A. Next, the opening region 120A is filled with the CVD oxide film 121, and the excess CVD oxide film 121 is removed by a CMP technique to form the opening 120 above the light receiving portion of the photoelectric conversion element (see FIG. 6A). ). Thereafter, by forming the color resist 118 and the on-chip lens 119, a CMOS type solid-state imaging device can be obtained (see FIG. 6B).

JP 2003-324189 A

By the way, in the above-described conventional CMOS type image pickup device, the diffusion prevention film (the first diffusion prevention film 113 and the second diffusion prevention film) is formed on the upper layer of the wiring layer (the first wiring layer 112 and the second wiring layer 116). 117) is formed, so that it is possible to suppress the diffusion of copper, which is a wiring material, but it is included in the slurry (mainly potassium hydroxide) used in the CMP process performed when forming the wiring layer. Diffusion of potassium cannot be avoided.
That is, between the first inter-wiring insulating film 111 and the first diffusion preventing film 113 and between the second inter-wiring insulating film 114 and the second diffusion preventing film 117, copper or barrier that is a wiring material is used. A large amount of potassium remains in the slurry used as an abrasive when CMP polishing the metal, and this potassium diffuses in the oxide film and the silicon substrate.
When the diffused potassium reaches the light receiving portion of the photoelectric conversion element, it leads to image quality deterioration such as white spot defects as impurity contamination.

  Although it is considered that the slurry may be removed after the CMP is completed, if the treatment with the hydrogen fluoride water or the like generally performed in the CMP polishing of the oxide film is performed, the wiring material such as copper and barrier The metal is also melted, which adversely affects physical defects and wiring characteristics. Therefore, it is considered that the current copper wiring CMP technology does not remove the slurry with hydrogen fluoride water or the like after polishing, and a large amount of potassium remains on the surface of the layer to be polished at the end of CMP polishing. .

  The present invention was devised in view of the above points, and a solid-state imaging device capable of suppressing diffusion of remaining metal elements by performing a flattening process and suppressing deterioration of sensitivity and image quality, and such An object of the present invention is to provide a method for manufacturing a solid-state imaging device.

In order to achieve the above object, a solid-state imaging device according to the present invention includes a semiconductor substrate on which an imaging region having a light receiving portion is formed, and a hole formed in an upper layer of the semiconductor substrate and provided in an insulating film. Formed between a metal wiring layer formed by performing a planarization process using a liquid containing a metal element after a conductor is embedded in the portion, and the semiconductor wiring layer on the lowermost layer, An interlayer insulating film having a connection portion connecting the semiconductor substrate and the lowermost metal wiring layer, and the light receiving portion is formed between the interlayer insulating film and the lowermost metal wiring layer , A diffusion prevention film made of silicon carbide or silicon nitride, and an opening for guiding incident light to the light receiving part are formed on the diffusion prevention film.

Here, formed by covering the light receiving portion between the interlayer insulating film and the lowermost metal wiring layer, the diffusion barrier layer made of silicon carbide or silicon nitride, a flattening treatment using a liquid containing a metal element By applying, diffusion of the remaining metal element to the semiconductor substrate side can be suppressed.

In order to achieve the above object, a method for manufacturing a solid-state imaging device according to the present invention includes a step of forming an imaging region having a light receiving portion on a semiconductor substrate, and an interlayer insulating film is formed on the semiconductor substrate. Forming a connecting portion for connecting the semiconductor substrate and the lowermost metal wiring layer to the interlayer insulating film; and silicon carbide or silicon nitride covering the light receiving portion on the interlayer insulating film. forming a diffusion preventing layer, the lowermost layer of the metal wiring layer that consists by performing the flattening processing using a liquid containing a metal element after embedding the conductor into a hole portion formed in the insulating film And a step of forming in the upper layer of the diffusion prevention film and a step of forming an opening for guiding incident light to the light receiving portion in the upper layer of the diffusion prevention film by an etching process.

Here, forming a lowermost metal wiring layer that is configured on the upper layer of the diffusion barrier layer by performing flattening processing using a liquid containing a metal element after embedding the conductor into a hole portion formed in the insulating film By doing so, it is possible to suppress the diffusion of the remaining metal element to the semiconductor substrate side by performing a planarization process using a liquid containing the metal element on the layer formed on the upper layer of the diffusion prevention film.

  In the solid-state imaging device and the manufacturing method of the solid-state imaging device of the present invention described above, diffusion of the remaining metal element to the semiconductor substrate side can be suppressed by performing the planarization process, and the deterioration of sensitivity and image quality is reduced. be able to.

It is typical sectional drawing for demonstrating the CMOS type solid-state image sensor which is an example of the solid-state image sensor to which this invention is applied. It is typical sectional drawing for demonstrating the manufacturing method of the solid-state image sensor to which this invention is applied. It is typical sectional drawing for demonstrating the modification (1) of the manufacturing method of the solid-state image sensor to which this invention is applied. It is typical sectional drawing for demonstrating the modification (2) of the manufacturing method of the solid-state image sensor to which this invention is applied. It is typical sectional drawing for demonstrating the manufacturing method of the conventional CMOS type solid-state image sensor. It is typical sectional drawing for demonstrating the manufacturing method of the modification of the conventional CMOS type solid-state image sensor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic cross-sectional view for explaining a CMOS type solid-state imaging device as an example of a solid-state imaging device to which the present invention is applied.

  In the CMOS type solid-state imaging device 100 shown in FIG. 1, a transistor gate is formed on an N-type silicon substrate 1 on which an element isolation film 2 is formed and a high-concentration diffusion layer region 6 having an LDD structure and a light-receiving portion 7 are formed. An oxide film 3, a transistor gate electrode 4 and sidewalls 5 are formed.

  Further, on the N-type silicon substrate, a silicon nitride film 8 having an opening 50 in order, an interlayer insulating film 9, a first diffusion preventing film 30, a first inter-wiring insulating film 11, a second diffusion preventing film 13, A second inter-wiring insulating film 14, a third diffusion prevention film 17, and a color resist 18 are formed. An on-chip lens 19 is provided in the light receiving area of the color resist.

  Further, a first connection portion 10 electrically connected to the high concentration diffusion region is formed in the silicon nitride film and the interlayer insulating film, and the first diffusion preventing film and the first inter-wiring insulating film are provided with the first connection portion 10. The first wiring layer 12 electrically connected to the connection portion is formed, and the second diffusion prevention film and the second inter-wiring insulating film are electrically connected to the first wiring layer. The second wiring layer 16 electrically connected to the connecting portion 15 and the second connecting portion is formed.

  Hereinafter, a manufacturing method of the CMOS type solid-state imaging device configured as described above will be described. That is, an example of a method for manufacturing a solid-state imaging device to which the present invention is applied will be described.

In the method for manufacturing a solid-state imaging device to which the present invention is applied, first, as shown in FIG. 2A, an element isolation film 2 is formed on an N-type silicon substrate 1 by STI. Also, a well region (not shown) is formed, and phosphorus (P), arsenic (As), boron (B), and boron difluoride (BF) as impurities are formed in a region that becomes an N-type MOS transistor or a P-type MOS transistor. ₂ ) is selectively implanted, and then the gate oxide film 3 of the transistor is formed by a thermal oxidation technique, and then the gate electrode 4 of the transistor is formed.

  Next, the side wall 5 and the high-concentration diffusion layer region 6 having an LDD structure are formed by ion implantation and heat treatment, and impurities are implanted to form the light receiving portion 7.

  Further, a silicon nitride film 8 serving as a stopper layer is formed on the silicon substrate surface by a low pressure CVD method, and an opening 50 is formed in a part of the silicon nitride film by a general-purpose photolithography technique and an etching technique. Thereafter, an interlayer insulating film 9 is formed on the silicon nitride film (see FIG. 2A).

  Next, as shown in FIG. 2B, a first connection hole connecting the high-concentration diffusion layer region 6 and a first wiring layer described later is opened, and the first connection hole contains tantalum nitride. After embedding the barrier metal layer 10A and the tungsten electrode layer 10B, the first connecting portion 10 is formed by polishing using a CMP technique. Subsequently, a silicon nitride film is formed as a first diffusion preventing film 30 on the interlayer insulating film by a CVD method.

  Also, a first inter-wiring insulating film 11 is formed on the upper layer of the first anti-diffusion film 30, and the first inter-wiring insulating film 11 and the first anti-diffusion film 30 are etched using a general-purpose photolithography technique and etching. The first wiring groove is opened in a region to be a copper wiring described later by processing with the technique. Subsequently, the barrier metal 12A and the copper 12B are embedded in the first wiring groove, and the first copper layer 12 is formed by polishing excess copper and the barrier metal by a CMP technique. Further, a second diffusion preventing film (for example, silicon carbide film) 13 for protecting the copper wiring is formed on the first wiring layer 12 (see FIG. 2B).

  Subsequently, as shown in FIG. 2C, a second inter-wiring insulating film 14 is formed on the second diffusion prevention film 13, and then the second connection portion 15 and the second wiring layer 16 are formed. The second wiring layer 16 is formed by processing a region to be a general photolithography technique and an etching technique, filling the barrier metal 15A, 16A and copper 15B, 16B, and polishing excess copper and the barrier metal by CMP technique. Form. Further, a third diffusion prevention film (for example, silicon carbide film) 17 for protecting the copper wiring is formed on the second wiring layer 16 (see FIG. 2C).

  Thereafter, by forming the color resist 18 and the on-chip lens 19, the above-described CMOS type solid-state imaging device can be obtained (see FIG. 2D).

  In this embodiment, the first diffusion prevention film is formed after the first connection portion is formed in the interlayer insulation film. However, the first diffusion prevention film is formed on the interlayer insulation film, Thereafter, the first connection portion may be formed.

  In this embodiment, a silicon nitride film is used as the first diffusion preventing film. However, it is sufficient if the diffusion of potassium to the silicon substrate side can be suppressed, and the silicon nitride film is not necessarily required. For example, silicon carbide may be used.

  Here, in the CMOS type solid-state imaging device shown in FIG. 1, light reception to the photoelectric conversion device is caused by light attenuation and interference due to the layers having different refractive indexes and absorption rates being stacked on the light receiving unit 7. If there is a concern about the deterioration of efficiency, a CMOS solid-state imaging device in which the second diffusion prevention film and the third diffusion prevention film are opened in a predetermined range in the upper region of the photoelectric conversion element may be used.

  In addition, as a specific manufacturing method (1) of the CMOS type solid-state imaging device in which the second diffusion prevention film and the third diffusion prevention film are opened in a predetermined range in the upper region of the photoelectric conversion element, FIG. ), A third diffusion prevention film 17 is formed to protect the copper wiring of the second wiring layer, and then the light receiving region of the photoelectric conversion element is opened by a general-purpose photolithography technique and etching technique. Then, the opening region 20A is formed. Next, the opening region 20A is filled with the CVD oxide film 21, and the excess CVD oxide film 21 is removed by CMP technique to form the opening 20 above the light receiving portion of the photoelectric conversion element (see FIG. 3A). ). Thereafter, the color resist 18 and the on-chip lens 19 are formed to obtain a CMOS solid-state imaging device having the second diffusion prevention film and the third diffusion prevention film opened in a predetermined range in the upper region of the photoelectric conversion element. (See FIG. 3 (b)).

  Further, as a specific manufacturing method (2) of the CMOS solid-state imaging device in which the second diffusion prevention film and the third diffusion prevention film are opened in a predetermined range of the upper region of the photoelectric conversion element, FIG. ), A third diffusion prevention film 17 is formed to protect the copper wiring of the second wiring layer, and then the light receiving region of the photoelectric conversion element is opened by a general-purpose photolithography technique and etching technique. Then, the opening region 20A is formed. At this time, the first diffusion prevention film is applied as an etching stopper film, and the second diffusion prevention film and the third diffusion prevention film, or the first interlayer insulation film and the second interlayer insulation film are used as the first diffusion film. Etching is performed under etching conditions having a higher selection ratio than that of the prevention film, and the first diffusion prevention film is left in a desired thickness. Subsequently, the opening region 20A is filled with the CVD oxide film 21, and the excess CVD oxide film 21 is removed by a CMP technique to form the opening 20 above the light receiving portion of the photoelectric conversion element (see FIG. 4A). ). Thereafter, the color resist 18 and the on-chip lens 19 are formed to obtain a CMOS solid-state imaging device having the second diffusion prevention film and the third diffusion prevention film opened in a predetermined range in the upper region of the photoelectric conversion element. (See FIG. 4 (b)).

  In the CMOS solid-state imaging device to which the present invention described above is applied, the first diffusion prevention film can suppress the influence of potassium contained in the slurry used as an abrasive when performing CMP polishing. Degradation of image quality such as defects can be reduced.

  Further, by adjusting the material and film thickness of the first diffusion preventing film, it is possible to adjust the amount of incident light and the amount of incident light depending on the wavelength, and it is possible to cope with imaging characteristics such as sensitivity.

  A diffusion preventing film for preventing diffusion from the wiring material (second diffusion preventing film) is formed by opening the second diffusion preventing film and the third diffusion preventing film in a predetermined range of the upper region of the photoelectric conversion element. Even if materials having different refractive indexes and absorption rates of transmitted light are used as the film and the third diffusion prevention film), the incident light to the light receiving portion can be incident well, and the light receiving efficiency is deteriorated due to light attenuation and interference. Can be suppressed.

DESCRIPTION OF SYMBOLS 1 N type silicon substrate 2 Element isolation film 3 Transistor gate oxide film 4 Transistor gate electrode 5 Side wall 6 High concentration diffused layer area | region 7 Light-receiving part 8 Silicon nitride film 9 Interlayer insulating film 10 1st connection part 10A Barrier metal layer 10B Tungsten electrode layer 11 First inter-wiring insulating film 12 First wiring layer 12A Barrier metal 12B Copper 13 Second diffusion prevention film 14 Second inter-wiring insulating film 15 Second connecting portion 15A Barrier metal 15B Copper 16 Second wiring layer 17 Third diffusion prevention film 18 Color resist 19 On-chip lens 20 Opening 20A Opening area 21 CVD oxide film 30 First diffusion prevention film 50 Opening 100 CMOS solid-state imaging device

Claims (2)

A semiconductor substrate on which an imaging region having a light receiving portion is formed;
A metal wiring layer formed on the semiconductor substrate and formed by performing planarization using a liquid containing a metal element after a conductor is embedded in a hole provided in the insulating film;
An interlayer insulating film formed between the semiconductor substrate and the lowermost metal wiring layer, and having a connecting portion connecting the semiconductor substrate and the lowermost metal wiring layer;
A diffusion prevention film formed of silicon carbide or silicon nitride, formed by covering the light receiving portion between the interlayer insulating film and the lowermost metal wiring layer ;
A solid-state imaging device, comprising: an opening formed on an upper layer of the diffusion prevention film, and an opening that guides incident light to the light receiving unit. Forming an imaging region having a light receiving portion on a semiconductor substrate;
Forming an interlayer insulating film on an upper layer of the semiconductor substrate;
Forming a connection portion connecting the semiconductor substrate and the lowermost metal wiring layer in the interlayer insulating film;
Forming a diffusion prevention film made of silicon carbide or silicon nitride covering the light receiving portion on the interlayer insulating film;
The lowermost layer of the metal wiring layer that consists by performing the flattening processing using a liquid containing a metal element after embedding the conductor into a hole portion formed in the insulating film, formed on the upper layer of the diffusion barrier layer And a process of
And a step of forming an opening for guiding incident light to the light receiving portion in the upper layer of the diffusion prevention film by an etching process.

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