JP5211652B2 - Method for manufacturing lateral MOS transistor - Google Patents

Description

  The present invention relates to a lateral MOS (Metal Oxide Silicon) transistor and a manufacturing method thereof.

  Conventionally, in a horizontal power MOS transistor, in order to improve the high breakdown voltage characteristics, the shape of the end portion has been made gentle or the impurity concentration has been made gradient in order to relax the electric field strength at the end portion of the Locos oxide film. Has been done.

Specifically, the end portion of the Locos oxide film on the drain electrode side is made larger than the end portion on the source electrode side and the end portion has a gentle gradient, and the impurity concentration at the end portion of the Locos oxide film is set. The distribution has a gentle concentration gradient similar to the impurity concentration distribution in the diffusion region. With such a shape, a concentration gradient is provided in the n + -type diffusion region serving as the drain extraction region and is formed widely in the current passing direction (lateral direction in the cross section), so that a high voltage is applied on the drain electrode side. Electric field concentration in the withstand voltage characteristics of the Further, the parasitic resistance in the drain region is reduced, and the on-resistance of the MOS transistor is reduced (see, for example, Patent Document 1).
JP 2003-309258 A

  By the way, in the lateral MOS transistor as described above, the electric field concentration in the breakdown voltage characteristic at the end of the Locos oxide film on the drain electrode side (bird's beak shape portion) is reduced, but the electric field concentration is reduced at the end on the source electrode side. There was a problem that was not done.

  Further, in order to make the end portion (bird's beak shape portion) on the drain electrode side of the Locos oxide layer larger than the end portion on the source electrode side and the end portion has a gentle gradient, three oxidation steps are performed. There is a problem that the process is complicated and the manufacturing cost increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a lateral MOS transistor that can be manufactured without adding a manufacturing process and relaxed electric field concentration in a breakdown voltage characteristic on the source electrode side of a Locos oxide film, and a manufacturing method thereof.

  A method of manufacturing a lateral MOS transistor according to one aspect of the present invention includes a source region formed on a surface portion of a semiconductor layer, a drain region formed on the surface portion of the semiconductor layer apart from the source region, A gate oxide layer formed on the surface of the semiconductor layer and connected to the source region; formed on the surface of the semiconductor layer; a first end connected to the gate oxide layer; and a second end A method of manufacturing a lateral MOS transistor including a Locos oxide layer connected to a drain region, wherein the Locos layer includes a first region including the first end, a second region including the second end, A first diffusion step of diffusing impurities in the semiconductor layer through a region including the first region and not including the second region; and the semiconductor through the region including the first region and the second region. Not layered Including a second diffusion step of implanting an object, and an etching step of etching the first region and the second region.

  According to the present invention, it is possible to provide a lateral MOS transistor that can be manufactured without adding a manufacturing process and relaxed electric field concentration in the breakdown voltage characteristic on the source electrode side of the Locos oxide film, and a manufacturing method thereof. It is done.

  Embodiments to which the lateral MOS transistor and the manufacturing method thereof according to the present invention are applied will be described below.

[Embodiment 1]
FIG. 1 is a diagram showing a cross-sectional structure of the lateral MOS transistor of the first embodiment.

  As shown in FIG. 1, the lateral MOS transistor of the first embodiment includes a substrate 100, an n − type active layer 101, a Locos (Local Oxidation of Silicon) oxide film 102, an n − diffusion layer 103, a p − diffusion layer 104, An n− diffusion layer 105, a gate oxide layer 106, an n + drain region 107, an n + source region 108, a p + body diffusion layer 109, and a gate polycide electrode 110 are provided.

  The substrate 100 and the n − -type active layer 101 are composed of a silicon wafer. Among these, the n − type active layer 101 is a silicon semiconductor layer whose conductivity type is changed to n − type by diffusing (implanting) impurities (typically phosphine (P)) into the silicon wafer.

  The Locos oxide layer 102 is a silicon oxide film formed by thermal oxidation using, for example, a silicon nitride film (SiN) as a mask before the gate oxide layer 106 and the gate polysilicide electrode 110 are formed. The n − type active layer 101 is grown inside the n − type active layer 101.

  The Locos oxide layer 102 includes a first region 102a and a second region 102b. The first region 102 a and the second region 102 b are both three-dimensional regions that form part of the Locos oxide layer 102, and are performed through the Locos oxide layer 102 to form the n− diffusion layer 103 and the n− diffusion layer 105. These are regions having different impurity concentrations formed by the diffusion process.

  The first region 102a includes a first end (left end of the Locos oxide layer 102 in the drawing) serving as a connection portion between the Locos oxide layer 102 and the gate oxide layer 106, and the second region 102b includes the Locos oxide layer 102 and the n +. A second end portion (the right end of the Locos oxide layer 102 in the drawing) which is a connection portion with the drain region 107 is included. The first region 102 a is a region close to the n + source region 108 in the Locos oxide layer 102. The impurity concentration of these regions (102a, 102b) will be described later.

  The n- diffusion layer 103 is made conductive by diffusing (injecting) impurities (typically phosphine (P)) through the Locos oxide layer 102 before the gate oxide layer 106 and the gate polysilicide electrode 110 are formed. It is a diffusion layer whose type is n-type. The n − diffusion layer 103 is formed in a region including the junction between the Locos oxide layer 102 and the gate oxide layer 106 and both sides thereof. The impurity concentration is set to such an extent that a withstand voltage strength described later can be realized.

  The p− diffusion layer 104 diffuses (implants) impurities (typically boron (B)) from the surface of the n− type active layer 101 before the gate oxide layer 106 and the gate polysilicide electrode 110 are formed. Thus, the diffusion layer is a p-type conductivity type. The p− type is a region having a lower impurity concentration than the p + type. The impurity concentration is set to such an extent that a withstand voltage strength described later can be realized.

  The n− diffusion layer 105 has a conductivity type of n by diffusing (implanting) impurities (typically phosphine (P)) through the entire Locos oxide layer 102 and the region where the n + drain region 107 will be formed later. A diffused layer which is shaped. The impurity concentration of the n − diffusion layer 105 is set to an impurity concentration that can realize a withstand voltage strength described later.

  The gate oxide layer 106 is an oxide layer formed by thermal oxidation after forming the p- diffusion layer 104 and the n- diffusion layer 105. In the n− diffusion layer 103 and the p− diffusion layer 104 located under the gate oxide film 106, a channel region of the MOS transistor is formed.

  The n + drain region 107 is a region adjacent to the second end portion of the Locos oxide layer 102 (the right end of the Locos oxide layer 102 in the figure), and impurities (typically phosphine (P)) from the surface of the n− diffusion layer 105. It is a drain region formed in the n − diffusion layer 105 by being diffused (implanted). Similar to the n + source region 108, the n + drain region 107 is a region set to an n + type having an impurity concentration higher than that of the n− type.

  The n + source region 108 diffuses (implants) impurities (typically phosphine (P)) into a partial region of the p− diffusion layer 104 (region near the left end of the gate polycide electrode 110 in the drawing). Thus, the conductivity type is n + type. Note that the n + type is a region having a higher impurity concentration than the n− type.

  The p + body diffusion layer 109 is a region whose conductivity type is changed to p-type by diffusing (implanting) impurities (typically boron (B)) from the surface of the p− diffusion layer 104. A p + type diffusion layer for holding the diffusion layer 104 at the ground potential. The p + body diffusion layer 109 is grounded, and the P− diffusion layer 104 is grounded via the p + body diffusion layer 109.

The gate polycide electrode 110 is a gate electrode having a laminated structure of silicide and polysilicon. Silicide is a refractory metal or transition metal and silicon alloyed by heat treatment, and for example, WSi ₂ or MoSi ₂ silicide can be used.

  Here, in the lateral MOS transistor of the first embodiment, the thickness of the first region 102a including the first end (left end in the figure) of the Locos oxide layer 102 includes the second end (right end in the figure). It is thinner than the second region 102b.

  In the manufacturing process of the lateral MOS transistor according to the first embodiment, a first diffusion step for diffusing impurities to produce the n − diffusion layer 103 and a second diffusion for diffusing impurities to produce the n − diffusion layer 105 are performed. The process is repeated in the first region 102a. For this reason, the first region 102a of the Locos oxide layer 102 has a higher impurity concentration than the second region 102b.

  FIG. 2 is a characteristic diagram showing the relationship between the impurity dose and the etching rate. As shown in this characteristic diagram, when the impurity dose in the diffusion process increases, the impurity concentration in the layer increases, and the etching rate increases substantially linearly in proportion thereto. This is because when the impurities in the layer increase, the bonding force of atoms in the layer is reduced, and etching becomes easy. For this reason, the first region 102a of the Locos oxide layer 102 becomes an oxide layer having an etching rate faster than that of the second region 102b.

  By utilizing such a difference in etching rate, a Locos oxide layer is etched at the stage of etching a sacrificial oxide film (an oxide film formed at the same position as the gate oxide layer 106 in FIG. 1 during the manufacturing process), which will be described later. Since the first region 102a of 102 is etched more than the second region 102b, the first region 102a is made thinner than the second region 102b.

  FIG. 3 is a diagram showing a manufacturing process of the lateral MOS transistor of the first embodiment.

  First, as shown in FIG. 3A, a buffer oxide layer and a silicon nitride layer (SiN) are formed on a substrate 100 and an n − type active layer 101 formed of a silicon wafer. As for the silicon nitride layer and the buffer silicon layer, the region where the Locos oxide layer 102 is formed is removed by etching.

  FIG. 3B shows a state where the Locos oxide layer 102 is formed. Following the state shown in FIG. 3A, thermal oxidation is performed using the silicon nitride layer as a mask, and the silicon nitride layer and the buffer silicon layer which are masks are removed. As a result, Locos 102 is formed in a desired region on the n − -type active layer 101 as shown in FIG. Locos oxide layer 102 is formed to bite into n − type active layer 101. Thereby, the structure of FIG. 3B is obtained.

  FIG. 3C is a diagram illustrating a state in which the second diffusion process is completed. Following the state shown in FIG. 3B, impurities (typically phosphine) are formed through the n − -type active layer 101 and the Locos oxide layer 102 in the region including the first end (left end in the figure) of the Locos oxide layer 102. An n − diffusion layer 103 is formed in the n − type active layer 101 by performing a first diffusion step of diffusing (implanting) (P)). By this first diffusion step, impurities are also implanted into a part of the Locos oxide layer 102 (a region located on the n − diffusion layer 103). This area becomes the first area 102a.

The first diffusion step is performed, for example, with a dose amount of 3.0 × 10 ¹² (atoms / cm ² ).

  Further, by diffusing (implanting) impurities (typically boron (B)) from the surface of the n − -type active layer 101 in the region adjacent to the n − diffusion layer 103 (the left region in the figure). , A p- diffusion layer 104 is formed.

  Further, in a region including the entire Locos oxide layer 102 and the n − -type active layer 101 adjacent to the right side of the Locos oxide layer 102, impurities (typically phosphine are typically passed through the Locos oxide layer 102 and the n − -type active layer 101. By performing a second diffusion step of diffusing (implanting) (P)), an n − diffusion layer 105 is formed in the n − type active layer 101.

  Thus, impurities are implanted into the first region 102a of the Locos oxide layer 102 by the second diffusion step in addition to the first diffusion step, and impurities are implanted into the second region 102b only by the second diffusion step. The Thus, the structure of FIG. 3C is obtained.

  Since the first diffusion step and the second diffusion step are performed in the same chamber, the first region 102a and the second region 102b of the Locos oxide layer 102 having different etching rates are not increased in manufacturing cost. Can be produced.

Note that the second diffusion step is performed, for example, at a dose of 8.0 × 10 ¹¹ (atoms / cm ² ). Thus, the impurity concentration of the first region is 7.0 × 10 ¹⁶ (atoms / cm ³ ), and the impurity concentration of the second region is 4.0 × 10 ¹⁶ (atoms / cm ³ ).

  FIG. 3D is a diagram showing a state where the wet etching of the sacrificial oxide film is finished. Following the state of FIG. 3C, the entire surface is thermally oxidized to form a sacrificial oxide film. The sacrificial oxide film is removed by wet etching.

  According to the manufacturing process of the lateral MOS transistor of the first embodiment, the Locos oxide layer 102 is also etched by wet etching of the sacrificial oxide film that is necessarily performed in the manufacturing process of the transistor.

  In this etching, the first region 102a is made thinner than the second region 102b due to a difference in etching rate due to a difference in impurity concentration between the first region 102a and the second region 102b. Thereby, the structure of FIG. 3D is obtained.

  Thus, according to the manufacturing process of the lateral MOS transistor of the first embodiment, the layer thickness on the source region side of the Locos oxide layer 102 can be reduced without adding a new process.

  The etching rate is set so that, for example, the first region 102a is about 1.2 times faster than the second region 102b due to the difference in impurity concentration between the first region 102a and the second region 102b. .

  FIG. 3E shows a state after the gate oxide layer 106 is formed. As shown in FIG. 3D, after etching the first region 102a and the second region 102b of the Locos oxide layer 102, a gate oxide layer 106 is formed on the entire element by thermal oxidation treatment. Thereby, the structure of FIG. 3E is obtained.

  FIG. 3F shows a state in which the n + drain region 107, the n + source region 108, the p + body diffusion layer 109, and the gate polycide electrode 110 are formed. Following the state shown in FIG. 3E, an impurity (typically phosphine (P)) is further diffused (implanted) into the n − diffusion layer 105 adjacent to the right side of the second region 102b to thereby obtain an impurity concentration. N + drain region 107 is formed.

  Next, a gate polycide electrode 110 is formed. The gate polycide electrode 110 includes a region on the p− diffusion layer 104 for forming the n + drain region 107 and the n + source region 108, and a side for forming the n + drain region 107 in the lateral length of the Locos oxide layer 102. It is formed so as not to cover about 2/5. The gate polycide electrode 110 is manufactured by forming a gate polycide layer over the entire element and then performing an etching process using a mask.

  Further, an impurity (typically phosphine (P)) is further diffused (implanted) in a region adjacent to the left end of the gate polycide electrode 110, thereby increasing the impurity concentration and forming the n + source region 108.

  Further, an impurity (typically boron (B)) is diffused (implanted) in a region adjacent to the left side of the n + source region 108 to form a p + body diffusion layer 109 in the p− diffusion layer 104. .

  Thus, the lateral MOS transistor shown in FIG. 3F is completed. For use as an actual device, the gate oxide layer 106 existing on the n + drain region 107, the n + source region 108, and the p + body diffusion layer 109 is removed (this state is shown in FIG. 4). . Although not shown here, a drain electrode and a source electrode are formed on the n + drain region 107 and the n + source region 108, and for insulating the gate polycide electrode 110, the drain electrode, and the source electrode. An insulating layer is formed.

  FIG. 4 is a diagram showing the structure and breakdown voltage strength distribution of the lateral MOS transistor of the first embodiment. In the lateral MOS transistor shown in FIG. 4, the gate oxide layer 106 existing on the n + drain region 107, the n + source region 108, and the p + body diffusion layer 109 is removed.

  In the lateral MOS transistor of the first embodiment, in the Locos oxide layer 102, the first region 102a on the source (n + source region 108) side is thinner than the second region 102b. In a state where a voltage of about 100 (V) is applied to the drain region 107, the n + source region 108 is grounded, and 0 (V) is applied to the gate polycide layer 110 (that is, the gate is turned off), FIG. 4 shows the pressure strength distribution as shown by the solid line. For comparison, the breakdown voltage strength distribution of a lateral MOS transistor in which the first region 102a is set to the same layer thickness as the second region 102b as in a conventional lateral MOS transistor is indicated by a broken line.

  As shown in FIG. 4, according to the lateral MOS transistor of the first embodiment, the breakdown voltage is improved by reducing the layer thickness of the Locos oxide layer 102 on the source region side, which has been a problem in the past. The concentration of the electric field on the source region side of the Locos oxide layer 102 can be reduced.

  In addition, the Locos oxide layer 102 having a structure for reducing the concentration of the electric field is formed by wet etching of a sacrificial oxide film that is inevitably performed in a transistor manufacturing process without adding a manufacturing process. Produced. For this reason, it can be manufactured without adding a new manufacturing process, and an increase in manufacturing cost can be suppressed.

  Further, as shown in FIG. 4, the lateral MOS transistor having the breakdown voltage distribution capable of relaxing the electric field concentration has the first region closer to the n + source region 108 without increasing the lateral length of the Locos oxide layer 102. Since it is realized by reducing the thickness of 102a, a lateral MOS transistor can be provided at low cost without increasing the area of the transistor in plan view.

  The substrate 100 may be a semiconductor layer formed on an insulating layer of an SOI (Silicon On Insulator) wafer.

[Embodiment 2]
FIG. 5 is a diagram showing a cross-sectional structure and electric field intensity distribution of the lateral MOS transistor of the second embodiment. The lateral MOS transistor of the second embodiment does not include the n− diffusion layer 105 shown in the lateral MOS transistor of the first embodiment because the second diffusion process is not performed in the manufacturing process. This is because the channel region is formed between the n + drain region 107 and the n + source region 108 if the n− type active layer 101 exists even if the n− diffusion layer 105 is not formed. Further, since the second diffusion step is not performed, the impurity concentrations of the first region 102a and the second region 102b are also different from those of the first embodiment. Since the rest is the same as the horizontal MOS transistor of the first embodiment, the redundant description is avoided and only the differences will be described below.

  FIG. 6 is a diagram illustrating a manufacturing process of the lateral MOS transistor of the second embodiment. This manufacturing process is the same as the manufacturing process of the lateral MOS transistor of the first embodiment shown in FIG. 3 except that the second diffusion process for forming the n− diffusion layer 105 is not provided.

  For this reason, the steps shown in FIGS. 6A to 6C are the same as those in FIGS. 3A to 3C, and the description thereof is omitted.

  FIG. 6D is a diagram illustrating a state where wet etching for removing the sacrificial oxide film is completed. In the state shown in FIG. 6C, the first region 102a of the Locos oxide layer 102 is implanted with impurities from the first diffusion step, and the second region 102b is not implanted with impurities. Thus, the impurity concentration of the first region 102a and the second region 102b is different from that in the first embodiment, but the first region 102a has a higher impurity concentration and a higher etching rate than the second region 102b. It has become.

For example, the first diffusion step is performed with a dose amount of 3.0 × 10 ¹² (atoms / cm ² ), and the impurity concentration of the first region is 5.0 × 10 ¹⁶ (atoms / cm ³ ).

  Following the state of FIG. 6C, a sacrificial oxide film is formed in a region where the gate oxide layer 106 will be formed later. In order to remove the sacrificial oxide film, the Locos oxide layer 102 is also etched by wet etching. At this time, the first region 102a is made thinner than the second region 102b due to a difference in etching rate due to a difference in impurity concentration between the first region 102a and the second region 102b. Thereby, the structure of FIG. 6D is obtained.

  FIG. 6E shows a state after the gate oxide layer 106 is formed. As shown in FIG. 6D, after the first region 102a and the second region 102b of the Locos oxide layer 102 are etched, a gate oxide layer 106 is formed.

  FIG. 6F shows a state in which the n + drain region 107, the n + source region 108, the p + body diffusion layer 109, and the gate polycide electrode 110 are formed. Following the state shown in FIG. 6E, an impurity (typically phosphine (P)) is further diffused (implanted) into the n − -type active layer 101 adjacent to the right side of the second region 102b, whereby the impurity The n + drain region 107 is formed by increasing the concentration.

  Next, a gate polycide electrode 110 is formed. The gate polycide electrode 110 includes a region on the p− diffusion layer 104 for forming the n + drain region 107 and the n + source region 108, and a side for forming the n + drain region 107 in the lateral length of the Locos oxide layer 102. It is formed so as not to cover about 2/5. The gate polycide electrode 110 is manufactured by forming a gate polycide layer over the entire element and then performing an etching process using a mask.

  Further, an impurity (typically phosphine (P)) is further diffused (implanted) in a region adjacent to the left end of the gate polycide electrode 110, thereby increasing the impurity concentration and forming the n + source region 108.

  Further, an impurity (typically boron (B)) is diffused (implanted) in a region adjacent to the left side of the n + source region 108 to form a p + body diffusion layer 109 in the p− diffusion layer 104. .

  Thus, the lateral MOS transistor shown in FIG. 6F is completed. For use as an actual element, as shown in FIG. 5, the gate oxide layer 106 existing on the n + drain region 107, the n + source region 108, and the p + body diffusion layer 109 is removed. Although not shown here, a drain electrode and a source electrode are formed on the n + drain region 107 and the n + source region 108, and for insulating the gate polycide electrode 110, the drain electrode, and the source electrode. An insulating layer is formed.

  As described above, the lateral MOS transistor of the second embodiment is improved in breakdown voltage by reducing the layer thickness of the Locos oxide layer 102 on the source region side. The concentration of the electric field on the source region side can be reduced.

  In addition, the Locos oxide layer 102 having a structure for reducing the concentration of the electric field is realized without adding a new manufacturing process. For this reason, an increase in manufacturing cost can be suppressed.

[Embodiment 3]
FIG. 7 is a diagram showing a cross-sectional structure and electric field intensity distribution of the lateral MOS transistor of the third embodiment. In the lateral MOS transistor of the third embodiment, the second diffusion step is performed step by step with a plurality of doses in the manufacturing process, so that the first region 102a and the second region 102b in the first embodiment are The third embodiment is different from the first embodiment in that the third region 102c is formed. Since the rest is the same as the horizontal MOS transistor of the first embodiment, the redundant description is avoided and only the differences will be described below.

  FIG. 8 is a diagram illustrating a manufacturing process of the lateral MOS transistor of the third embodiment. This manufacturing process is the same as the manufacturing process of the lateral MOS transistor of the first embodiment shown in FIG. 3 except that the second diffusion process is performed stepwise with a plurality of doses.

  For this reason, since the process shown to Fig.8 (a) and (b) is the same as FIG. 3 (a) and (b), the description is abbreviate | omitted.

  FIG. 8C is a diagram illustrating a state in which the second diffusion process has been completed. Following the state shown in FIG. 8B, an impurity (typically phosphine) is formed through the n − -type active layer 101 and the Locos oxide layer 102 in a region including the first end portion (left end in the drawing) of the Locos oxide layer 102. An n − diffusion layer 103 is formed in the n − type active layer 101 by performing a first diffusion step of diffusing (implanting) (P)). By this first diffusion step, impurities are also implanted into a part of the Locos oxide layer 102 (a region located on the n − diffusion layer 103). This area becomes the first area 102a.

The first diffusion step is performed, for example, with a dose amount of 3.0 × 10 ¹² (atoms / cm ² ).

  Further, by diffusing (implanting) impurities (typically boron (B)) from the surface of the n − -type active layer 101 in the region adjacent to the n − diffusion layer 103 (the left region in the figure). , A p- diffusion layer 104 is formed.

Next, the second diffusion process is performed stepwise. First, as a first stage, by performing a second diffusion step of diffusing (implanting) impurities (typically phosphine (P)) through the Locos oxide layer 102 in the region on the left half of the Locos oxide layer 102. The n − diffusion layer 111 is formed in the n − type active layer 101. The first stage of the second diffusion process is performed, for example, with a dose amount of 1.0 × 10 ¹² (atoms / cm ² ).

  Further, as a second stage, in the region including the entire Locos oxide layer 102 and the n − type active layer 101 adjacent to the right side of the Locos oxide layer 102, impurities are introduced through the Locos oxide layer 102 and the n − type active layer 101. (Typically phosphine (P)) is diffused (injected). As a result, an n − diffusion layer 105 is formed in the n − type active layer 101.

  Thus, impurities are implanted into the first region 102a of the Locos oxide layer 102 not only by the first diffusion step but also by the second diffusion step (both the first step and the second step), and the third region 102c. The impurity is implanted in the first stage and the second stage of the second diffusion process. Further, the impurity is implanted into the second region 102b only by the second stage of the second diffusion process. Thus, the structure of FIG. 8C is obtained.

  Since the first diffusion step and the second diffusion step are performed in the same chamber, the first region 102a, the third region 102c, and the second region 102b of the Locos oxide layer 102 having different etching rates are manufactured. It can be manufactured without increasing the cost.

Note that the second stage of the second diffusion step is performed, for example, at a dose of 8.0 × 10 ¹¹ (atoms / cm ² ). Thus, the impurity concentration of the first region 102a is 7.0 × 10 ¹⁶ (atoms / cm ³ ), the impurity concentration of the third region 102c is 7.0 × 10 ¹⁶ (atoms / cm ³ ), and the second region 102b The impurity concentration is 4.0 × 10 ¹⁶ (atoms / cm ³ ).

  FIG. 8D is a diagram showing a state where the wet etching of the sacrificial oxide film is finished. Following the state of FIG. 8C, the entire surface is thermally oxidized to form a sacrificial oxide film. The sacrificial oxide film is removed by wet etching.

  According to the manufacturing process of the lateral MOS transistor of the first embodiment, the Locos oxide layer 102 is also etched by the wet etching of the sacrificial oxide film that is necessarily performed in the manufacturing process of the transistor, and the first region 102a, the third region The first region 102a is thinner than the third region 102c and the third region 102c is thinner than the second region 102b due to the difference in etching rate due to the difference in impurity concentration between the region 102c and the second region 102b. The As a result, a structure in which the layer thickness is set stepwise as shown in FIG. 8D is obtained.

  Thus, according to the manufacturing process of the lateral MOS transistor of the first embodiment, the layer thickness on the source region side of the Locos oxide layer 102 can be reduced without adding a new process.

  FIG. 8E shows a state after the gate oxide layer 106 is formed. As shown in FIG. 8D, after the first region 102a, the third region 102c, and the second region 102b of the Locos oxide layer 102 are etched, a gate oxide layer 106 is formed over the entire element by thermal oxidation treatment. As a result, the structure shown in FIG.

  FIG. 8F shows a state in which the n + drain region 107, the n + source region 108, the p + body diffusion layer 109, and the gate polycide electrode 110 are formed. Following the state shown in FIG. 8E, an impurity (typically phosphine (P)) is further diffused (implanted) into the n − diffusion layer 105 adjacent to the right side of the second region 102b, thereby providing an impurity concentration. N + drain region 107 is formed.

  Next, a gate polycide electrode 110 is formed. The gate polycide electrode 110 includes a region on the p− diffusion layer 104 for forming the n + drain region 107 and the n + source region 108, and a side for forming the n + drain region 107 in the lateral length of the Locos oxide layer 102. It is formed so as not to cover about 2/5. The gate polycide electrode 110 is manufactured by forming a gate polycide layer over the entire element and then performing an etching process using a mask.

  Further, an impurity (typically phosphine (P)) is further diffused (implanted) in a region adjacent to the left end of the gate polycide electrode 110, thereby increasing the impurity concentration and forming the n + source region 108.

  Further, an impurity (typically boron (B)) is diffused (implanted) in a region adjacent to the left side of the n + source region 108 to form a p + body diffusion layer 109 in the p− diffusion layer 104. .

  Thus, the lateral MOS transistor shown in FIG. 8F is completed. For use as an actual device, the gate oxide layer 106 existing on the n + drain region 107, the n + source region 108, and the p + body diffusion layer 109 is removed (this state is shown in FIG. 4). . Although not shown here, a drain electrode and a source electrode are formed on the n + drain region 107 and the n + source region 108, and for insulating the gate polycide electrode 110, the drain electrode, and the source electrode. An insulating layer is formed.

  The lateral MOS transistor and the manufacturing method thereof according to the exemplary embodiment of the present invention have been described above. However, the present invention is not limited to the specifically disclosed embodiment, and is from the claims. Various modifications and changes can be made without departing.

1 is a diagram showing a cross-sectional structure of a lateral MOS transistor according to a first embodiment. It is a characteristic view showing the relationship between the dose of impurities and the etching rate. FIG. 5 is a diagram showing a manufacturing process of the lateral MOS transistor of the first embodiment. It is a figure which shows the structure and pressure | voltage resistant strength distribution of the horizontal MOS transistor of Embodiment 1. FIG. It is a figure which shows the cross-section of the horizontal MOS transistor of Embodiment 2, and electric field strength distribution. FIG. 10 is a diagram showing a manufacturing process of the lateral MOS transistor of the second embodiment. It is a figure which shows the cross-section of a horizontal MOS transistor of Embodiment 3, and electric field strength distribution. FIG. 10 is a diagram showing a manufacturing process of the lateral MOS transistor of the third embodiment.

Explanation of symbols

100 substrate 101 n-type active layer 102 Locos oxide film 102a first region 102b second region 102c third region 103 n-diffusion layer 104 p-diffusion layer 105 n-diffusion layer 106 gate oxide layer 107 n + drain region 108 n + source Region 109 p + body diffusion layer 110 gate polycide electrode 111 n- diffusion layer

Claims (3)

A source region formed on the surface portion of the semiconductor layer, a drain region formed on the surface portion of the semiconductor layer apart from the source region, and formed on the surface portion of the semiconductor layer and connected to the source region And a Locos oxide layer formed on a surface portion of the semiconductor layer, having a first end connected to the gate oxide layer and a second end connected to the drain region. In the method of manufacturing a transistor, the Locos layer includes a first region including the first end and a second region including the second end.
A first diffusion step of diffusing impurities in the semiconductor layer through a region including the first region and not including the second region;
A second diffusion step of implanting impurities into the semiconductor layer through the region including the first region and the second region;
An etching process for etching the first region and the second region. A method for manufacturing a lateral MOS transistor. The second diffusion step, the in the second region of the first region and connected to the side, are carried out stepwise in the transverse direction at a plurality of different doses, the manufacturing method of the lateral MOS transistor according to claim 1 . The etching process, the a wet etching process for removing the sacrificial oxide film formed on the surface of the semiconductor layer prior to making the gate oxide layer, production of the lateral MOS transistor according to claim 1 or 2 Way .

Images