JP5296140B2 - Three-dimensional image processing apparatus and control method thereof - Google Patents

Description

  The present invention relates to a three-dimensional image processing apparatus and a control method thereof, and more particularly to a three-dimensional image processing apparatus that converts a three-dimensional image in a first format into a three-dimensional image in a second format.

  A three-dimensional image display device that displays a three-dimensional image that is a two-dimensional image that a viewer feels stereoscopically is known (see, for example, Patent Document 1). In recent years, home televisions having a function of displaying such a three-dimensional image are being realized.

  This three-dimensional image display device displays an image that the viewer feels stereoscopically by displaying an image for the right eye and an image for the left eye that have parallax. For example, the three-dimensional image display device alternately displays an image for the right eye and an image for the left eye for each frame.

JP 2000-293155 A

  However, when a three-dimensional image is to be realized while maintaining the same image quality as a conventional two-dimensional image, it is necessary to display two types of images for the right eye and for the left eye in the three-dimensional image. Therefore, for example, it is necessary to display an image at a frame rate (for example, 120 fps) that is twice that of a conventional two-dimensional image (for example, 60 fps).

  Accordingly, the three-dimensional image display device needs to include an image processing circuit that can process an image having a double frame rate, for example. When trying to realize such a high-performance image processing circuit, there arises a problem that the cost is increased and a significant circuit change from the conventional image display device is required.

  On the other hand, in Patent Document 1, a plurality of graphics processing units are operated in parallel to realize high-speed image processing without providing a high-performance image processing circuit.

  However, even when a plurality of image processing circuits (graphics processing units) are used, an increase in cost occurs due to an increase in the number of image processing circuits.

  Accordingly, an object of the present invention is to provide a three-dimensional image processing apparatus and a control method thereof that can generate a high-quality three-dimensional image while suppressing an increase in cost.

  In order to achieve the above object, a three-dimensional image processing apparatus according to the present invention includes a two-screen processing mode for generating a composite image including a first image and a second image in one screen, and a first input in a first format. A three-dimensional image processing apparatus having a three-dimensional image processing mode for converting a three-dimensional image into an output three-dimensional image in a second format, wherein the first image is converted into a first format in the two-screen processing mode. A first image processing unit for generating a first processed image, and a second format conversion process for generating a second processed image by performing a second format conversion process on the second image in the two-screen processing mode. A second image processing unit; and a synthesis unit that generates the synthesized image by synthesizing the first processed image and the second processed image. The first image processing unit includes the three-dimensional image processing module. The first input image that is a part of the first input three-dimensional image is subjected to a third format conversion process to generate a first output image that is a part of the output three-dimensional image, The second image processing unit performs a fourth format conversion process on the second input image that is a part of the first input three-dimensional image in the three-dimensional image processing mode, thereby obtaining one of the output three-dimensional images. A second output image that is a part is generated.

  According to this configuration, in the 3D image processing apparatus according to the present invention, in the 3D image processing mode, the first image processing unit processes the first input image that is a part of the first input 3D image, The second image processing unit processes a second input image that is a part of the first input three-dimensional image. By performing such parallel processing, the processing capability of the first image processing unit and the sub-second image processing unit can be reduced to about half compared to the case where the input three-dimensional image is processed by one image processing unit.

  Furthermore, in the three-dimensional image processing apparatus according to the present invention, in the two-screen processing mode, the first image processing unit that processes the first image and the second image processing unit that processes the second image are subjected to this parallel processing. By using it, the circuit addition from the conventional image processing apparatus can be suppressed. Therefore, the three-dimensional image processing apparatus according to the present invention can generate a high-quality three-dimensional image while suppressing an increase in cost.

  The first, second, third, and fourth format conversion processes may include at least one of an image size change process, a frame rate conversion process, and an interlace system to progressive system conversion process. .

  Further, the third format conversion process and the fourth format conversion process may include a process for increasing a frame rate.

  According to this configuration, the three-dimensional image processing apparatus according to the present invention can generate a high-quality three-dimensional image with a high frame rate and can suppress an increase in cost.

  The first input 3D image and the output 3D image include a left eye image for a viewer's left eye and a right eye image for the viewer's right eye, and the third format conversion The process and the fourth format conversion process may further include a process of changing an arrangement pattern of the left-eye image and the right-eye image.

  The first, second, third, and fourth format conversion processes may include a conversion process from an interlace method to a progressive method.

  The three-dimensional image processing apparatus further includes a memory, and the first image processing unit is included in the third format conversion process in the first input image in the three-dimensional image processing mode. A first pre-processing unit that generates a third processed image by performing a first pre-processing including a process of reducing an image size, and stores the third processed image in the memory; and the second image processing unit includes: In the three-dimensional image processing mode, a second processed image is generated by performing a second preprocessing included in the fourth format conversion process and including a process of reducing the image size, on the second input image. A second pre-processing unit that stores the fourth processed image in the memory, and the first image processing unit further includes the third processing stored in the memory in the three-dimensional image processing mode. image The first output image is converted into a fifth processed image including at least one of the fourth processed images by performing a first post-process included in the third format conversion process and including a process of enlarging the image size. A first post-processing unit that generates the sixth processed image including at least one of the third processed image and the fourth processed image stored in the memory in the three-dimensional image processing mode; A second post-processing unit that generates the second output image by performing a second post-process included in the 4-format conversion process and including a process of enlarging the image size may be provided.

  According to this configuration, the 3D image processing apparatus according to the present invention can reduce the capacity of the memory, for example, by storing the image after the image size is compressed in the memory.

  The first post-processing and the second post-processing further include processing for changing an arrangement pattern of the left-eye image and the right-eye image, and the first post-processing unit is stored in the memory. The fifth processed image including a plurality of pixels corresponding to the first output image is read out from the plurality of pixels included in the stored third processed image and fourth processed image, and the fifth processed image is read. The first post-processing is performed to generate the first output image, and the second post-processing unit includes a plurality of the third processing image and the fourth processing image stored in the memory. The sixth processed image including a plurality of pixels corresponding to the second output image is read out, and the second post-processing is performed on the sixth processed image to generate the second output image. May be.

  According to this configuration, the three-dimensional image processing apparatus according to the present invention can perform the left-eye image and the right-eye image even when the pixel corresponding to the first output image is included in the fourth processed image. The pattern conversion can be appropriately performed. Similarly, the 3D image processing apparatus according to the present invention performs pattern conversion between the left-eye image and the right-eye image even when the pixel corresponding to the second output image is included in the third processed image. Can be performed appropriately.

  Further, the first pre-processing and the second pre-processing may include processing for converting a scanning method from an interlace method to a progressive method.

  The first, second, third, and fourth format conversion processes include at least one of image size change and frame rate conversion, and the 3D image processing apparatus further includes the two-screen process. In the mode, the first image is generated by converting the third image from the interlace method to the progressive method, and in the two-screen processing mode, the fourth image is converted from the interlace method to the progressive method. A second IP conversion unit that generates the second image by converting the second input 3D image from the interlace method to the progressive mode in the 3D image processing mode. The first input three-dimensional image may be generated by converting into a method.

  In addition, the first image processing unit performs the first format conversion process on the first input image in the three-dimensional image processing mode, whereby one of the left half and the right half of the output three-dimensional image. The first output image is generated, and the second image processing unit performs the first format conversion process on the second input image in the three-dimensional image processing mode, thereby obtaining the output three-dimensional image. A second output image that is the other of the left half and the right half may be generated.

  The 3D image processing apparatus further includes an input selection unit that divides the first input 3D image into the first input image and the second input image in the 3D image processing mode. Also good.

  The present invention can be realized not only as such a three-dimensional image processing apparatus, but also as a method for controlling a three-dimensional image processing apparatus or a three-dimensional image processing using characteristic means included in the three-dimensional image processing apparatus as steps. It can also be realized as a method or as a program for causing a computer to execute such characteristic steps. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM and a transmission medium such as the Internet.

  Furthermore, the present invention can be realized as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a three-dimensional image processing apparatus, or a tertiary such as a digital television equipped with such a three-dimensional image processing apparatus. It can be realized as an original image display device or a 3D image display system including such a 3D image display device.

  As described above, the present invention can provide a three-dimensional image processing apparatus capable of generating a high-quality three-dimensional image while suppressing an increase in cost.

It is a block diagram which shows the structure of the three-dimensional image display system which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the format conversion process by the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the format conversion process by the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the arrangement | positioning pattern of the three-dimensional image which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the arrangement | positioning pattern of the three-dimensional image which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the arrangement | positioning pattern of the three-dimensional image which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the arrangement | positioning pattern of the three-dimensional image which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the arrangement | positioning pattern of the three-dimensional image which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the arrangement | positioning pattern of the three-dimensional image which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the arrangement | positioning pattern of the three-dimensional image which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the arrangement | positioning pattern of the three-dimensional image which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the image for left eyes and the image for right eyes which concerns on Embodiment 1 of this invention. It is a figure which shows the operation example at the time of 2 screen processing mode by the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the main screen image process part which concerns on Embodiment 1 of this invention, and a subscreen image process part. It is a figure which shows the operation example at the time of the three-dimensional image processing mode by the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the operation example at the time of the three-dimensional image processing mode by the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the operation example at the time of the three-dimensional image processing mode by the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the operation example at the time of the three-dimensional image processing mode by the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the operation example at the time of the three-dimensional image processing mode by the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the operation example at the time of the three-dimensional image processing mode by the three-dimensional image processing apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the main screen image process part which concerns on Embodiment 2 of this invention, and a subscreen image process part. It is a figure which shows the operation example at the time of the three-dimensional image processing mode by the three-dimensional image processing apparatus which concerns on Embodiment 2 of this invention.

  Hereinafter, embodiments of a three-dimensional image processing apparatus according to the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The three-dimensional image processing apparatus according to Embodiment 1 of the present invention divides a three-dimensional image into two images, and the two divided images are processed in parallel by two image processing units. Furthermore, in the 3D image processing apparatus according to the present invention, when displaying the main screen image and the sub screen image in one screen, the image processing unit used for processing the main screen image and the processing of the sub screen image An image processing unit used for the parallel processing is used. As a result, the image processing apparatus according to Embodiment 1 of the present invention can suppress circuit addition, and can generate a high-quality three-dimensional image while suppressing an increase in cost.

  First, the configuration of a 3D image display system including the 3D image processing apparatus according to Embodiment 1 of the present invention will be described.

  FIG. 1 is a block diagram showing the configuration of the three-dimensional image display system according to Embodiment 1 of the present invention.

  A three-dimensional image display system 10 shown in FIG. 1 includes a digital television 20, a digital video recorder 30, and shutter glasses 43. In addition, the digital television 20 and the digital video recorder 30 are connected via an HDMI (High-Definition Multimedia Interface) cable 40.

  The digital video recorder 30 converts the format of a 3D image recorded on an optical disc 41 such as a BD (Blu-ray disc), and outputs the converted 3D image to the digital television 20 via the HDMI cable 40.

  The digital television 20 converts the 3D image output from the digital video recorder 30 and the 3D image format included in the broadcast wave 42 and displays the converted image. For example, the broadcast wave 42 is a terrestrial digital television broadcast, a satellite digital television broadcast, or the like.

  Note that the digital video recorder 30 may convert the format of a three-dimensional image recorded on a recording medium other than the optical disk 41 (for example, a hard disk drive, a nonvolatile memory, or the like). In addition, the digital video recorder 30 may convert the format of a 3D image included in the broadcast wave 42 or a 3D image acquired via a communication network such as the Internet. The digital video recorder 30 may convert the format of the three-dimensional image input to an external input terminal (not shown) or the like by an external device.

  Similarly, the digital television 20 may convert the format of the three-dimensional image recorded on the optical disc 41 and other recording media. In addition, the digital television 20 may convert the format of the 3D image acquired via a communication network such as the Internet. In addition, the digital television 20 may convert the format of a three-dimensional image input to an external input terminal (not shown) or the like by an external device other than the digital video recorder 30.

  Further, the digital television 20 and the digital video recorder 30 may be connected by a standard cable other than the HDMI cable 40 or may be connected by a wireless communication network.

  The digital video recorder 30 includes an input unit 31, a decoder 32, a 3D image processing device 100B, and an HDMI communication unit 33.

  The input unit 31 acquires an encoded 3D image 51 recorded on the optical disc 41.

  The decoder 32 generates an input three-dimensional image 52 by decoding the encoded three-dimensional image 51 acquired by the input unit 31.

  The 3D image processing apparatus 100 </ b> B generates an output 3D image 53 by converting the format of the input 3D image 52.

  The HDMI communication unit 33 outputs the output 3D image 53 generated by the 3D image processing apparatus 100 </ b> B to the digital television 20 via the HDMI cable 40.

  The digital video recorder 30 may store the generated output 3D image 53 in a storage unit (such as a hard disk drive and a non-volatile memory) provided in the digital video recorder 30 or attach / detach to / from the digital video recorder 30. You may record on a possible recording medium (optical disc etc.).

  The digital television 20 includes an input unit 21, a decoder 22, an HDMI communication unit 23, a 3D image processing apparatus 100, a left screen drive unit 24L, a right screen drive unit 24R, a display panel 26, and a transmitter 27. Is provided.

  The input unit 21 acquires an encoded 3D image 55 included in the broadcast wave 42.

  The decoder 22 generates an input 3D image 56 by decoding the encoded 3D image 55 acquired by the input unit 21.

  The HDMI communication unit 23 acquires the output 3D image 53 output by the HDMI communication unit 33 and outputs it as an input 3D image 57.

  The 3D image processing apparatus 100 generates an output 3D image 58 by converting the format of the input 3D image 56 or the input 3D image 57. Here, the output three-dimensional image 58 includes a left screen image 58L and a right screen image 58R.

  The left screen drive unit 24L displays the left screen image 58L on the left screen 26L of the display panel 26. The right screen drive unit 24R displays the right screen image 58R on the right screen 26R of the display panel 26.

  The transmitter 27 controls the shutter glasses 43 using wireless communication.

  Hereinafter, the format conversion process by the 3D image processing apparatus 100 will be described. In the following, the format conversion process for the input three-dimensional image 56 by the three-dimensional image processing apparatus 100 will be described as an example. However, the format conversion process for the input three-dimensional image 57 by the three-dimensional image processing apparatus 100 and the third order The format conversion process for the input three-dimensional image 52 by the original image processing apparatus 100B is the same.

  Here, the format refers to the arrangement pattern of the left-eye image and the right-eye image in each frame (field) (hereinafter simply referred to as “arrangement pattern”), the frame rate, and the scanning method (progressive and interlaced). Race) and image size.

  That is, the 3D image processing apparatus 100 generates the output 3D image 58 by converting any one or more of the arrangement pattern, the frame rate, the scanning method, and the image size of the input 3D image 56.

  2A and 2B are diagrams illustrating an example of format conversion processing of the 3D image processing apparatus 100. FIG.

  For example, as shown in FIG. 2A, the input three-dimensional image 56 includes a left-eye image 56l and a right-eye image 56r in each field. The three-dimensional image processing apparatus 100 converts the arrangement pattern of the input three-dimensional image 56, whereby an output in which frames including only the left-eye image 58l and frames including only the right-eye image 58r are alternately arranged. A three-dimensional image 58 is generated.

  The three-dimensional image processing apparatus 100 converts the input three-dimensional image 56 of 60i (interlace method with a frame rate of 60 fps) into an output three-dimensional image 58 of 120 p (progressive method with a frame rate of 120 fps).

  The shutter glasses 43 are, for example, liquid crystal shutter glasses worn by a viewer, and include a left-eye liquid crystal shutter and a right-eye liquid crystal shutter. The transmitter 27 controls the opening and closing of the left-eye liquid crystal shutter and the right-eye liquid crystal shutter in accordance with the display timing of the left-eye image 58l and the right-eye image 58r. Specifically, the transmitter 27 opens the left-eye liquid crystal shutter of the shutter glasses 43 and closes the right-eye liquid crystal shutter during the period in which the left-eye image 58l is displayed. Further, the transmitter 27 closes the left-eye liquid crystal shutter of the shutter glasses 43 and opens the right-eye liquid crystal shutter during the period in which the right-eye image 58r is displayed. Thus, the left eye image 58l and the right eye image 58r are selectively incident on the viewer's left eye and the right eye, respectively.

  Note that the method of selectively causing the left-eye image 58l and the right-eye image 58r to enter the viewer's left eye and right eye is not limited to this method, and other methods may be used.

  For example, as shown in FIG. 2B, the input three-dimensional image 56 includes a left-eye image 56l and a right-eye image 56r in each field. The three-dimensional image processing apparatus 100B converts the arrangement pattern of the input three-dimensional image 52 into an output three-dimensional image 58 in which the left-eye image 58l and the right-eye image 58r are arranged in a checkered pattern in each frame. .

  In this case, the display panel 26 includes a left-eye polarizing film formed on the left-eye pixel and a right-eye polarizing film formed on the right-eye pixel. Different polarized light (linearly polarized light, circularly polarized light, or the like) is applied to 58l and the right-eye image 58r. Further, instead of the shutter glasses 43, by using polarized glasses having left-eye and right-eye polarization filters respectively corresponding to the polarized light, the left-eye image 58l and the left-eye and right-eye of the viewer are displayed. The right-eye image 58r can be made incident.

  In this case, the arrangement pattern of the output three-dimensional image 58 matches the arrangement pattern of the polarizing film.

  Note that the arrangement pattern of the input three-dimensional image 56 and the output three-dimensional image 58 may be any of the arrangement patterns shown below.

  3A, 3B, 4A, 4B, 5A, 5B, 6A, and 6B are diagrams showing arrangement patterns of three-dimensional images.

  In the arrangement pattern shown in FIG. 3A, the left-eye image 60l and the right-eye image 60r are arranged side by side in the vertical direction within one frame. Hereinafter, this arrangement pattern is referred to as a frame sequential.

  In the format shown in FIG. 3B, the left-eye image 60l and the right-eye image 60r are arranged side by side in a horizontal direction in one frame. Hereinafter, this arrangement pattern is called side-by-side.

  The example shown in FIGS. 3A and 3B shows an example of a so-called full high-definition image in which one frame is composed of pixels of 1920 columns × 1080 rows, but the number of pixels included in one frame is other than this number. There may be. For example, a so-called high-definition image in which one frame is composed of pixels of 1270 columns × 720 rows may be used.

  In the example shown in FIGS. 3A and 3B, each frame includes a left-eye image 60l and a right-eye image 60r that are each compressed in half in the vertical direction or the horizontal direction, but is not compressed. A left-eye image 60l and a right-eye image 60r each including 1920 columns × 1080 rows may be included. Moreover, it may be compressed at a compression rate other than 1/2, or may be compressed both in the vertical direction and in the horizontal direction.

  Further, the scanning method of the three-dimensional image may be a progressive method, or may be an interlace method in which a top field and a bottom field are alternately arranged.

  The frame rate of the three-dimensional image may be an arbitrary value.

  In the arrangement patterns shown in FIGS. 4A and 4B, the left-eye image 60l and the right-eye image 60r are arranged in a checkered pattern. Hereinafter, this arrangement pattern is referred to as a checker pattern. In FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, FIG. 6A and FIG. 6B, only the pixels of 10 columns × 6 rows are displayed for simplicity of explanation. A number of pixels are arranged.

  Also, the notations such as L0 and R1 shown in FIGS. 4A and 4B indicate the horizontal positions of the pixels of the left-eye image 60l and the right-eye image 60r. That is, the pixel L0 is the pixel in the 0th column of the left eye image 60l, and the pixel R1 is the pixel in the 1st column of the right eye image 60r.

  Note that the left-eye image 60l and the right-eye image 60r may be arranged in a checkered pattern in units of one pixel, or a checkered pattern having a plurality of pixel units, for example, a group of 2 columns × 2 rows of pixels as one unit. It may be arranged in a shape.

  In the arrangement patterns shown in FIGS. 5A and 5B, the left-eye image 60l and the right-eye image 60r are arranged in a vertical stripe shape. Hereinafter, this arrangement pattern is referred to as vertical interleaving. Note that the notations such as L0 and R1 shown in FIGS. 5A and 5B indicate the horizontal positions of the pixels of the left-eye image 60l and the right-eye image 60r. That is, the pixel L0 is the pixel in the 0th column of the left eye image 60l, and the pixel R1 is the pixel in the 1st column of the right eye image 60r.

  Note that the left-eye image 60l and the right-eye image 60r may be alternately arranged for each column, or may be alternately arranged for each of a plurality of columns.

  In the arrangement pattern shown in FIGS. 6A and 6B, the left-eye image 60l and the right-eye image 60r are arranged in a horizontal stripe shape. Hereinafter, this arrangement pattern is referred to as line sequential. Note that the notations such as L0 and R1 shown in FIGS. 6A and 6B indicate the positions of the pixels of the left-eye image 60l and the right-eye image 60r in the vertical direction. That is, the pixel L0 is the pixel in the 0th row of the left eye image 60l, and the pixel R1 is the pixel in the 1st row of the right eye image 60r.

  Note that the left-eye image 60l and the right-eye image 60r may be alternately arranged for each row, or may be alternately arranged for every plurality of rows.

  2A to 6B, the left eye image and the right eye image may be arranged in reverse.

  FIG. 7 is a diagram illustrating an example of the left-eye image 58l and the right-eye image 58r.

  As shown in FIG. 7, the objects included in the left-eye image 58l and the right-eye image 58r have parallax according to the distance of the object from the shooting position.

  In the 3D image processing apparatus 100B included in the digital video recorder 30, when the format conversion is performed, for example, the 3D image processing apparatus 100B changes the arrangement pattern of the input 3D image 52 as shown in FIG. 2B. The data is converted into a predetermined arrangement pattern (for example, a checker pattern) and converted into 120p. In this case, the three-dimensional image processing apparatus 100 included in the digital television 20 converts the arrangement pattern of the 120p input three-dimensional image 57 (for example, the left-eye image 58l and the right-eye image 58r are alternately arranged. Only conversion).

  Note that the 3D image processing apparatus 100B performs the format conversion shown in FIG. 2A, and the 3D image processing apparatus 100 may not perform the format conversion. The 3D image processing apparatus 100B may perform a part of the conversion of the arrangement pattern, the frame rate, the scanning method, and the image size, and the 3D image processing apparatus 100 may perform conversions other than the part. . Moreover, a part of process of the three-dimensional image processing apparatus 100 and the three-dimensional image processing apparatus 100B may overlap.

  Hereinafter, the three-dimensional image processing apparatus 100 will be described in detail.

  The three-dimensional image processing apparatus 100 is a composite image including two main screen images (corresponding to the first image of the present invention) and sub-screen images (corresponding to the second image of the present invention) as two two-dimensional images in one screen. And the three-dimensional image processing mode for converting the input three-dimensional image 56 or 57 in the first format into the output three-dimensional image 58 in the second format as described above.

  First, an outline of the operation of the 3D image processing apparatus 100 in the two-screen processing mode will be described.

  FIG. 8 is a diagram illustrating an operation example in the two-screen processing mode by the 3D image processing apparatus 100.

  As shown in FIG. 8, in the two-screen processing mode, the 3D image processing apparatus 100 generates a composite image in which a reduced sub-screen is placed on the main screen. Details of the operation in the two-screen processing mode will be described later.

  Next, the configuration of the 3D image processing apparatus 100 will be described.

  FIG. 9 is a block diagram illustrating a configuration of the 3D image processing apparatus 100.

  As illustrated in FIG. 9, the 3D image processing apparatus 100 includes an input selection unit 101, a main screen image processing unit 102, a sub screen image processing unit 103, a synthesis unit 104, and an output unit 105.

  In the two-screen processing mode, the input selection unit 101 outputs the main screen image 110 to the main screen image processing unit 102 and outputs the sub screen image 111 to the sub screen image processing unit 103.

  In the 3D image processing mode, the input selection unit 101 converts the 3D image 112 into the left screen input image 112L (corresponding to the first input image of the present invention) and the right screen input image 112R (second input image of the present invention). The left screen input image 112L is output to the main screen image processing unit 102, and the right screen input image 112R is output to the sub screen image processing unit 103.

  Note that, in the 3D image processing mode, the input selection unit 101 outputs the 3D image 112 to the main screen image processing unit 102 and the sub screen image processing unit 103, respectively, and the main screen image processing unit 102 outputs the 3D image 112 from the 3D image 112. The left screen input image 112L may be extracted, and the sub screen image processing unit 103 may extract the right screen input image 112R from the three-dimensional image 112.

  Here, the main screen image 110 and the sub screen image 111 are different two-dimensional images. For example, the main screen image 110 and the sub screen image 111 are an image of the first channel included in the broadcast wave 42, an image of the second channel included in the broadcast wave 42, and an image acquired by the HDMI communication unit 23. Two of them are images.

  The three-dimensional image 112 is the input three-dimensional image 56 or 57 described above. Further, for example, the left screen input image 112L is an image of the left half of the 3D image 112, and the right screen input image 112R is an image of the right half of the 3D image 112.

  In the two-screen processing mode, the main screen image processing unit 102 (corresponding to the first image processing unit of the present invention) converts the format of the main screen image 110 output by the input selection unit 101 to thereby convert the main screen processed image 150. (Corresponding to the first processed image of the present invention) is generated. In the 3D image processing mode, the main screen image processing unit 102 converts the format of the left screen input image 112L output by the input selection unit 101, thereby converting the left screen output image 153L (first output image of the present invention). Equivalent).

  In the two-screen processing mode, the sub-screen image processing unit 103 (corresponding to the second image processing unit of the present invention) converts the format of the sub-screen image 111 output by the input selection unit 101, thereby sub-screen processing image 151. (Corresponding to the second processed image of the present invention) is generated. Further, in the 3D image processing mode, the sub-screen image processing unit 103 converts the format of the right screen input image 112R output by the input selection unit 101, thereby converting the right screen output image 153R (second output image of the present invention). Equivalent).

  The combining unit 104 generates a composite image 152 by combining the main screen processed image 150 generated by the main screen image processing unit 102 and the sub screen processed image 151 generated by the sub screen image processing unit 103. .

  In the two-screen processing mode, the output unit 105 divides the composite image 152 generated by the combining unit 104 into a left screen image 58L and a right screen image 58R. The output unit 105 outputs the divided left screen image 58L to the left screen drive unit 24L, and outputs the divided right screen image 58R to the right screen drive unit 24R.

  In the three-dimensional image processing mode, the output unit 105 outputs the left screen output image 153L generated by the main screen image processing unit 102 as the left screen image 58L to the left screen driving unit 24L, and the sub screen image processing unit 103. The right screen output image 153R generated by the above is output as the right screen image 58R to the right screen drive unit 24R.

  Hereinafter, detailed configurations of the main screen image processing unit 102 and the sub screen image processing unit 103 will be described.

  FIG. 10 is a block diagram illustrating the configuration of the main screen image processing unit 102 and the sub screen image processing unit 103.

  As shown in FIG. 10, the main screen image processing unit 102 includes a main screen preprocessing unit 120 and a main screen postprocessing unit 121. The 3D image processing apparatus 100 further includes a memory 140 and a memory controller 141.

  The main screen pre-processing unit 120 (corresponding to the first pre-processing unit of the present invention) reduces the image size of the main screen image 110 or the left screen input image 112L and converts the scanning method, thereby converting the left screen processed image. 160L (corresponding to the third processed image of the present invention) is generated. The main screen preprocessing unit 120 includes a horizontal reduction unit 122, an IP conversion unit 123, and a vertical reduction unit 124.

  The horizontal reduction unit 122 reduces and outputs the horizontal image size of the main screen image 110 or the left screen input image 112L.

  The IP conversion unit 123 converts the scanning method of the image output from the horizontal reduction unit 122 from an interlace method to a progressive method (hereinafter referred to as “IP conversion”) and outputs the converted image. Here, the IP conversion is a process of interpolating pixels in a nonexistent row in an interlaced image. For example, in the IP conversion, pixels in a non-existing row are interpolated using pixels around the same field, or the same or surrounding pixels in a field having a different field determination signal immediately or immediately after. Also, which pixel is used for interpolation is determined according to the motion of the image. The field determination signal is a signal indicating whether the field is a top field or a bottom field.

  The vertical reduction unit 124 generates and outputs a left screen processed image 160L by reducing the image size in the vertical direction of the image output by the IP conversion unit 123.

  As a method for reducing the image size, a method of thinning out pixels or a method of calculating an average value of a plurality of pixels can be used.

  Note that the processing order by the horizontal reduction unit 122, the IP conversion unit 123, and the vertical reduction unit 124 illustrated in FIG. 10 is an example, and the processing by each processing unit may be performed in an arbitrary order.

  The memory controller 141 writes and reads data 149 to and from the memory.

  Further, the main screen preprocessing unit 120 stores the generated left screen processed image 160 </ b> L in the memory 140 via the memory controller 141.

  The main screen post-processing unit 121 (corresponding to the first post-processing unit of the present invention) includes at least one of the left screen processed image 160L and the right screen processed image 160R stored in the memory 140 via the memory controller 141. The left screen processed image 161L (corresponding to the fifth processed image of the present invention) is read. Specifically, the left screen processed image 161L includes pixels corresponding to the left screen 26L of the display panel 26 among the pixels included in the left screen processed image 160L and the right screen processed image 160R stored in the memory 140. .

  The main screen post-processing unit 121 generates the main screen processed image 150 or the left screen output image 153L by increasing the image size of the left screen processed image 161L and converting the arrangement pattern and the frame rate. The main screen post-processing unit 121 includes a pattern conversion unit 125, a vertical enlargement unit 126, and a horizontal enlargement unit 127.

  The pattern conversion unit 125 converts and outputs the arrangement pattern and frame rate of the left screen processed image 161L. The pattern conversion unit 125 may convert the arrangement pattern and the frame rate after reading the left screen processed image 161L, or read the pixels by reading out the left screen processed image 161L in the arrangement order. At the same time, pattern conversion and frame rate conversion may be performed.

  The vertical enlargement unit 126 enlarges and outputs the image size in the vertical direction of the image output by the pattern conversion unit 125.

  The horizontal enlargement unit 127 enlarges and outputs the image size in the horizontal direction of the image output by the vertical enlargement unit 126.

  As a method for enlarging the image size, a method of simply copying pixels, a method of interpolating nonexistent pixels, or the like can be used.

  Note that the order of processing by the pattern conversion unit 125, the vertical enlargement unit 126, and the horizontal enlargement unit 127 illustrated in FIG. 10 is an example, and the processing by each processing unit may be performed in an arbitrary order.

  Next, the configuration of the sub-screen image processing unit 103 will be described. Note that the configuration of the sub-screen image processing unit 103 is the same as that of the main screen image processing unit 102.

  Specifically, as shown in FIG. 10, the sub screen image processing unit 103 includes a sub screen preprocessing unit 130 and a sub screen post processing unit 131.

  The sub-screen pre-processing unit 130 (corresponding to the second pre-processing unit of the present invention) reduces the image size of the sub-screen image 111 or the right screen input image 112R and performs IP conversion so that the right screen processed image 160R ( Corresponding to the fourth processed image of the present invention). The sub-screen preprocessing unit 130 includes a horizontal reduction unit 132, an IP conversion unit 133, and a vertical reduction unit 134.

  The horizontal reduction unit 132 reduces and outputs the horizontal image size of the sub-screen image 111 or the right screen input image 112R.

  The IP conversion unit 133 performs IP conversion on the image output by the horizontal reduction unit 132 and outputs the image.

  The vertical reduction unit 134 generates and outputs a right screen processed image 160R by reducing the image size in the vertical direction of the image output by the IP conversion unit 133.

  Note that the order of processing by the horizontal reduction unit 132, the IP conversion unit 133, and the vertical reduction unit 134 illustrated in FIG. 10 is an example, and the processing by each processing unit may be performed in an arbitrary order.

  In addition, the sub-screen preprocessing unit 130 stores the generated right screen processed image 160R in the memory 140 via the memory controller 141.

  The sub-screen post-processing unit 131 (corresponding to the second post-processing unit of the present invention) includes at least one of the left screen processed image 160L and the right screen processed image 160R stored in the memory 140 via the memory controller 141. The right screen processed image 161R (corresponding to the sixth processed image of the present invention) is read. Specifically, the right screen processed image 161R is the right screen output image 153R (the right screen 26R of the display panel 26) among the pixels included in the left screen processed image 160L and the right screen processed image 160R stored in the memory 140. ).

  Further, the sub screen post-processing unit 131 generates the sub screen processed image 151 or the right screen output image 153R by enlarging the image size of the right screen processed image 160R and converting the arrangement pattern and the frame rate. The sub-screen post-processing unit 131 includes a pattern conversion unit 135, a vertical enlargement unit 136, and a horizontal enlargement unit 137.

  The pattern conversion unit 135 converts and outputs the arrangement pattern and frame rate of the right screen processed image 161R. The pattern conversion unit 135 may convert the arrangement pattern and the frame rate after reading out the right screen processed image 161R, or read out the pixels by reading out the right screen processed image 161R in the arrangement order. At the same time, pattern conversion and frame rate conversion may be performed.

  The vertical enlargement unit 136 enlarges and outputs the image size in the vertical direction of the image output by the pattern conversion unit 135.

  The horizontal enlargement unit 137 enlarges and outputs the image size in the horizontal direction of the image output by the vertical enlargement unit 136.

  Note that the order of processing by the pattern conversion unit 135, the vertical enlargement unit 136, and the horizontal enlargement unit 137 shown in FIG. 10 is an example, and the processing by each processing unit may be performed in an arbitrary order.

  Hereinafter, an operation example of the 3D image processing apparatus 100 configured as described above will be described.

  First, an operation example of the 3D image processing apparatus 100 in the two-screen processing mode will be described.

  Here, as shown in FIG. 8, it is assumed that the main screen image 110 and the sub screen image 111 are 480i and the frame rate is 60 fps.

  First, the input selection unit 101 outputs the main screen image 110 to the main screen image processing unit 102 and outputs the sub screen image 111 to the sub screen image processing unit 103.

  Next, the main screen image processing unit 102 performs IP conversion of the main screen image 110 and expands the image size from high definition to full high definition to generate a main screen processed image 150 of 1080p and 60 fps.

  Specifically, the IP conversion unit 123 generates a 720p and 60 fps converted image by performing IP conversion on the main screen image 110. Next, the vertical enlargement unit 126 and the horizontal enlargement unit 127 generate the 1080p and 60 fps main screen processed image 150 by enlarging the converted image.

  On the other hand, the sub-screen image processing unit 103 converts the scanning method of the sub-screen image 111 from the interlace method to the progressive method and reduces the image size to generate, for example, a sub-screen processed image 151 of 400 p and 60 fps. To do.

  Specifically, the horizontal reduction unit 132 reduces the horizontal image size of the sub-screen image 111, and the IP conversion unit 133 converts the reduced image scanning method from the interlace method to the progressive method. , 720p and 60 fps converted images are generated. Next, the vertical reduction unit 134 generates a 400p and 60 fps sub-screen processed image 151 by reducing the vertical image size of the converted image.

  Next, the synthesizing unit 104 synthesizes the main screen processed image 150 generated by the main screen image processing unit 102 and the sub-screen processed image 151 generated by the sub-screen image processing unit 103, thereby 1080p and 60fps. The composite image 152 is generated.

  Next, the output unit 105 divides the combined image 152 generated by the combining unit 104 into a left screen image 58L and a right screen image 58R. The output unit 105 outputs the divided left screen image 58L to the left screen drive unit 24L, and outputs the divided right screen image 58R to the right screen drive unit 24R.

  As described above, the 3D image processing apparatus 100 can generate a composite image in which the reduced sub-screen is displayed on the main screen.

  If the image size of the input main screen image 110 is larger than the image size that can be displayed on the display panel 26 (hereinafter referred to as display image size), the main screen image processing unit 102 performs image size reduction processing. Is called.

  In addition, here, an example of generating a composite image in which a sub screen is superimposed on a main screen has been described. However, one screen is divided into two sub screens, and the main screen and the sub screen are arranged on each sub screen. A composite image may be generated.

  In this case, when the main screen image 110 is larger than the size of the sub screen, the main screen image processing unit 102 performs image size reduction processing. In the two-screen processing mode, the 3D image processing apparatus 100 generates a composite image in which the main screen and the sub screen are arranged on the divided sub screen instead of generating a composite image in which the sub screen is superimposed on the main screen. Or a mode for generating a composite image in which the sub screen is superimposed on the main screen, and a mode for generating a composite image in which the main screen and the sub screen are arranged on the divided sub screen. Good.

  Further, regardless of the image size of the main screen image 110 and the display image size of the display panel 26, the main screen preprocessing unit 120 once reduces the image size of the main screen image 110, and then the main screen postprocessing unit 121. However, the image size may be increased so that the reduced image size is restored to the original image size. For example, when the image size of the main screen image 110 matches the display image size of the display panel 26 (when it is not necessary to reduce and enlarge the image size), the main screen preprocessing unit 120 sets the image size of the main screen image 110. May be reduced to ½ in the vertical direction, and the main screen post-processing unit 121 may enlarge the reduced image size twice in the vertical direction.

  Thereby, since the amount of data stored in the memory 140 can be reduced, the capacity of the memory 140 can be reduced. Furthermore, the processing amount in the IP conversion unit 123, the pattern conversion unit 125, and the like can be reduced.

  Note that in the sub-screen image processing unit 103 as well as the main screen image processing unit 102, the sub-screen pre-processing unit 130 once sets the sub-screen image 111 and the display image size of the display panel 26 regardless of the image size. After reducing the image size of the sub-screen image 111, the sub-screen post-processing unit 131 may enlarge the image size so that the reduced image size is restored to the original image size.

  Further, the main screen image processing unit 102 and the sub screen image processing unit 103 may perform processing for increasing or decreasing the frame rate.

  In addition to the two-screen processing mode and the three-dimensional image processing mode, the three-dimensional image processing apparatus 100 has a normal mode that displays only one normal image on one screen. In the normal mode, the main screen image processing unit 102 performs format conversion of the one image.

  Next, an operation example of the 3D image processing apparatus 100 in the 3D image processing mode will be described.

  FIGS. 11-16 is a figure which shows the operation example at the time of the three-dimensional image processing mode by the three-dimensional image processing apparatus 100. FIG.

  Here, in the example shown in FIG. 11, the three-dimensional image 112 is a full-size 1080i frame sequential and 60 fps image. That is, the three-dimensional image 112 includes a left eye image 60l of 1080i (1920 columns × 540 rows) and a right eye image 60r of 1080i (1920 columns × 540 rows) in one field.

  That is, the dot clock of the three-dimensional image 112 is 148.5 MHz. Here, the dot clock is a value represented by the product of the image size (number of rows × number of columns) and the frame rate. That is, the higher the dot clock, the shorter the time that can be used for processing one pixel, in other words, the larger the amount of data to be processed per unit time.

  The display panel 26 displays a 1080p and 120 fps image in which the left-eye image 60l and the right-eye image 60r are alternately arranged.

  In this case, first, the input selection unit 101 divides the three-dimensional image 112 into a left screen input image 112L and a right screen input image 112R, and outputs the left screen input image 112L to the main screen image processing unit 102. The input image 112R is output to the sub-screen image processing unit 103.

  Here, the left screen input image 112L and the right screen input image 112R are half the image size of the three-dimensional image 112. Therefore, the dot clock of the left screen input image 112L and the right screen input image 112R is 74.25 MHz which is half of the dot clock of the three-dimensional image 112.

  Specifically, the left screen input image 112L includes a left eye image 60l of 1080i / 2 (960 columns × 540 rows) and a right eye image 60r of 1080i / 2 (960 columns × 540 rows) in one field. including. The right screen input image 112R includes a left eye image 60l of 1080i / 2 (960 columns × 540 rows) and a right eye image 60r of 1080i / 2 (960 columns × 540 rows) in one field.

  That is, the image sizes of the left screen input image 112L and the right screen input image 112R are 960 columns × 1080 rows, respectively.

  Next, the main screen preprocessing unit 120 performs I / P conversion on the left screen input image 112L to generate a left screen processed image 160L of 1080p and 60 fps. This I / P conversion doubles the vertical image size. Therefore, the dot clock of the left screen processed image 160L is 148.5 MHz, which is twice that of the left screen input image 112L.

  Specifically, the left screen processed image 160L includes a left-eye image 60l of 1080p / 2 (960 columns × 1080 rows) and a right-eye image 60r of 1080p / 2 (960 columns × 1080 rows) per frame. including. Therefore, the image size of the left screen processed image 160L is 960 columns × 2160L rows.

  Next, the main screen preprocessing unit 120 stores the left screen processed image 160 </ b> L in the memory 140 via the memory controller 141.

  Next, the main screen post-processing unit 121 reads the left screen processed image 160L via the memory controller 141. At this time, the main screen post-processing unit 121 performs 1080p / 2 (960) in which the left-eye image 60l and the right-eye image 60r are alternately arranged by performing pattern conversion and double speeding of the left-screen processed image 160L. Column x 1080 rows) and 120 fps left screen output image 153L is generated. By this pattern conversion, the image size is halved, and by double speed, the frame rate is doubled. Therefore, the dot clock of the left screen output image 153L is 148.5 MHz, which is the same as the dot clock of the left screen processed image 160L.

  On the other hand, the sub-screen image processing unit 103 performs the same processing as the main screen image processing unit 102 on the right screen input image 112R.

  Specifically, the sub-screen pre-processing unit 130 generates a 1080p and 60 fps right-screen processed image 160R by performing I / P conversion on the right-screen input image 112R. This I / P conversion doubles the vertical image size. Therefore, the dot clock of the right screen processed image 160R is 148.5 MHz, which is twice that of the right screen input image 112R.

  Specifically, the right screen processed image 160R includes a left-eye image 60l of 1080p / 2 (960 columns × 1080 rows) and a right-eye image 60r of 1080p / 2 (960 columns × 1080 rows) per frame. including. Therefore, the image size of the right screen processed image 160R is 960 columns × 2160 L rows.

  Next, the sub-screen preprocessing unit 130 stores the right screen processed image 160R in the memory 140 via the memory controller 141.

  Next, the sub-screen post-processing unit 131 reads the right-screen processed image 160R via the memory controller 141. At this time, the sub-screen post-processing unit 131 performs 1080p / 2 (960) in which the left-eye image 60l and the right-eye image 60r are alternately arranged by performing pattern conversion and double speeding of the right-screen processed image 160R. Column × 1080 rows) and 120 fps right screen output image 153R. By this pattern conversion, the image size is halved, and by double speed, the frame rate is doubled. Therefore, the dot clock of the right screen output image 153R is 148.5 MHz, which is the same as the dot clock of the right screen processed image 160R.

  Next, the output unit 105 outputs the left screen output image 153L generated by the main screen image processing unit 102 to the left screen drive unit 24L as the left screen image 58L, and the right screen generated by the sub screen image processing unit 103. The output image 153R is output to the right screen drive unit 24R as the right screen image 58R.

  Next, the left screen drive unit 24L displays the left screen image 58L on the left screen 26L of the display panel 26. The right screen drive unit 24R displays the right screen image 58R on the right screen 26R of the display panel 26.

  As described above, a total of 1080p and 120 fps images including the left screen image 58L and the right screen image 58R are displayed on the display panel 26. That is, the dot clock of the image displayed on the display panel 26 is 297 MHz.

  As described above, in the three-dimensional image processing apparatus 100 according to Embodiment 1 of the present invention, the main screen image processing unit 102 and the sub screen image processing unit 103 each process an image with a maximum dot clock of 148 and 5 MHz. Thus, an image with a dot clock of 297 MHz can be generated.

  Next, an operation example when the three-dimensional image 112 is a 720p image will be described with reference to FIG.

  Specifically, in the example illustrated in FIG. 12, the three-dimensional image 112 is a full-size 720p frame sequential and 60 fps image. That is, the 3D image 112 includes a left-eye image 60l of 720p (1270 columns × 720 rows) and a right-eye image 60r of 720p (1270 columns × 720 rows) in one frame. That is, the dot clock of the three-dimensional image 112 is 148.5 MHz.

  The display panel 26 displays a 1080p and 120 fps image in which the left-eye image 60l and the right-eye image 60r are alternately arranged.

  In this case, first, the input selection unit 101 divides the three-dimensional image 112 into a left screen input image 112L and a right screen input image 112R, and outputs the left screen input image 112L to the main screen image processing unit 102. The input image 112R is output to the sub-screen image processing unit 103.

  Here, the left screen input image 112L and the right screen input image 112R are half the image size of the three-dimensional image 112. Therefore, the dot clock of the left screen input image 112L and the right screen input image 112R is 74.25 MHz which is half of the dot clock of the three-dimensional image 112.

  Specifically, the left screen input image 112L includes a left-eye image 60l of 720p / 2 (635 columns × 720 rows) and a right-eye image 60r of 720p / 2 (635 columns × 720 rows) per frame. including. The right screen input image 112R includes a left-eye image 60l of 720p / 2 (635 columns × 720 rows) and a right-eye image 60r of 720p / 2 (635 columns × 720 rows) in one frame.

  That is, the image sizes of the left screen input image 112L and the right screen input image 112R are 635 columns × 1440 rows, respectively.

  Next, the main screen preprocessing unit 120 stores the left screen input image 112L (left screen processed image 160L) in the memory 140 via the memory controller 141.

  Next, the main screen post-processing unit 121 reads the left screen processed image 160L via the memory controller 141. At this time, the main screen post-processing unit 121 performs pattern conversion and double speeding of the left screen processed image 160L, so that the left eye image 60l and the right eye image 60r are alternately arranged 720p / 2 (635 Column 720 rows) and 120 fps left screen processed image 163L is generated. By this pattern conversion, the image size is halved, and by double speed, the frame rate is doubled. Therefore, the dot clock of the left screen processed image 163L is 74.25 MHz, which is the same as the dot clock of the left screen processed image 160L.

  Next, the main screen post-processing unit 121 enlarges the image size of the left screen processed image 163L to thereby arrange 1080p / 2 (960 rows × 960 images) in which the left eye image 60l and the right eye image 60r are alternately arranged. 1080 line) and 120 fps left screen output image 153L. This enlargement process doubles the image size. Therefore, the dot clock of the left screen output image 153L is 148.5 MHz, which is twice the dot clock of the left screen processed image 163L.

  On the other hand, as with the main screen image processing unit 102, the sub-screen image processing unit 103 performs pattern conversion and double speed conversion of the right screen processed image 160R so that the left-eye image 60l and the right-eye image 60r alternate. 720p / 2 (635 columns × 720 rows) and 120 fps right screen processed image 163R are generated. Next, the sub-screen post-processing unit 131 generates a right screen output image 153R of 1080p / 2 (960 columns × 1080 rows) and 120 fps by enlarging the image size of the right screen processed image 163R.

  Next, the output unit 105 outputs the left screen output image 153L generated by the main screen image processing unit 102 to the left screen drive unit 24L as the left screen image 58L, and the right screen generated by the sub screen image processing unit 103. The output image 153R is output to the right screen drive unit 24R as the right screen image 58R.

  Next, the left screen drive unit 24L displays the left screen image 58L on the left screen 26L of the display panel 26. The right screen drive unit 24R displays the right screen image 58R on the right screen 26R of the display panel 26.

  As described above, a total of 1080p and 120 fps images including the left screen image 58L and the right screen image 58R are displayed on the display panel 26. That is, the dot clock of the image displayed on the display panel 26 is 297 MHz.

  Next, an operation example when the arrangement pattern of the three-dimensional image 112 is side-by-side will be described with reference to FIGS. 13 and 14.

  The operation example shown in FIGS. 13 and 14 is mainly different from the operation example shown in FIGS. 11 and 12 described above in the following points. 13 and 14, the main screen post-processing unit 121 cannot generate the left screen output image 153L from only the left screen processed image 160L generated by the main screen pre-processing unit 120. Therefore, the main screen post-processing unit 121 uses the left screen processed image 160L generated by the main screen pre-processing unit 120 and the right screen processed image 160R generated by the sub-screen pre-processing unit 130 to output the left screen. An image 153L is generated.

  Similarly, the sub screen post-processing unit 131 cannot generate the right screen output image 153R only from the right screen processed image 160R generated by the sub screen pre-processing unit 130. Therefore, the sub-screen post-processing unit 131 uses the left-screen processed image 160L generated by the main-screen pre-processing unit 120 and the right-screen processed image 160R generated by the sub-screen pre-processing unit 130 to output the right screen. An image 153R is generated.

  Specifically, in the example illustrated in FIG. 13, the three-dimensional image 112 is a full-size 1080i side-by-side and 60 fps image. That is, the three-dimensional image 112 includes a left eye image 60l of 1080i (1920 columns × 540 rows) and a right eye image 60r of 1080i (1920 columns × 540 rows) in one field. That is, the dot clock of the three-dimensional image 112 is 148.5 MHz.

  The display panel 26 displays a 1080p and 120 fps image in which the left-eye image 60l and the right-eye image 60r are alternately arranged.

  In this case, first, the input selection unit 101 divides the three-dimensional image 112 into a left screen input image 112L and a right screen input image 112R, and outputs the left screen input image 112L to the main screen image processing unit 102. The input image 112R is output to the sub-screen image processing unit 103.

  Here, the left screen input image 112L and the right screen input image 112R are half the image size of the three-dimensional image 112. Therefore, the dot clock of the left screen input image 112L and the right screen input image 112R is 74.25 MHz which is half of the dot clock of the three-dimensional image 112.

  Specifically, the left screen input image 112L includes a left-eye image 60l of 1080i (1920 columns × 540 rows) in one field. Further, the right screen input image 112R includes a 1080i (1920 columns × 540 rows) right-eye image 60r in one field. That is, the image sizes of the left screen input image 112L and the right screen input image 112R are 1920 columns × 540 rows, respectively.

  Next, the main screen preprocessing unit 120 performs I / P conversion on the left screen input image 112L to generate a left screen processed image 160L of 1080p and 60 fps. This I / P conversion doubles the vertical image size. Therefore, the dot clock of the left screen processed image 160L is 148.5 MHz, which is twice that of the left screen input image 112L.

  Specifically, the left screen processed image 160L includes a left-eye image 60l of 1080p (1920 columns × 1080 rows) in one frame. Therefore, the image size of the left screen processed image 160L is 1920 columns × 1080 rows.

  Next, the main screen preprocessing unit 120 stores the left screen processed image 160 </ b> L in the memory 140 via the memory controller 141.

  On the other hand, the sub-screen preprocessing unit 130 generates a 1080p and 60 fps right screen processed image 160R by performing I / P conversion on the right screen input image 112R. This I / P conversion doubles the vertical image size. Therefore, the dot clock of the right screen processed image 160R is 148.5 MHz, which is twice that of the right screen input image 112R.

  Specifically, the right screen processed image 160R includes a right eye image 60r of 1080p (1920 columns × 1080 rows) in one frame. Therefore, the image size of the right screen processed image 160R is 1920 columns × 1080 rows.

  Next, the sub-screen preprocessing unit 130 stores the right screen processed image 160R in the memory 140 via the memory controller 141.

  Next, the main screen post-processing unit 121 via the memory controller 141, among the plurality of pixels included in the left screen processed image 160L and the right screen processed image 160R, a plurality of pixels corresponding to the left screen 26L of the display panel 26. A left screen processed image 161L including pixels is read out. Also, the main screen post-processing unit 121 performs 1080p / 2 (960 columns) in which the left-eye image 60l and the right-eye image 60r are alternately arranged by performing pattern conversion and double speeding of the left-screen processed image 161L. × 1080 lines) and a left screen output image 153L of 120 fps is generated.

  Specifically, the main screen post-processing unit 121 reads the left half of the left screen processed image 160L and the left half of the right screen processed image 160R, and also reads the left half of the read left screen processed image 160L and the right screen processed image 160R. The left screen output image 153L is generated by alternately arranging the left half of the left screen.

  By this pattern conversion, the image size is halved, and by double speed, the frame rate is doubled. Therefore, the dot clock of the left screen output image 153L is 148.5 MHz, which is the same as the dot clock of the left screen processed image 160L.

  On the other hand, similarly to the main screen post-processing unit 121, the sub-screen post-processing unit 131 is connected to the display panel 26 among a plurality of pixels included in the left screen processed image 160L and the right screen processed image 160R via the memory controller 141. A right screen processed image 161R including a plurality of pixels corresponding to the right screen 26R is read out. Further, the sub-screen post-processing unit 131 performs 1080p / 2 (960 columns) in which the left-eye image 60l and the right-eye image 60r are alternately arranged by performing pattern conversion and double speeding of the right-screen processed image 161R. X 1080 lines) and 120 fps right screen output image 153R is generated.

  Specifically, the sub-screen post-processing unit 131 reads the right half of the left screen processed image 160L and the right half of the right screen processed image 160R, and the right half of the read left screen processed image 160L and the right screen processed image 160R. The right screen output image 153R is generated by alternately arranging the right half of the right screen.

  By this pattern conversion, the image size is halved, and by double speed, the frame rate is doubled. Therefore, the dot clock of the right screen output image 153R is 148.5 MHz, which is the same as the dot clock of the left screen processed image 160L.

  Next, the output unit 105 outputs the left screen output image 153L generated by the main screen image processing unit 102 to the left screen drive unit 24L as the left screen image 58L, and the right screen generated by the sub screen image processing unit 103. The output image 153R is output to the right screen drive unit 24R as the right screen image 58R.

  Next, the left screen drive unit 24L displays the left screen image 58L on the left screen 26L of the display panel 26. The right screen drive unit 24R displays the right screen image 58R on the right screen 26R of the display panel 26.

  As described above, a total of 1080p and 120 fps images including the left screen image 58L and the right screen image 58R are displayed on the display panel 26. That is, the dot clock of the image displayed on the display panel 26 is 297 MHz.

  Next, an operation example shown in FIG. 14 will be described.

  Here, in the example illustrated in FIG. 14, the three-dimensional image 112 is a full-size 720p side-by-side and 60 fps image. That is, the 3D image 112 includes a left-eye image 60l of 720p (1270 columns × 720 rows) and a right-eye image 60r of 720p (1270 columns × 720 rows) in one frame. That is, the dot clock of the three-dimensional image 112 is 148.5 MHz.

  The display panel 26 displays a 1080p and 120 fps image in which the left-eye image 60l and the right-eye image 60r are alternately arranged.

  In this case, first, the input selection unit 101 divides the three-dimensional image 112 into a left screen input image 112L and a right screen input image 112R, and outputs the left screen input image 112L to the main screen image processing unit 102. The input image 112R is output to the sub-screen image processing unit 103.

  Here, the left screen input image 112L and the right screen input image 112R are half the image size of the three-dimensional image 112. Therefore, the dot clock of the left screen input image 112L and the right screen input image 112R is 74.25 MHz which is half of the dot clock of the three-dimensional image 112.

  Specifically, the left screen input image 112L includes a left-eye image 60l of 720p (1270 columns × 720 rows) in one frame. The right screen input image 112R includes a right-eye image 60r of 720p (1270 columns × 720 rows) in one frame. That is, the image sizes of the left screen input image 112L and the right screen input image 112R are 1270 columns × 720 rows, respectively.

  Next, the main screen preprocessing unit 120 stores the left screen input image 112L (left screen processed image 160L) in the memory 140 via the memory controller 141.

  On the other hand, the sub-screen preprocessing unit 130 stores the right screen input image 112 </ b> R (right screen processed image 160 </ b> R) in the memory 140 via the memory controller 141.

  Next, the main screen post-processing unit 121 via the memory controller 141, among the plurality of pixels included in the left screen processed image 160L and the right screen processed image 160R, a plurality of pixels corresponding to the left screen 26L of the display panel 26. A left screen processed image 161L including pixels is read out. Further, the main screen post-processing unit 121 performs pattern conversion and double speed conversion of the left screen processed image 161L, thereby 720p / 2 (635 columns) in which the left eye image 60l and the right eye image 60r are alternately arranged. × 720 lines) and 120 fps left screen processed image 163L is generated.

  Specifically, the main screen post-processing unit 121 reads the left half of the left screen processed image 160L and the left half of the right screen processed image 160R, and also reads the left half of the read left screen processed image 160L and the right screen processed image 160R. The left screen output image 153L is generated by alternately arranging the left half of the left screen.

  By this pattern conversion, the image size is halved, and by double speed, the frame rate is doubled. Therefore, the dot clock of the left screen processed image 163L is 74.25 MHz, which is the same as the dot clock of the left screen processed image 160L.

  Next, the main screen post-processing unit 121 enlarges the image size of the left screen processed image 163L to thereby arrange 1080p / 2 (960 rows × 960 images) in which the left eye image 60l and the right eye image 60r are alternately arranged. 1080 line) and 120 fps left screen output image 153L. This enlargement process doubles the image size. Therefore, the dot clock of the left screen output image 153L is 148.5 MHz, which is twice the dot clock of the left screen processed image 163L.

  On the other hand, the sub-screen post-processing unit 131 performs the same processing as the main-screen post-processing unit 121, whereby 1080p / 2 (960 rows × 960) in which the left-eye image 60l and the right-eye image 60r are alternately arranged. 1080 line) and 120 fps right screen output image 153R.

  Next, the output unit 105 outputs the left screen output image 153L generated by the main screen image processing unit 102 to the left screen drive unit 24L as the left screen image 58L, and the right screen generated by the sub screen image processing unit 103. The output image 153R is output to the right screen drive unit 24R as the right screen image 58R.

  Next, the left screen drive unit 24L displays the left screen image 58L on the left screen 26L of the display panel 26. The right screen drive unit 24R displays the right screen image 58R on the right screen 26R of the display panel 26.

  As described above, a total of 1080p and 120 fps images including the left screen image 58L and the right screen image 58R are displayed on the display panel 26. That is, the dot clock of the image displayed on the display panel 26 is 297 MHz.

  Next, an operation example when the frame rate of the three-dimensional image 112 is 120 fps will be described with reference to FIG.

  Specifically, in the example illustrated in FIG. 15, the three-dimensional image 112 is a 1080i frame sequential and 120 fps image. That is, the three-dimensional image 112 includes a left eye image 60l of 1080i (1920 columns × 540 rows) and a right eye image 60r of 1080i (1920 columns × 540 rows) in one field. That is, the dot clock of the three-dimensional image 112 is 148.5 MHz.

  The display panel 26 displays a 1080p and 120 fps image in which the left-eye image 60l and the right-eye image 60r are alternately arranged.

  In this case, first, the input selection unit 101 divides the three-dimensional image 112 into a left screen input image 112L and a right screen input image 112R, and outputs the left screen input image 112L to the main screen image processing unit 102. The input image 112R is output to the sub-screen image processing unit 103.

  Here, the left screen input image 112L and the right screen input image 112R are half the image size of the three-dimensional image 112. Therefore, the dot clock of the left screen input image 112L and the right screen input image 112R is 74.25 MHz which is half of the dot clock of the three-dimensional image 112.

  Specifically, the left screen input image 112L includes a left eye image 60l of 1080i / 2 (960 columns × 540 rows) and a right eye image 60r of 1080i / 2 (960 columns × 540 rows) in one field. including. The right screen input image 112R includes a left eye image 60l of 1080i / 2 (960 columns × 540 rows) and a right eye image 60r of 1080i / 2 (960 columns × 540 rows) in one field.

  That is, the image sizes of the left screen input image 112L and the right screen input image 112R are 480 columns × 1080 rows, respectively.

  Next, the main screen preprocessing unit 120 performs I / P conversion on the left screen input image 112L to generate a left screen processed image 160L of 1080p / 2 and 120 fps. This I / P conversion doubles the vertical image size. Therefore, the dot clock of the left screen processed image 160L is 148.5 MHz, which is twice that of the left screen input image 112L.

  Specifically, the left screen processed image 160L includes a left-eye image 60l of 1080p / 2 (960 columns × 1080 rows) and a right-eye image 60r of 1080p / 2 (960 columns × 1080 rows) per frame. including. Therefore, the image size of the left screen processed image 160L is 960 columns × 2160L rows.

  Next, the main screen preprocessing unit 120 stores the left screen processed image 160 </ b> L in the memory 140 via the memory controller 141.

  Next, the main screen post-processing unit 121 reads the left screen processed image 160L via the memory controller 141. At this time, the main screen post-processing unit 121 performs 1080p / 2 (960 columns × 1080) in which the left-eye image 60l and the right-eye image 60r are alternately arranged by performing pattern conversion of the left-screen processed image 160L. Row) and a left screen processed image 163L of 120 fps is generated. For example, the main screen post-processing unit 121 generates a left screen processed image 163L that alternately includes only one of the left eye image 60l and the right eye image 60r included in each frame of the left screen processed image 160L.

  This pattern conversion reduces the image size to ½. Therefore, the dot clock of the left screen output image 153L is 74.25 MHz which is half of the dot clock of the left screen processed image 160L.

  Next, the main screen post-processing unit 121 enlarges the image size of the left screen processed image 163L to thereby arrange 1080p / 2 (960 rows × 960 images) in which the left eye image 60l and the right eye image 60r are alternately arranged. 1080 line) and 120 fps left screen output image 153L. This enlargement process doubles the image size. Therefore, the dot clock of the left screen output image 153L is 148.5 MHz, which is twice the dot clock of the left screen processed image 163L.

  On the other hand, the sub-screen image processing unit 103 performs the same processing as the main screen image processing unit 102 on the right screen input image 112R, thereby alternately arranging the left-eye image 60l and the right-eye image 60r. The left screen output image 153L of 1080p / 2 (960 columns × 1080 rows) and 120 fps is generated.

  Next, the output unit 105 outputs the left screen output image 153L generated by the main screen image processing unit 102 to the left screen drive unit 24L as the left screen image 58L, and the right screen generated by the sub screen image processing unit 103. The output image 153R is output to the right screen drive unit 24R as the right screen image 58R.

  Next, the left screen drive unit 24L displays the left screen image 58L on the left screen 26L of the display panel 26. The right screen drive unit 24R displays the right screen image 58R on the right screen 26R of the display panel 26.

  As described above, a total of 1080p and 120 fps images including the left screen image 58L and the right screen image 58R are displayed on the display panel 26. That is, the dot clock of the image displayed on the display panel 26 is 297 MHz.

  As described above, in the three-dimensional image processing apparatus 100 according to Embodiment 1 of the present invention, the main screen image processing unit 102 and the sub screen image processing unit 103 each process an image with a maximum dot clock of 148 and 5 MHz. Thus, an image with a dot clock of 297 MHz can be generated.

  Next, with reference to FIG. 16, an operation example in the case of converting the format of the 3D image 112 into a line sequential image will be described.

  In the example shown in FIG. 16, the three-dimensional image 112 is a full-size 1080i side-by-side and 60 fps image, as in the example shown in FIG. The display panel 26 displays line sequential 1080p and 60 fps images.

  The operations of the main screen preprocessing unit 120 and the sub screen preprocessing unit 130 are the same as those in FIG.

  In this case, the main screen post-processing unit 121 includes a plurality of pixels corresponding to the left screen 26L of the display panel 26 among the plurality of pixels included in the left screen processed image 160L and the right screen processed image 160R via the memory controller 141. A left screen processed image 161L including pixels is read out. Further, the main screen post-processing unit 121 performs pattern conversion of the left screen processed image 161L, whereby 1080p / 2 (960 columns × 1080 rows) in which the left eye image 60l and the right eye image 60r are alternately arranged. ) And a left screen output image 153L of 60 fps is generated.

  Specifically, the main screen post-processing unit 121 reads the left half of the left screen processed image 160L and the left half of the right screen processed image 160R, and also reads the left half of the read left screen processed image 160L and the right screen processed image 160R. The pattern conversion is performed by arranging the left half of the two in a horizontal stripe shape.

  This pattern conversion reduces the image size to ½. Therefore, the dot clock of the left screen output image 153L is 74.25 MHz which is half of the dot clock of the left screen processed image 160L.

  On the other hand, the sub-screen post-processing unit 131 performs the same processing as the main-screen post-processing unit 121, whereby 1080p / 2 (960 rows × 960) in which the left-eye image 60l and the right-eye image 60r are alternately arranged. 1080 lines) and 60 fps right screen output image 153R.

  The output unit 105 outputs the left screen output image 153L generated by the main screen image processing unit 102 to the left screen drive unit 24L as the left screen image 58L, and outputs the right screen output generated by the sub screen image processing unit 103. The image 153R is output to the right screen drive unit 24R as the right screen image 58R.

  Next, the left screen drive unit 24L displays the left screen image 58L on the left screen 26L of the display panel 26. The right screen drive unit 24R displays the right screen image 58R on the right screen 26R of the display panel 26.

  As described above, a total of 1080p and 60 fps images including the left screen image 58L and the right screen image 58R are displayed on the display panel 26. That is, the dot clock of the image displayed on the display panel 26 is 148.5 MHz.

  The arrangement pattern of the three-dimensional image 112 may be any one of the patterns shown in FIGS. 3A, 3B, 4A, 4B, 5A, 5B, 6A, and 6B. Similarly, the arrangement patterns of the left screen output image 153L and the right screen output image 153R (images displayed on the display panel 26) are shown in FIGS. 3A, 3B, 4A, 4B, 5A, 5B, 6A, and 6A. Any of the patterns shown in FIG. 6B may be used.

  The scanning method, frame rate, and image size of the three-dimensional image 112, the left screen output image 153L, and the right screen output image 153R may be other than those described above.

  The order of the image size reduction, image size enlargement, IP conversion, pattern conversion, and frame rate conversion processing described above is an example, and these processing may be performed in an arbitrary order.

  When the image size of the left eye image 60l and the image size of the right eye image 60r included in the three-dimensional image 112 are larger than the display image size of the display panel 26, the main screen image processing unit 102 and the sub screen The image processing unit 103 performs image size reduction processing.

  In addition, the main screen preprocessing unit 120 temporarily sets the left eye image 60l and the right eye image 60r included in the three-dimensional image 112 to the left regardless of the image size of the left eye image 60r and the display image size of the display panel 26. After reducing the image size of the screen input image 112L, the main screen post-processing unit 121 may increase the image size so that the reduced image size is restored to the original image size. For example, when the image size of the left-eye image 60l and the image size of the right-eye image 60r included in the three-dimensional image 112 match the display image size of the display panel 26 (when the image size is not reduced or enlarged) ), The main screen pre-processing unit 120 reduces the image size of the left screen input image 112L to ½ in the vertical direction, and the main screen post-processing unit 121 increases the reduced image size by two times in the vertical direction. May be.

  Thereby, since the amount of data stored in the memory 140 can be reduced, the capacity of the memory 140 can be reduced. Furthermore, the processing amount in the IP conversion unit 123, the pattern conversion unit 125, and the like can be reduced.

  As described above, the 3D image processing apparatus 100 according to Embodiment 1 of the present invention divides the 3D image 112 into the left screen input image 112L and the right screen input image 112R, and the left screen input image 112L. Processing is performed by the main screen image processing unit 102, and the right screen input image 112 </ b> R is processed by the sub screen image processing unit 103. By performing such parallel processing, the processing capabilities of the main screen image processing unit 102 and the sub screen image processing unit 103 can be halved compared to the case where the three-dimensional image 112 is processed by one image processing unit.

  Furthermore, the 3D image processing apparatus 100 uses the main screen image processing unit 102 that processes the main screen image and the sub screen image processing unit 103 that processes the sub screen image for the parallel processing in the two-screen processing mode. Thus, it is possible to suppress the addition of a circuit from the conventional image processing apparatus. Therefore, the 3D image processing apparatus 100 according to Embodiment 1 of the present invention can generate a high-quality 3D image while suppressing an increase in cost.

  In general, the processing capability of the sub screen image processing unit 103 is lower than the processing capability of the main screen image processing unit 102. In such a case, a difference occurs in the image quality between the left screen output image 153L and the right screen output image 153R. In order to avoid this, the processing capability of the main screen image processing unit 102 may be matched with the processing capability of the sub-screen image processing unit 103. Thereby, although the image quality of the left screen output image 153L is reduced, the unevenness of the image quality between the left screen output image 153L and the right screen output image 153R can be eliminated.

  Note that the processing capability of the sub-screen image processing unit 103 may be the same as that of the main screen image processing unit 102. In this case, it is necessary to increase the processing capability of the sub-screen image processing unit 103 compared to the conventional image processing device, but the cost of the three-dimensional image processing device 100 is lower than when a new image processing unit is added. Increase can be suppressed.

(Embodiment 2)
In the first embodiment, the example in which the 3D image 112 is divided into the left screen input image 112L and the right screen input image 112R, and then all the format conversion processes are performed in parallel on each of them is described. In the second embodiment of the present invention, an example in which a part of the format conversion process is performed on the three-dimensional image 112 and then divided into a left screen image and a right screen image will be described.

  In addition, below, the description which overlaps with Embodiment 1 is abbreviate | omitted, and the difference with Embodiment 1 is mainly demonstrated.

  FIG. 17 is a block diagram showing configurations of the main screen image processing unit 102 and the sub screen image processing unit 103 according to Embodiment 2 of the present invention. In addition, the same code | symbol is attached | subjected to the element similar to FIG. The configuration of the 3D image processing apparatus 100 according to Embodiment 2 of the present invention is the same as that shown in FIG.

  The 3D image processing apparatus 100 according to Embodiment 2 of the present invention differs from the 3D image processing apparatus 100 according to Embodiment 1 in the following points.

  The input selection unit 101 outputs the 3D image 112 to the main screen image processing unit 102 in the 3D image processing mode.

  The main screen preprocessing unit 120 performs horizontal image size reduction and IP conversion on the three-dimensional image 112 in the three-dimensional image processing mode, and then outputs the processed image to the left screen input image 162L. The image is divided into the right screen input image 162R. The main screen preprocessing unit 120 generates the left screen processed image 160L by reducing the image size in the vertical direction on the divided left screen input image 162L.

  The sub-screen preprocessing unit 130 generates the right screen processed image 160R by reducing the vertical image size of the divided right screen input image 162R in the 3D image processing mode.

  Hereinafter, an operation example in the 3D image processing mode by the 3D image processing apparatus 100 according to Embodiment 2 of the present invention will be described.

  FIG. 18 is a diagram illustrating an operation example in the 3D image processing mode by the 3D image processing apparatus 100 according to Embodiment 2 of the present invention.

  In the 3D image processing apparatus 100 according to Embodiment 2 of the present invention, in the 3D image processing mode, the main screen preprocessing unit 120 generates a converted image 162 by performing I / P conversion on the 3D image 112. At the same time, the converted image 162 is divided into a left screen input image 162L and a right screen input image 162R.

  Here, in the example illustrated in FIG. 18, the three-dimensional image 112 is a full-size 1080i frame sequential and 60 fps image. That is, the three-dimensional image 112 includes a left-eye image 60l of 1080i (1920 columns × 540 rows) and a right-eye image 60r of 1080i (1920 columns × 540 rows) in one frame. That is, the dot clock of the three-dimensional image 112 is 148.5 MHz.

  The display panel 26 displays a 1080p and 120 fps image in which the left-eye image 60l and the right-eye image 60r are alternately arranged.

  In this case, first, the input selection unit 101 outputs the three-dimensional image 112 to the main screen image processing unit 102.

  Next, the main screen preprocessing unit 120 performs I / P conversion on the three-dimensional image 112 to generate a 1080p × 2 and 60 fps converted image 162. This I / P conversion doubles the vertical image size. Therefore, the dot clock of the converted image 162 is 297 MHz, which is twice that of the three-dimensional image 112.

  Specifically, the converted image 162 includes a left-eye image 60l of 1080p (1920 columns × 1080 rows) and a right-eye image 60r of 1080p (1920 columns × 1080 rows) in one frame. Therefore, the image size of the converted image 162 is 1920 columns × 2160 L rows.

  Next, the main screen preprocessing unit 120 divides the converted image 162 into a left screen input image 162L and a right screen input image 162R.

  Here, the left screen input image 162L and the right screen input image 162R are half the image size of the converted image 162. Therefore, the dot clocks of the left screen input image 162L and the right screen input image 162R are 148.5 MHz, which is half of the dot clock of the converted image 162.

  Specifically, the left screen input image 162L includes a left-eye image 60l of 1080p / 2 (960 columns × 1080 rows) and a right-eye image 60r of 1080p / 2 (960 columns × 1080 rows) per frame. including. The right screen input image 162R includes a left-eye image 60l of 1080p / 2 (960 columns × 1080 rows) and a right-eye image 60r of 1080p / 2 (960 columns × 1080 rows) in one frame.

  That is, the image sizes of the left screen input image 162L and the right screen input image 162R are 1920 columns × 1080 rows, respectively.

  The IP conversion process and the division process are preferably performed simultaneously. That is, an image corresponding to the converted image 162 is not actually generated. In other words, the main screen preprocessing unit 120 generates the left screen input image 162L and the right screen input image 162R by performing IP conversion and division on the three-dimensional image 112. Thereby, the maximum value of the dot clock of the image processed by each processing unit can be set to 148.5 MHz instead of 297 MHz.

  Next, the main screen preprocessing unit 120 stores the left screen input image 162L (left screen processed image 160L) in the memory 140 via the memory controller 141.

  Further, the main screen preprocessing unit 120 outputs the right screen input image 162R to the sub screen preprocessing unit 130.

  Next, the sub-screen preprocessing unit 130 stores the right screen input image 162R (right screen processed image 160R) in the memory 140 via the memory controller 141.

  Note that the processes of the main screen post-processing unit 121 and the sub-screen post-processing unit 131 are the same as those in the first embodiment, and a description thereof will be omitted.

  In the example of Embodiment 2 of the present invention, the vertical reduction unit 124 and the main screen post-processing unit 121 correspond to the first image processing unit of the present invention, and the vertical reduction unit 134 and the sub-screen post-processing unit 131 are the main image. This corresponds to the second image processing unit of the invention. The IP conversion unit 123 and the IP conversion unit 133 correspond to a first IP conversion unit and a second IP conversion unit of the present invention, respectively. The converted image 162, the left screen input image 162L, and the right screen input image 162R correspond to the first input three-dimensional image, the first input image, and the second input image of the present invention, respectively. The main screen image 110, the sub screen image 111, and the three-dimensional image 112 correspond to the third image, the fourth image, and the second input three-dimensional image of the present invention, respectively. In addition, images generated by the IP conversion unit 123 and the IP conversion unit 133 in the two-screen processing mode correspond to the first image and the second image of the present invention, respectively.

  As described above, a total of 1080p and 120 fps images including the left screen image 58L and the right screen image 58R are displayed on the display panel 26. That is, the dot clock of the image displayed on the display panel 26 is 297 MHz.

  As described above, in the three-dimensional image processing apparatus 100 according to Embodiment 2 of the present invention, the main screen image processing unit 102 and the sub screen image processing unit 103 each process an image with a maximum dot clock of 148 and 5 MHz. Thus, an image with a dot clock of 297 MHz can be generated.

  As described above, the 3D image processing apparatus 100 according to the second embodiment of the present invention, like the 3D image processing apparatus 100 according to the first embodiment, suppresses an increase in cost and has a high quality tertiary. An original image can be generated.

  The order of the image size reduction, image size enlargement, IP conversion, pattern conversion, and frame rate conversion processing described above is an example, and these processing may be performed in an arbitrary order. Even in such a case, the 3D image processing apparatus 100 may divide the image after IP conversion into a left screen image and a right screen image.

  Note that the 3D image processing apparatus 100 may divide an image other than immediately after the IP conversion into a left screen image and a right screen image. That is, the 3D image processing apparatus 100 divides the image into a left screen image and a right screen image when the dot clock of the processed image becomes higher than a predetermined frequency (148.5 MHz in the above example). do it.

  In addition, the 3D image processing apparatus 100 converts the processed image into a left screen image and a right screen image before the dot clock of the processed image becomes higher than a predetermined frequency (148.5 MHz in the above example). It may be divided. Even in this case, the maximum value of the dot clock of the image processed by each of the main screen image processing unit 102 and the sub screen image processing unit 103 can be suppressed to 148 and 5 MHz. For example, the 3D image processing apparatus 100 may divide the image output by the horizontal reduction unit 122 into a left screen image and a right screen image.

  The three-dimensional image processing apparatus 100 according to Embodiments 1 and 2 of the present invention has been described above, but the present invention is not limited to this embodiment.

  For example, in the above description, the case where dedicated glasses (shutter glasses 43) are used has been described as an example, but the present invention can also be applied to a system that does not use dedicated glasses.

  In the above description, an example in which two images (left-eye image and right-eye image) having parallax are included in the three-dimensional image has been described. However, three or more images having parallax in the three-dimensional image are described. May be included.

  In the above description, the main screen image processing unit 102 processes the left screen image, and the sub screen image processing unit 103 processes the right screen image. However, the main screen image processing unit 102 processes the right screen image. The sub screen image processing unit 103 may process the left screen image.

  In the above description, the input selection unit 101 generates the left screen input image 112L and the right screen input image 112R by dividing the 3D image 112 into two equal parts in the left-right direction. 112L and the right screen input image 112R may be a part of the three-dimensional image 112, respectively. For example, the input selection unit 101 may bisect the three-dimensional image 112 in the vertical direction.

  Further, the image size of the left screen input image 112L and the right screen input image 112R may be different.

  The input selection unit 101 may divide the three-dimensional image 112 into three or more images. In this case, the 3D image processing apparatus 100 performs parallel processing on the three divided images. The three image processing units that perform this parallel processing include the main screen image processing unit 102 and the sub-screen image processing unit 103 described above. Even in this case, it is necessary to provide a new image processing unit to the conventional image processing apparatus. However, by using the sub-screen image processing unit 103, the number of image processing units to be newly added can be reduced. Therefore, an increase in the cost of the 3D image processing apparatus 100 can be suppressed.

  Further, the input selection unit 101 may divide the three-dimensional image 112 into the left screen input image 112L and the right screen input image 112R so as to include areas that partially overlap each other. Thereby, for example, when the digital television 20 includes two image quality correction units that individually correct the image quality of the left screen image 58L (left screen input image 112L) and the right screen image 58R (right screen input image 112R), The accuracy of end point processing (image quality correction processing near the divided boundaries) in the image quality correction unit can be improved.

  For the same reason, the left screen processed image 161L and the right screen processed image 161R may include areas that partially overlap each other.

  Similarly, the left screen output image 153L and the right screen output image 153R may be a part of the output three-dimensional image 58 (image displayed on the display panel 26).

  In the above description, the 3D image processing apparatus 100 outputs the left screen image 58L and the right screen image 58R separately. However, the 3D image processing apparatus 100 combines the left screen image 58L and the right screen image 58R and outputs the synthesized image. May be. The 3D image processing apparatus 100 may output the composite image 152 as it is without dividing it.

  Further, the configuration of the three-dimensional image processing apparatus 100 is for illustration in order to specifically describe the present invention, and the three-dimensional image processing apparatus according to the present invention is necessarily provided with all of the above-described configurations. There is no.

  For example, in the above description, the main screen image processing unit 102 and the sub screen image processing unit 103 have all the functions of image size reduction, image size enlargement, IP conversion, pattern conversion, and frame rate conversion. However, what is necessary is just to have at least one of these functions.

  In the above description, the example in which the 3D image processing apparatus 100 includes the memory 140 and the memory controller 141 commonly used in the main screen image processing unit 102 and the sub screen image processing unit 103 has been described. The unit 102 and the sub-screen image processing unit 103 may each include a memory.

  In the above description, the example in which the three-dimensional image processing apparatus 100 according to the present invention is applied to a digital television and a digital video recorder has been described. However, the three-dimensional image processing apparatus 100 according to the present invention is a three-dimensional image other than a digital television. The present invention can be applied to a three-dimensional image display device (for example, a mobile phone device, a personal computer, etc.) that displays an image. The 3D image processing apparatus 100 according to the present invention can be applied to a 3D image output apparatus (for example, a BD player) that outputs a 3D image other than a digital video recorder.

  The three-dimensional image processing apparatus 100 according to the first and second embodiments is typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.

  Further, the circuit integration is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI or a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.

  Further, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out integration of processing units using that technology.

  In addition, some or all of the functions of the 3D image processing apparatuses 100 and 100B according to Embodiments 1 and 2 of the present invention may be realized by a processor such as a CPU executing a program.

  Further, the present invention may be the above program or a recording medium on which the above program is recorded. Needless to say, the program can be distributed via a transmission medium such as the Internet.

  Moreover, you may combine at least one part among the functions of the three-dimensional image processing apparatuses 100 and 100B which concern on the said Embodiment 1-2, and its modification.

  Moreover, all the numbers used above are illustrated to specifically describe the present invention, and the present invention is not limited to the illustrated numbers.

  Further, various modifications in which the present embodiment is modified within the scope conceivable by those skilled in the art are also included in the present invention without departing from the gist of the present invention.

  The present invention can be applied to a three-dimensional image processing apparatus, and in particular, can be applied to a digital television, a digital video recorder, and the like.

DESCRIPTION OF SYMBOLS 10 3D image display system 20 Digital television 21, 31 Input part 22, 32 Decoder 23, 33 HDMI communication part 24L Left screen drive part 24R Right screen drive part 26 Display panel 26L Left screen 26R Right screen 27 Transmitter 30 Digital video recorder 40 HDMI cable 41 Optical disc 42 Broadcast wave 43 Shutter glasses 51, 55 Encoded 3D image 52, 56, 57 Input 3D image 53, 58 Output 3D image 56l, 58l, 60l Left eye image 56r, 58r, 60r Right eye Image 58L Left screen image 58R Right screen image 100, 100B Three-dimensional image processing apparatus 101 Input selection unit 102 Main screen image processing unit 103 Sub screen image processing unit 104 Composition unit 105 Output unit 110 Main screen image 111 Sub screen image 112 Tertiary The original image 112L, 162L Left screen input image 112R, 162R Right screen input image 120 Main screen pre-processing unit 121 Main screen post-processing unit 122, 132 Horizontal reduction unit 123, 133 IP conversion unit 124, 134 Vertical reduction unit 125, 135 Pattern conversion unit 126, 136 Vertical enlargement unit 127, 137 Horizontal enlargement unit 130 Sub-screen pre-processing unit 131 Sub-screen post-processing unit 140 Memory 141 Memory controller 150 Main screen processed image 151 Sub-screen processed image 152 Composite image 153L Left screen output image 153R Right screen Output image 160L, 161L, 163L Left screen processed image 160R, 161R, 163R Right screen processed image 162 Converted image

Claims (12)

Two-screen processing mode for generating a composite image including the first image and the second image in one screen, and three-dimensional image processing for converting the first input three-dimensional image in the first format into the output three-dimensional image in the second format A three-dimensional image processing apparatus having a mode,
A first image processing unit that generates a first processed image by performing a first format conversion process on the first image in the two-screen processing mode;
A second image processing unit that generates a second processed image by performing a second format conversion process on the second image in the two-screen processing mode;
A combining unit that generates the combined image by combining the first processed image and the second processed image;
An output unit that outputs the composite image in the two-screen processing mode and outputs the output three-dimensional image in the three-dimensional processing mode;
The first image processing unit performs a third format conversion process on the first input image that is a part of the first input three-dimensional image in the three-dimensional image processing mode, so that the output three-dimensional image Generating a first output image that is a part,
The second image processing unit performs a fourth format conversion process on a second input image that is a part of the first input three-dimensional image in the three-dimensional image processing mode, so that the output three-dimensional image Generate a second output image that is a part,
The three-dimensional image processing apparatus, wherein the output unit outputs the output three-dimensional image having a dot clock that is the same as or twice the dot clock of the first input three-dimensional image. The first, second, third, and fourth format conversion processes include at least one of an image size change process, a frame rate conversion process, and an interlace method to a progressive method conversion process. 3D image processing device. The three-dimensional image processing apparatus according to claim 2, wherein the third format conversion process and the fourth format conversion process include a process of increasing a frame rate. The first input 3D image and the output 3D image include a left eye image for a viewer's left eye and a right eye image for the viewer's right eye,
The three-dimensional image processing apparatus according to claim 2, wherein the third format conversion process and the fourth format conversion process further include a process of changing an arrangement pattern of the left-eye image and the right-eye image. . 5. The three-dimensional image processing apparatus according to claim 2, wherein the first, second, third, and fourth format conversion processes include a conversion process from an interlace system to a progressive system. The three-dimensional image processing apparatus further includes a memory,
The first image processing unit
In the three-dimensional image processing mode, a first processed image is generated by performing a first preprocessing included in the third format conversion process and including a process of reducing the image size, in the first input image, A first preprocessing unit for storing the third processed image in the memory;
The second image processing unit
In the three-dimensional image processing mode, a fourth processed image is generated by performing a second preprocessing included in the fourth format conversion process and including a process of reducing the image size, in the second input image, A second preprocessing unit for storing the fourth processed image in the memory;
The first image processing unit further includes:
In the three-dimensional image processing mode, the fifth processed image including at least one of the third processed image and the fourth processed image stored in the memory is included in the third format conversion processing, and the image size A first post-processing unit that generates the first output image by performing a first post-process including a process of enlarging
In the three-dimensional image processing mode, a sixth processed image including at least one of the third processed image and the fourth processed image stored in the memory is included in the fourth format conversion process, and the image size The three-dimensional image processing apparatus according to claim 5, further comprising: a second post-processing unit that generates the second output image by performing a second post-process including a process of enlarging the image. The first post-process and the second post-process further include a process of changing an arrangement pattern of the left-eye image and the right-eye image,
The first post-processing unit includes a plurality of pixels corresponding to the first output image among a plurality of pixels included in the third processed image and the fourth processed image stored in the memory. By reading out a 5-processed image and performing the first post-processing on the fifth processed image, the first output image is generated,
The second post-processing unit includes a plurality of pixels corresponding to the second output image among a plurality of pixels included in the third processed image and the fourth processed image stored in the memory. The three-dimensional image processing apparatus according to claim 6, wherein a six-processed image is read and the second output image is generated by performing the second post-processing on the sixth processed image. The three-dimensional image processing apparatus according to claim 6 or 7, wherein the first pre-processing and the second pre-processing include a process of converting a scanning method from an interlace method to a progressive method. The first, second, third, and fourth format conversion processes include at least one of image size change and frame rate conversion,
The three-dimensional image processing apparatus further includes:
A first IP conversion unit that generates the first image by converting the third image from an interlace method to a progressive method in the two-screen processing mode;
A second IP conversion unit that generates the second image by converting the fourth image from the interlace method to the progressive method in the two-screen processing mode;
The first IP conversion unit generates the first input three-dimensional image by converting a second input three-dimensional image from an interlace method to a progressive method in the three-dimensional image processing mode. The three-dimensional image processing apparatus according to any one of the above. The first image processing unit is one of a left half and a right half of the output three-dimensional image by performing the first format conversion process on the first input image in the three-dimensional image processing mode. Generating a first output image;
The second image processing unit performs the first format conversion process on the second input image in the three-dimensional image processing mode, so that the second half of the output three-dimensional image is the other of the left half and the right half. The three-dimensional image processing apparatus according to any one of claims 1 to 9, wherein a two-output image is generated. The three-dimensional image processing apparatus further includes:
The input selection part which divides | segments the said 1st input 3D image into the said 1st input image and the said 2nd input image in the said 3D image processing mode is provided. 3D image processing device. Two-screen processing mode for generating a composite image including the first image and the second image in one screen, and three-dimensional image processing for converting the first input three-dimensional image in the first format into the output three-dimensional image in the second format A control method of a three-dimensional image processing apparatus having a first image processing unit and a second image processing unit,
The first image processing unit generating a first processed image by performing a first format conversion process on the first image in the two-screen processing mode;
The second image processing unit generates a second processed image by performing a second format conversion process on the second image in the two-screen processing mode;
Generating the synthesized image by synthesizing the first processed image and the second processed image;
In the 3D image processing mode, the first image processing unit performs a third format conversion process on the first input image that is a part of the first input 3D image, so that the output 3D image Generating a first output image that is a part;
The second image processing unit performs a fourth format conversion process on a second input image that is a part of the first input three-dimensional image in the three-dimensional image processing mode, whereby the output three-dimensional image Generating a second output image that is a part;
Outputting the composite image in the two-screen processing mode;
And a step of outputting the output three-dimensional image having a dot clock equal to or twice the dot clock of the first input three-dimensional image in the three-dimensional image processing mode.

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