JP5294929B2 - Semiconductor device, TFT substrate, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device (double gate type thin film transistor) improved in drive performance by increasing an ON-current, and also to provide a semiconductor device manufacturing method for manufacturing the semiconductor device, a TFT substrate mounted with the semiconductor device, and a display device which applies the TFT substrate. <P>SOLUTION: The semiconductor device 1 is equipped with: a first gate electrode 11 formed on an insulating substrate 10 (insulating substrate 110); a first insulating layer 12 formed on the first gate electrode 11; a semiconductor layer 13 formed on the first insulating layer 12; a source electrode 15 connected to one end of the semiconductor layer 13; a drain electrode 16 connected to the other end of the semiconductor layer 13 so as to oppose the source electrode 15; a second insulating layer 17 formed on the semiconductor layer 13; and a second gate electrode 19 formed on the second insulating layer 17. At least either one of the first gate electrode 11 and the second gate electrode 19 is formed of a transparent conductive material, and constitutes a transparent electrode. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

The present invention, first gate electrode formed on an insulating substrate, a semiconductor layer, a semiconductor device having a second gate electrode, this semiconductor device equipped with TFT substrate, and a display apparatus using the TFT substrate.

  In a display device such as a liquid crystal display device, an inverted staggered amorphous silicon TFT (Thin Film Transistor: hereinafter, TFT may be referred to as a thin film transistor) has been used (for example, refer to Patent Document 1). However, the inverted staggered amorphous silicon TFT has a problem that the on-current is the smallest among TFTs used in the display device.

  In other words, since the on-current is small, it is difficult to increase the speed, and when the size of the TFT is increased to increase the on-current, the area of the drive unit (TFT) of the display device is larger than the area of the display unit. Thus, there is a problem that a substantial display area is reduced and a high-definition display device cannot be realized.

JP 2001-127296 A

  The present invention has been made in view of such a situation, and is a semiconductor device including a first gate electrode, a semiconductor layer, and a second gate electrode stacked on an insulating substrate. A semiconductor device (double gate) in which at least one of the gate electrode and the second gate electrode is formed of a transparent conductive material and the channel region formed in the semiconductor layer is enlarged, thereby increasing the on-current that can be extracted and increasing the driving capability. Type thin film transistor).

  Further, the present invention is a TFT substrate having a display pixel electrode and a thin film transistor as a pixel transistor, and a semiconductor device having a large on-current (double gate type) by using the thin film transistor as the semiconductor device according to the present invention. Another object of the present invention is to provide a TFT substrate capable of driving a pixel electrode using a thin film transistor) as a pixel transistor and performing a large screen display at high speed.

  Further, the present invention is a display device including a TFT substrate having pixel electrodes for display, and by using the TFT substrate as a TFT substrate according to the present invention, a large screen display is possible and a display area ratio is improved. Another object is to provide a display device.

A semiconductor device according to the present invention is formed on a first gate electrode formed on an insulating substrate, a first insulating layer formed on the first gate electrode, and the first insulating layer. A semiconductor electrode; a source electrode connected to one end of the semiconductor layer; a drain electrode connected to the other end of the semiconductor layer opposite the source electrode; and a second electrode formed on the semiconductor layer. A semiconductor device comprising: an insulating layer; a second gate electrode formed on the second insulating layer; and a channel region formed in the semiconductor layer between the source electrode and the drain electrode, At least one of the first gate electrode and the second gate electrode is formed of a transparent conductive material, and the second insulating layer is formed by inserting the second gate electrode between the source electrode and the drain electrode. 2 insulation layer holes, the second insulation Sides of Soana has a protrusion protruding toward the center, projecting portion, characterized by having a projection length of the above 5nm to the end portion of the bottom surface of the second insulating layer hole.

With this structure, a double gate type TFT (double gate type thin film transistor) having a first gate electrode and a second gate electrode can be formed and a channel region in a semiconductor layer can be enlarged, so that an on-current that can be extracted is increased. A semiconductor device with high driving capability can be obtained. In addition, since the second gate electrode is pinned to the constriction formed below the protruding portion of the second insulating layer hole, the gap between the second insulating layer and the second gate electrode It is possible to improve the adhesion and prevent the second gate electrode from peeling off, and the yield and reliability can be improved.

  In the semiconductor device according to the present invention, the source electrode and the drain electrode are joined to a surface of the semiconductor layer, and the semiconductor layer is thinned in the channel region between the source electrode and the drain electrode. It has a channel step, and the channel step is 10 nm or more and 200 nm or less.

  With this configuration, since the channel step is 10 nm or more, the influence of residue variation on the surface of the channel region (semiconductor layer) thinned by etching is suppressed, and the channel step is 200 nm or less. It is possible to suppress a decrease in on-current due to an increase in the distance between the region and the source electrode and the distance between the channel region and the drain electrode.

  In the semiconductor device according to the present invention, the semiconductor layer is mainly composed of microcrystalline silicon.

  With this configuration, since microcrystalline silicon having high mobility is used as a channel region on the surface side of a semiconductor layer that cannot be used in a normal inverted staggered TFT, a large on-current can be extracted.

  In the semiconductor device according to the present invention, a silicon oxide film is provided between the semiconductor layer and the second insulating layer.

  With this configuration, the level formed on the surface of the semiconductor layer can be reduced, so that a reduction in mobility due to the presence of the level can be suppressed.

  In the semiconductor device according to the present invention, the channel region has a thickness of 10 nm to 1000 nm.

  With this configuration, the film thickness of the semiconductor layer in the channel region can be increased to 10 nm or more, and a stable film quality can be obtained. Therefore, it is possible to ensure the stability of transistor characteristics. An increase in the layer formation time can be suppressed.

  In the semiconductor device according to the present invention, the first insulating layer and the second insulating layer have the same main component.

  With this configuration, the same material can be used for the materials used for forming the first insulating layer and the second insulating layer, the gas used for etching, and the etching material. It becomes possible.

  The TFT substrate according to the present invention includes an insulating substrate, a display pixel electrode formed on the insulating substrate, and a pixel transistor that is formed on the insulating substrate and controls a voltage applied to the pixel electrode. The thin film transistor is a semiconductor device according to the present invention.

  With this configuration, a semiconductor device (double-gate TFT) having a large on-current is used as a pixel transistor, so that a pixel electrode can be driven by a low-resistance pixel transistor, and a large-screen display can be performed at high speed. It can be.

In addition, the TFT substrate according to the present invention may further include a driver transistor that is formed on the insulating substrate and controls the pixel transistor, and the driver transistor may be configured by the semiconductor device according to the present invention.

  With this configuration, a semiconductor device (double-gate thin film transistor) with a large on-state current is used as a driver transistor of a driver circuit (gate driver circuit, source driver circuit), so that the area occupied by the driver circuit on the insulating substrate can be reduced. Thus, the area of the pixel transistor region with respect to the area of the insulating substrate can be increased to obtain a TFT substrate with an improved display area ratio. In addition, the TFT substrate can mount the pixel transistor and the driver transistor in a small area.

  The display device according to the present invention is a display device including a TFT substrate having a pixel electrode for display, and the TFT substrate is a TFT substrate according to the present invention.

  With this configuration, a semiconductor device (double-gate TFT) with a large on-current is used as a pixel transistor or a driver transistor, so that a large screen display is possible, and the display area is increased by increasing the area of the pixel transistor area relative to the area of the insulating substrate. A display device with an improved ratio can be obtained.

A semiconductor device according to the present invention includes a first gate electrode formed on an insulating substrate, a first insulating layer formed on the first gate electrode, and a semiconductor formed on the first insulating layer. A source electrode connected to one end of the semiconductor layer, a drain electrode facing the source electrode and connected to the other end of the semiconductor layer, a second insulating layer formed on the semiconductor layer, a second A semiconductor device comprising a second gate electrode formed on an insulating layer, wherein at least one of the first gate electrode and the second gate electrode is formed of a transparent conductive material, and the second insulating layer is a source A second insulating layer hole in which a second gate electrode is fitted between the electrode and the drain electrode; and a side surface of the second insulating layer hole has a protruding portion protruding in a central direction, and the protruding portion is a second insulating layer. that we have a projection length of the above 5nm to the end portion of the bottom surface of Soana.

Therefore, a double gate TFT having a first gate electrode and a second gate electrode can be formed to expand a channel region in the semiconductor layer, so that a semiconductor device having a large driving capability can be obtained by increasing the on-current that can be extracted. There is an effect that can be. In addition, since the second gate electrode is pinned to the constriction formed below the protruding portion of the second insulating layer hole, the gap between the second insulating layer and the second gate electrode It is possible to improve the adhesion and prevent the second gate electrode from peeling off, and the yield and reliability can be improved.

  A TFT substrate according to the present invention includes an insulating substrate, a pixel electrode for display formed on the insulating substrate, and a thin film transistor as a pixel transistor that is formed on the insulating substrate and controls a voltage applied to the pixel electrode. A thin film transistor, which is a TFT substrate, is a semiconductor device according to the present invention.

  Therefore, since a semiconductor device (double-gate TFT) having a large on-current is used as a pixel transistor, the pixel electrode can be driven by a low-resistance pixel transistor, and a TFT substrate capable of large-screen display by high-speed driving is obtained. There is an effect that can be.

  The display device according to the present invention is a display device including a TFT substrate having a pixel electrode for display, and the TFT substrate is a TFT substrate according to the present invention.

Accordingly, since the used semiconductor device ON current is large (the double gate type TFT) and a pixel transistor data, an effect that can have a large screen display, it can be improved in display area ratio display.

It is a cross-sectional schematic diagram which shows typically the cross-sectional state of the semiconductor device which concerns on Embodiment 1 of this invention, and a TFT substrate (principal part). It is a plane schematic diagram which shows typically the planar state of the semiconductor device which concerns on Embodiment 1 of this invention, and a TFT substrate (principal part). It is explanatory drawing explaining the opening state after image development of the planarization film in the manufacturing method of the semiconductor device concerning Embodiment 2 of the present invention, and (A) is a section state by arrow AA shown in Drawing 1B. (B) is a cross-sectional schematic diagram which shows the cross-sectional state in the arrow BB shown to FIG. 1B. It is explanatory drawing explaining the state which etched the insulating film by using the planarization film | membrane after image development in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention as a mask, (A) is the arrow A shown to FIG. 1B. It is a cross-sectional schematic diagram which shows the cross-sectional state in -A, (B) is a cross-sectional schematic diagram which shows the cross-sectional state in the arrow BB shown to FIG. 1B. Explanatory drawing explaining the state which etch-backed the planarizing film after image development in the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention, and exposed the 2nd insulating layer corresponding to the hole for 2nd gate electrodes. (A) is a schematic cross-sectional view showing the cross-sectional state at arrow AA shown in FIG. 1B, and (B) is a schematic cross-sectional view showing the cross-sectional state at arrow BB shown in FIG. 1B. It is. It is explanatory drawing explaining the state which formed the 2nd gate electrode and pixel electrode in the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention, (A) is the arrow AA shown to FIG. 1B. It is a cross-sectional schematic diagram which shows a cross-sectional state, (B) is a cross-sectional schematic diagram which shows the cross-sectional state in the arrow BB shown to FIG. 1B. It is a cross-sectional schematic diagram which shows typically the cross-sectional state of the principal part of the semiconductor device which concerns on Embodiment 3 of this invention. It is a cross-sectional schematic diagram which shows typically the cross-sectional state of the principal part of the semiconductor device which concerns on Embodiment 4 of this invention. It is a plane schematic diagram which shows typically the planar state of the TFT substrate which concerns on Embodiment 10 of this invention. It is a plane schematic diagram which shows typically the planar state of the TFT substrate (modification 1) which concerns on Embodiment 10 of this invention. It is a plane schematic diagram which shows typically the planar state of the TFT substrate (modification 2) which concerns on Embodiment 10 of this invention. It is a front schematic diagram which shows typically the front state of the display apparatus which concerns on Embodiment 11 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In order to facilitate understanding of the semiconductor device according to the embodiment of the present invention, a comparative example based on the prior art will be described first.

<Comparative example>
A general inverted stagger type amorphous silicon TFT described as background art was actually manufactured. The element size is a channel length L = 4 μm and a channel width W = 18 μm.

  The film thickness of each layer is as follows. That is, the gate electrode made of titanium (Ti) / aluminum (Al) / titanium laminated film is 400 nm, the silicon nitride (SiNx) gate insulating layer is 410 nm, and the amorphous silicon semiconductor layer (film thickness in the state where the channel region is completed) is The thickness was 150 nm, the high-concentration contact layer was 50 nm, the source and drain electrodes made of a titanium / aluminum / titanium laminated film were 400 nm, the silicon nitride passivation layer was 250 nm, and the planarization film was 4 μm.

As a result of measuring the transistor characteristics of the manufactured inverted staggered amorphous silicon TFT, the threshold voltage Vth was 4 V, and the obtained on-current was Id = 5.70 × 10 ⁻⁷ A. The drain voltage Vd at the time of measurement was 1 V and the gate voltage Vg at the time of on-current evaluation was 35 V. Hereinafter, the drain voltage Vd and the gate voltage Vg when measuring the on-current were set to the same conditions.

  It is impossible to improve the small on-current of the inverted staggered amorphous silicon TFT at a low cost with the conventional inverted staggered structure.

  In other words, in the conventional inverted staggered amorphous silicon TFT that has been subjected to comparative measurement, the gate electrode is formed only on one side (lower side) of the semiconductor layer, so that when the gate voltage is applied, the channel region is on one side (lower side). ) Only. Therefore, there is a limit to the on-current that can be extracted, and there is a problem that it is impossible in principle to increase the on-current.

<Embodiment 1>
Based on FIG. 1A and FIG. 1B, a semiconductor device (double gate type TFT) according to the present embodiment and a TFT substrate (main part) on which the semiconductor device is formed will be described. Since the TFT substrate will be described in more detail in Embodiment 10, only an outline is given here.

  1A is a schematic cross-sectional view schematically showing a cross-sectional state of a semiconductor device and a TFT substrate (main part) according to Embodiment 1 of the present invention. In addition, the position of a cross section is arrow AA shown to FIG. 1B. In addition, hatching is omitted in consideration of the visibility of the figure (the same applies below).

  FIG. 1B is a schematic plan view schematically showing a planar state of the semiconductor device and the TFT substrate (main part) according to Embodiment 1 of the present invention.

  The semiconductor device 1 according to the present embodiment is formed on a first gate electrode 11 formed on an insulating substrate 10 (an insulating substrate 110 in the TFT substrate 100) and on the first gate electrode 11. A first insulating layer 12; a semiconductor layer 13 formed on the first insulating layer 12; a source electrode 15 connected to one end of the semiconductor layer 13; and the other end of the semiconductor layer 13 facing the source electrode 15. A drain electrode 16 connected to the semiconductor layer 13, a second insulating layer 17 formed on the semiconductor layer 13, a second gate electrode 19 formed on the second insulating layer 17, a source electrode 15 and a drain electrode 16 And a channel region 13c formed in the semiconductor layer 13 therebetween.

  In the semiconductor device 1, at least one of the first gate electrode 11 and the second gate electrode 19 is formed of a transparent conductive material and constitutes a transparent electrode.

  Therefore, a double-gate TFT having the first gate electrode 11 and the second gate electrode 19 can be formed and the channel region 13c in the semiconductor layer 13 can be enlarged on both the upper and lower sides, so that the on-current that can be extracted is increased. The semiconductor device 1 having high driving capability can be obtained.

  In addition, the semiconductor device 1 is applied to a TFT substrate 100 having a display pixel electrode 130 and a thin film transistor (TFT) as a pixel transistor 101 that controls a voltage applied to the pixel electrode 130, so that the first gate electrode 11 and the first gate electrode 11 Since at least one of the two gate electrodes 19 can be formed using the same transparent conductive material as that of the pixel electrode 130, a double gate can be formed without adding an additional material and an additional layer to the manufacturing process of the TFT substrate 100. A type TFT (semiconductor device 1 according to the present invention) can be easily and inexpensively manufactured as the pixel transistor 101.

  The drain electrode 16 and the pixel electrode 130 are connected by the first contact hole 21. The first gate electrode 11 and the second gate electrode 19 are connected by a second contact hole 22. The first gate electrode 11 is extended and connected to the gate signal line 11w, and a voltage is applied from the outside (driver circuit: gate driver circuit) via the gate signal line 11w. The source electrode 15 is extended and connected to the source signal line 15w, and is connected to the outside (driver circuit: source driver circuit) via the source signal line 15w. The details of the driver circuit will be described in Embodiment 10.

  A planarizing film 18 is formed in a region other than the second insulating layer hole 17h, the first contact hole 21, and the second contact hole 22, so as to planarize the entire surface of the semiconductor device 1 and the TFT substrate 100. .

  On the surface side of the semiconductor layer 13 (the side to which the source electrode 15 and the drain electrode 16 are connected), a high-concentration contact layer 13d is formed to make ohmic contact between the source electrode 15 and the drain electrode 16 with respect to the semiconductor layer 13. Since the semiconductor device 1 (double gate TFT) is an n-channel type, the high-concentration contact layer 13d is formed by introducing a high-concentration n-type impurity and is an n + type.

  Since the semiconductor device 1 has a structure in which the semiconductor layer 13 is sandwiched between the first gate electrode 11 and the second gate electrode 19, when the gate voltage is applied, the channel region 13c is located above the semiconductor layer 13 (the second layer). It is formed on both sides of the gate electrode 19 side) and the lower side (first gate electrode 11 side). Therefore, the channel region 13c is enlarged as compared with the conventional inverted stagger type TFT, and the on-current that can be extracted from the drain electrode 16 (source electrode 15) can be increased according to the size of the enlarged region.

  That is, in the semiconductor device 1, the gate electrode (first gate electrode 11) is disposed only on the lower side of the semiconductor layer 13 such as a conventional inverted staggered TFT. The structure is such that (second gate electrode 19) is arranged (added).

  Further, by applying the transparent conductive material used for forming the pixel electrode 130 as the material of the second gate electrode 19, the cost of the TFT substrate 100 manufacturing process is increased due to the addition of materials and the increase in formation layers. Therefore, it is possible to manufacture the semiconductor device 1 that can extract an on-current larger than the conventional one.

  In the semiconductor device 1 according to the present embodiment, a transparent conductive material that is the same material as the pixel electrode 130 is used for the second gate electrode 2. This is because in this embodiment, the pixel electrode 130 is formed above the source electrode 15 and the drain electrode 16, the semiconductor layer 13, and the passivation layer (second insulating layer 17). In this case, the pixel electrode 130 and the second gate electrode 19 can be formed together by performing simultaneous film formation and simultaneous patterning using the same material.

  On the other hand, when the TFT substrate 100 in which the pixel electrode 130 is formed on the surface of the insulating substrate 10 (insulating substrate 110) is employed, in order to perform simultaneous film formation and simultaneous patterning with the same material as the pixel electrode 130, It is necessary to use a transparent conductive material for one gate electrode 11.

  Note that, by using a transparent conductive material for both the first gate electrode 11 and the second gate electrode 19, the advantage of simultaneous film formation and simultaneous patterning with the same material can be obtained. Another point that makes it possible to manufacture the semiconductor device 1 without adding a material is to reuse a layer (second insulating layer 17) that has been used as a passivation layer as a gate insulating layer for the second gate electrode 19. This is the point.

As a result of measuring the on-current of the semiconductor device 1 manufactured using indium tin oxide (ITO), which is the same transparent conductive material as the pixel electrode 130, as the second gate electrode 19, the on-current is about 1.2 times that of the conventional TFT. Doubled to 6.85 × 10 ⁻⁷ A.

  The threshold voltage Vth was 4 V, which is the same as that of the inverted staggered amorphous silicon TFT manufactured in the comparative example. The device size was fabricated with a channel length of 4 μm and a channel width of 18 μm, as in the comparative example. Hereinafter, the element sizes of the semiconductor device 1 (double gate type TFT) are all channel length 4 μm and channel width 18 μm.

  As described above, by manufacturing the semiconductor device 1 using a transparent conductive material for at least one gate electrode (at least one of the first gate electrode 11 and the second gate electrode 19), a conventional inverted staggered amorphous silicon TFT is obtained. It was confirmed that the on-current can be greatly increased as compared with FIG.

<Embodiment 2>
With reference to FIGS. 1A and 1B shown in the first embodiment, the manufacturing method (manufacturing process) of the semiconductor device 1 and the TFT substrate 100 described in the first embodiment will be described as a second embodiment. In addition, the formation process of the 1st contact hole 21 and the 2nd contact hole 22 is demonstrated based on FIG. 2A thru | or FIG. 2D.

(Insulating substrate preparation process)
An insulating substrate 10 (insulating substrate 110) is prepared as a substrate for forming the semiconductor device 1 (the TFT substrate 100 will be described as appropriate).

  A glass substrate was used as the insulating substrate 10. However, the present invention is not limited to this, and a plastic substrate (transparent insulating resin substrate such as acrylic, polycarbonate, and polyimide) can also be applied. When the semiconductor device 1 (double gate type TFT) manufactured on the insulating substrate 10 is used as an insulating substrate for a display such as a liquid crystal display or an organic EL display, it is preferably a transparent insulating substrate. Moreover, when manufacturing a flexible display, it is preferable to use a plastic substrate.

(First gate electrode formation step)
Titanium (Ti), aluminum (Al), and titanium are deposited on the insulating substrate 10 by sputtering to a thickness of 100 nm, 200 nm, and 100 nm, respectively, and a Ti—Al—Ti metal laminated film is formed. A first gate metal film was formed. As a method for forming the first gate metal film, vapor deposition or the like can be used in addition to sputtering. Also, the film thickness is not particularly limited.

  Subsequently, the formed first gate metal film was patterned by a photolithography process and an etching process to form the first gate electrode 11. The resist pattern film remaining after the etching was stripped and removed using a stripping solution.

  In addition, the material which comprises the 1st gate electrode 11 is not limited to the metal of an Example. For example, transparent conductive films such as indium tin oxide (ITO) and zinc oxide (ZnO), tungsten (W), copper (Cu), chromium (Cr), tantalum (Ta), molybdenum (Mo), titanium (Ti) Such a single metal or a material containing nitrogen, oxygen, or another metal therein may be used to form a single layer, or a laminated structure in which a plurality of these materials are combined may be used.

  That is, the first gate electrode 11 includes a Mo / Al / Mo laminated film of molybdenum and aluminum, a Ti / Cu / Ti laminated film of titanium and copper, a Mo / Cu / Mo laminated film of molybdenum and copper, tantalum and tantalum nitride ( It is also possible to use a Ta / TaN / Ta laminated film by TaN).

  The transparent conductive film referred to in this embodiment may be a film having a sheet resistance of 100Ω / □ or less and a transmittance in the visible light region (wavelength of 380 nm to 780 nm) of 50% or more (less than 100%). . This is because if the transmittance is 50% or more, it can be used as a transparent conductive material.

(First insulating layer forming step)
A first insulating layer 12 made of silicon nitride (SiNx) was formed on the entire surface of the insulating substrate 10 that had undergone the first gate electrode formation process by plasma chemical vapor deposition (PECVD). The film thickness of the first insulating layer 12 was 410 nm. As a film forming gas, a mixed gas of silane (SiH ₄ ), ammonia (NH ₃ ), and nitrogen (N ₂ ) was used.

  In addition to the PECVD method, the first insulating layer 12 can be formed by sputtering, vapor deposition, inductively coupled plasma CVD apparatus, microwave CVD apparatus, or electron cyclotron resonance CVD apparatus. The material of the first insulating layer 12 is not particularly limited to the embodiment, and may be a silicon oxide film (SiOx) or the like. Further, the film thickness is not limited to the examples.

(Semiconductor layer formation process)
A semiconductor film containing amorphous silicon as a main component was formed using another film forming chamber in the same film forming apparatus used in the first insulating layer forming step. Here, the film thickness of the semiconductor film was 230 nm.

  Subsequently, the formed semiconductor film was patterned by a photolithography process and an etching process to form a semiconductor layer 13. The resist pattern film remaining after the etching was stripped and removed using a stripping solution.

  As a method for forming the semiconductor film, in addition to PECVD, sputtering, vapor deposition, inductively coupled plasma CVD apparatus, microwave CVD apparatus, and electron cyclotron resonance CVD apparatus can be used.

  The material of the semiconductor film is not particularly limited to the embodiment, and a quaternary system composed of microcrystalline silicon, polycrystalline silicon, indium (In) -gallium (Ga) -zinc (Zn) -oxygen (O) An amorphous oxide, zinc oxide (ZnO), etc. may be sufficient. Further, the film thickness is not limited to the examples.

(High concentration contact layer formation process)
In order to facilitate the ohmic contact between the semiconductor layer 13 and the source electrode 15 and the drain electrode 16 formed in the next step, a high concentration contact film is formed on the surface side of the semiconductor layer 13 (to the source electrode 15 and the drain electrode 16). On the opposite side).

  In the case of forming a high concentration contact film, only the semiconductor film is formed in the semiconductor layer forming step, and the patterning of the semiconductor layer 13 by the photolithography step and the etching step is performed as described later. You can apply it.

  In the formation of the high-concentration contact film, an n + type silicon film (high-concentration contact film) is formed in succession to the semiconductor layer formation step using a separate film formation chamber in the same film formation apparatus as in the semiconductor layer formation step. did. That is, three films of the first insulating layer 12, the semiconductor film, and the n + type silicon film are continuously formed by one apparatus. Accordingly, the transistor characteristics (TFT performance) of the semiconductor device 1 can be stabilized. Here, the film thickness of the n + type silicon film was 50 nm.

  In addition to the PECVD method, an inductively coupled plasma CVD device, a microwave CVD device, or an electron cycloton resonance CVD device can be used as a method for forming the n + type silicon film (high concentration contact film).

  The material constituting the high concentration contact film may be n + type amorphous silicon, n + type microcrystalline silicon, n + type polycrystalline silicon, or the like. That is, any material that can form an ohmic contact between the semiconductor layer 13 and the high-concentration contact layer 13d may be used. Also, the film thickness is not particularly limited to the examples.

  Subsequently, the formed semiconductor film and n + type silicon film were patterned by a photolithography process and an etching process to form the semiconductor layer 13 and the high concentration contact layer 13d. The resist pattern film remaining after the etching was stripped and removed using a stripping solution.

  This high-concentration contact layer forming step can be omitted.

(Source / drain electrode formation process)
Titanium (Ti), aluminum (Al), titanium is sputtered on the insulating substrate 10 that has undergone the first gate electrode forming step, the first insulating layer forming step, the semiconductor layer forming step, and the high concentration contact layer forming step. The film was formed to a thickness of 100 nm, 200 nm, and 100 nm, respectively, to form a source / drain metal film made of a Ti—Al—Ti metal laminated film.

  Subsequently, the formed source / drain metal film was patterned by a photolithography process and an etching process to form a source electrode 15 and a drain electrode 16.

  When the high-concentration contact layer 13d was formed in the high-concentration contact layer formation step, the resist after etching was used in the next step (source-drain electrode separation step), and thus was not peeled off or removed.

  On the other hand, if the high-concentration contact layer 13d is not formed in the previous step, the source electrode 15 and the drain electrode 16 are separated by patterning, and the resist becomes unnecessary, so that the resist layer is removed. ,Remove.

  In addition, the material which comprises the source electrode 15 and the drain electrode 16 is not limited to the metal of an Example, For example, tungsten (W), copper (Cu), chromium (Cr), tantalum (Ta), molybdenum (Mo ), A single metal such as titanium (Ti), or a material containing nitrogen, oxygen, or another metal in them, or a laminated structure in which a plurality of these materials are combined. It is also possible to make it.

  That is, the source electrode 15 and the drain electrode 16 are made of Mo / Al / Mo laminated film made of molybdenum and aluminum, Ti / Cu / Ti laminated film made of titanium and copper, Mo / Cu / Mo laminated film made of molybdenum and copper, and tantalum. A Ta / TaN / Ta laminated film made of tantalum nitride can be used.

  As a method for forming the source / drain metal film, vapor deposition or the like can be used in addition to sputtering. The film thickness of the source / drain metal film is not particularly limited to the embodiment.

(Source-drain electrode separation process)
This step is performed only when the high concentration contact layer 13d is formed.

  Of the n + type silicon film (high concentration contact layer 13d) and the semiconductor layer 13, a portion not covered with the source electrode 15 and the drain electrode 16 is subjected to an etching process, and the n + type silicon film (high concentration contact layer 13d). The source electrode 15 and the drain electrode 16 were separated from each other by removing.

  After completion of the etching, the resist pattern film was peeled and removed using a stripping solution.

(Second insulating layer forming step)
Plasma enhanced chemical vapor deposition (PECVD) is performed on the insulating substrate 10 through the first gate electrode forming step, the first insulating layer forming step, the semiconductor layer forming step, the high concentration contact layer forming step, and the source / drain electrode forming step. A second insulating layer 17 made of silicon nitride (SiNx) was formed on the entire surface by the method. Here, the film thickness of the second insulating layer 17 was 410 nm. As a film forming gas, a mixed gas of silane (SiH ₄ ), ammonia (NH ₃ ), and nitrogen (N ₂ ) was used.

  As a method for forming the second insulating layer 17, in addition to PECVD, sputtering, vapor deposition, inductively coupled plasma CVD apparatus, microwave CVD apparatus, or electron cyclotron resonance CVD apparatus can be used. The material of the second insulating layer 17 is not particularly limited to the example, and may be a silicon oxide film (SiOx) or the like. Further, the film thickness of the second insulating layer 17 is not limited to the example.

  The second insulating layer 17 protects the channel region 13c after separating the source electrode 15 and the drain electrode 16 in addition to the function as an upper gate insulating film with respect to the second gate electrode 19. It has an important role as a passivation film.

  The second insulating layer 17 is a region corresponding to the channel region 13c, and is affected by a step caused by the source electrode 15 and the drain electrode 16, and a step Hs caused by etching removal of the semiconductor layer 13 (high-concentration contact layer 13d) (see FIG. 4). ) To have a shape having the second insulating layer hole 17h. Details of the second insulating layer hole 17h will be described in the third embodiment.

(Planarization film formation process)
A planarizing film 18 formed of a photosensitive acrylic resin was applied to the entire surface of the insulating substrate 10 that has undergone the second insulating layer forming process by slit coating. The thickness of the planarizing film 18 was 4 μm. Note that the method for applying the planarizing film 18 is not limited to the embodiment, and spin coating, printing, ink jetting, or the like can also be used.

  Further, the material constituting the planarizing film 18 is not limited to the embodiment, but may be SOG (Spin On Glass), polyimide, or the like. Further, the thickness of the planarizing film 18 is not particularly limited to the embodiment.

(Hole formation process)
A contact hole (first contact hole 21, second contact hole 22, second gate electrode hole 23) is formed on the insulating substrate 10 that has undergone the planarization film forming process by a photolithography process using halftone exposure and an etching process. Formed.

  Halftone exposure is an exposure method using an exposure mask (halftone exposure mask) having a light shielding portion for exposure light, a transmission portion for exposure light, and a semi-transmission portion for exposure light. By exposing using a halftone exposure mask, the flattened film 18 (photosensitive acrylic resin) after development is completely removed from the area (light-shielding portion) where the state after application is maintained and the photosensitive acrylic resin is completely removed. The patterned region (transmission portion) and the portion (semi-transmission portion) where the photosensitive acrylic resin is not completely removed and remain slightly are patterned.

  The films to be patterned when forming the three types of holes, the first contact hole 21, the second contact hole 22, and the second gate electrode hole 23, are as follows.

  The first contact hole 21 is a region where the pixel electrode 130 contacts the drain electrode 16, and patterning of the planarizing film 18 by a photolithography process and etching of the second insulating layer 17 using the first contact hole 21 as a mask are performed. is necessary.

  The second contact hole 22 is a region where the second gate electrode 19 is in contact with the first gate electrode 11 (gate signal line 11w), and the planarization film 18 is patterned by a photolithography process, and the second contact hole 22 is masked. Etching of the second insulating layer 17 and the first insulating layer 12 is necessary.

  The second gate electrode hole 23 is a region where the second gate electrode 19 is laminated on the second insulating layer 17, and the second insulating layer 17 must not be removed by etching. That is, the second gate electrode hole 23 formed in the planarizing film 18 cannot be formed in the same manner as the first contact hole 21 and the second contact hole 22.

  Therefore, the region where the second gate electrode hole 23 is formed is exposed by applying the halftone part (semi-transmissive part) of the halftone exposure mask, and after development, the photosensitive acrylic resin is compared with the transmissive part. And keep it thin. That is, when the first contact hole 21 and the second contact hole 22 are formed, a semi-transmissive portion is applied to the second gate electrode hole 23 to prevent the second insulating layer 17 from being exposed.

  A method of forming the first contact hole 21, the second contact hole 22, and the second gate electrode hole 23 will be described with reference to FIGS. 2A to 2D. For convenience of explanation, the first contact hole 21, the second contact hole 22, and the second gate electrode hole 23 may be described for the holes before completion.

  FIG. 2A is an explanatory view for explaining an opening state after development of the planarizing film in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. 2A is an arrow AA shown in FIG. It is a cross-sectional schematic diagram which shows the cross-sectional state in FIG. 1, (B) is a cross-sectional schematic diagram which shows the cross-sectional state in the arrow BB shown to FIG. 1B.

  Of the planarizing film 18 applied to the entire surface of the insulating substrate 10 (insulating substrate 110), the region where the first contact hole 21 is formed and the region where the second contact hole 22 is formed are subjected to normal exposure and development. Thus, the planarizing film 18 is removed. Therefore, the second insulating layer 17 is exposed in the first contact hole 21, and the second insulating layer 17 is exposed in the second contact hole 22.

  At this time, since the half-tone exposure is performed on the region where the second gate electrode hole 23 is formed, the planarization film 18 is not completely removed even after development, and the second insulating layer 17 remains thin. The remaining planarizing film 18r is covered. Therefore, the second insulating layer 17 is not exposed. Since the region where the second gate electrode hole 23 is to be formed is exposed to some extent, a hole with a certain depth can be opened.

  FIG. 2B is an explanatory diagram for explaining a state in which the insulating film is etched using the developed flattening film as a mask in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. It is a cross-sectional schematic diagram which shows the cross-sectional state in the arrow AA shown, (B) is a cross-sectional schematic diagram which shows the cross-sectional state in the arrow BB shown in FIG. 1B.

  Etching in the first contact hole 21 and the second contact hole 22 is performed using the planarizing film 18 remaining after the development as a mask. The second insulating layer 17 exists in the first contact hole 21, and the second insulating layer 17 and the first insulating layer 12 exist in the second contact hole 22 as etching targets.

  Accordingly, the first contact hole 21 and the second contact hole 22 have different etching thicknesses. However, the drain electrode 16 exists under the second insulating layer 17 in the first contact hole 21, and the first gate electrode 11 exists under the second insulating layer 17 and the first insulating layer 12 in the second contact hole 22. Exists.

  Since both the first contact hole 21 and the second contact hole 22 have a metal layer (drain electrode 16 and first gate electrode 11) formed on the lower side, the metal layer and the insulating layer (second insulating layer 17) are formed. The etching of the insulating layer can be stopped with high accuracy by the difference in etching rate with the first insulating layer 12). Therefore, the difference in thickness between the two insulating films to be etched is not a problem, and both can be etched until the metal layer is exposed.

  Therefore, after the insulating layer is etched, the drain electrode 16 is exposed in the first contact hole 21, and the first gate electrode 11 is exposed in the second contact hole 22.

  FIG. 2C shows a state in which the planarized film after development in the method for manufacturing a semiconductor device according to the second embodiment of the present invention is etched back to expose the second insulating layer corresponding to the second gate electrode hole. It is explanatory drawing to explain, (A) is a cross-sectional schematic diagram which shows the cross-sectional state in arrow AA shown in FIG. 1B, (B) is the cross-sectional state in arrow BB shown in FIG. 1B. It is a cross-sectional schematic diagram shown.

  After etching the insulating layers at the two locations (the first contact hole 21 and the second contact hole 22), the planarizing film 18 is further etched back (the thickness of the entire planarizing film 18 is reduced). A two-gate electrode hole 23 is formed, and the second insulating layer 17 is exposed. The second insulating layer 17 has a second insulating layer hole 17h in a region corresponding to the channel region 13c.

  Through the above steps (FIGS. 2A to 2C), the first contact hole 21, the second contact hole 22, and the second gate electrode hole 23 are formed.

  Note that the hole forming process can be performed by applying a conventional photolithography process and etching process that do not use halftone exposure. The process example in that case is shown below.

  First, a region for forming the first contact hole 21 and a region for forming the second contact hole 22 in the planarizing film 18 applied to the entire surface of the insulating substrate 10 by applying a resist and using the first mask. Only exposure and development are performed. Using the resist patterned by development as a mask, the planarizing film 18 is etched to form the first contact hole 21 and the second contact hole 22. Using the planarizing film 18 patterned by etching (opening the first contact hole 21 and the second contact hole 22) as a mask, the insulating layer exposed in the first contact hole 21 and the second contact hole 22 is etched. .

  Next, a resist is applied again, a photolithography process is performed using the second mask, and the planarizing film 18 is etched using a resist patterned by development corresponding to the second gate electrode hole 23 as a mask. . The second gate electrode hole 23 is formed by etching the planarizing film 18 in the region corresponding to the second gate electrode hole 23 until the second insulating layer 17 is exposed. Thereafter, the remaining resist is removed.

  In the above process, when a photosensitive acrylic resin is used as the planarizing film 18, the first resist coating process is unnecessary, and the planarizing film 18 made of a photosensitive acrylic resin is used as a substitute for the resist. It becomes possible.

  The first contact hole 21, the second contact hole 22, and the second gate electrode hole 23 can also be formed by the above general conventional process.

  Each of the two types of hole forming methods described above has advantages. That is, when halftone exposure is used, all contact holes can be formed with one mask, and the number of masks can be reduced. On the other hand, when halftone exposure is not used, the number of masks increases by one, but there is no need to use a special technique called halftone exposure, and contact holes can be formed by a general photolithography process and etching process. The process becomes simple.

(Second gate electrode and pixel electrode forming step)
FIG. 2D is an explanatory view illustrating a state in which the second gate electrode and the pixel electrode are formed in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, and (A) is an arrow A shown in FIG. 1B. It is a cross-sectional schematic diagram which shows the cross-sectional state in -A, (B) is a cross-sectional schematic diagram which shows the cross-sectional state in the arrow BB shown to FIG. 1B.

  The insulating substrate 10 (insulating substrate 110) in which the first contact hole 21, the second contact hole 22, and the second gate electrode hole 23 are formed in the hole forming process is a transparent conductive film by sputtering. A second gate electrode film and a pixel electrode film made of indium tin oxide (ITO) were formed. The film thicknesses of the second gate electrode film and the pixel electrode film were 100 nm.

  Subsequently, the formed second gate electrode film and pixel electrode film were patterned by a photolithography process and an etching process to form the second gate electrode 19 and the pixel electrode 130. After completion of the etching, the resist pattern film was peeled off and removed using a stripping solution.

  The material constituting the second gate electrode 19 and the pixel electrode 130 is not limited to the embodiment, and for example, a transparent conductive film such as zinc oxide (ZnO), tungsten (W), copper (Cu), chromium (Cr ), A single metal such as tantalum (Ta), molybdenum (Mo), titanium (Ti), or a material containing nitrogen, oxygen, or another metal in them may be used to form a single layer, Further, a laminated structure in which a plurality of these materials are combined may be used.

  That is, the second gate electrode 19 and the pixel electrode 130 are a Ti / Al / Ti laminated film of titanium and aluminum, a Mo / Al / Mo laminated film of molybdenum and aluminum, a Ti / Cu / Ti laminated film of titanium and copper, copper And a Mo / Cu / Mo laminated film made of molybdenum and a Ta / TaN / Ta laminated film made of tantalum and tantalum nitride (TaN).

  The transparent conductive film referred to in this embodiment is a film having a sheet resistance of 100 Ω / □ or less and a transmittance of 50% or more (less than 100%) in the visible light region (wavelength 380 to 780 nm). If it is this range, it can be used as a transparent conductive material, and can function as a transparent electrode.

  Note that the second gate electrode film and the pixel electrode film can be formed by vapor deposition or the like in addition to sputtering. Further, the thicknesses of the second gate electrode film and the pixel electrode film are not particularly limited to the examples.

<Embodiment 3>
The semiconductor device according to the present embodiment will be described with reference to FIG. Note that the basic configuration of the semiconductor device according to the present embodiment is the same as that of the semiconductor device 1 of the first and second embodiments, and therefore, reference numerals are used to refer to the first and second embodiments. What is different is mainly explained.

  FIG. 3 is a schematic cross-sectional view schematically showing the cross-sectional state of the main part of the semiconductor device according to the third embodiment of the present invention. The position of the cross section is in the vicinity of the second insulating layer hole 17h shown in FIG.

  In the semiconductor device 1 according to the present embodiment, the second insulating layer 17 includes the second insulating layer hole 17h in which the second gate electrode 19 is fitted between the source electrode 15 and the drain electrode 16, and the second insulating layer 17 is provided with the second insulating layer hole 17h. The side surface of the layer hole 17h has a projecting portion 17p projecting in the center direction, and the projecting portion 17p has a projecting length Lp of 5 nm or more with respect to the end of the bottom surface of the second insulating layer hole 17h.

  Accordingly, since the second gate electrode 19 is pinned to the constriction formed below the protrusion 17p of the second insulating layer hole 17h, the second insulating layer 17 and the second gate electrode It is possible to improve the adhesion between the second gate electrode 19 and the film peeling of the second gate electrode 19, thereby improving the yield and reliability.

  When the configuration of the semiconductor device 1 according to the present embodiment is not employed, the semiconductor device 1 according to the first embodiment has poor adhesion between the second insulating layer 17 and the second gate electrode 19, and the second gate electrode 19. There were places where film peeling occurred. That is, the yield may be low.

  When the transparent conductive material (the second gate electrode 19 and the pixel electrode 130) is peeled off from the lower layer of the pixel electrode 130 when one side has a large area of, for example, 100 μm or more like the pixel electrode 130 of the TFT substrate 100, It was not a problem because the adhesion could be secured.

  However, in the semiconductor device 1 (double gate TFT) according to the first embodiment, since a transparent conductive material is used as the upper electrode (second gate electrode 19), the area is smaller than that of the conventional case, that is, one side is 100 μm. The step (the second insulating layer hole 17h) is present in a shape that has never been reported so far. As a result, the problem that the film peeling of the transparent conductive material, which has not been a problem until now, has become apparent. The semiconductor device 1 according to the present embodiment has solved the problem.

  As a result of observing the cross section of the semiconductor device 1 manufactured in the first embodiment with a scanning electron microscope (SEM), the cross section of the second insulating layer 17 corresponding to the channel region 13c has a concave shape and the second insulating layer hole. It was found to have 17h. That is, at the interface between the second insulating layer 17 and the second gate electrode 19 in the second insulating layer hole 17h, the second insulating layer 17 is in contact with the bottom surface of the second gate electrode hole 23 (second insulating layer hole 17h). The side surface has a protrusion 17p that protrudes toward the center of the hole.

  In the semiconductor device 1 according to the first embodiment, the protruding portion 17p has a protruding length Lp of 3 nm with respect to the end portion of the bottom surface of the second insulating layer hole 17h. In the first embodiment, the temperature of the insulating substrate 10 when forming the second insulating layer 17 was 300 ° C., and the defect rate due to film peeling of the second gate electrode 19 was 0.01%. The short side length of the second gate electrode 19 was 10 μm.

  In the semiconductor device 1 according to the present embodiment, the second insulating layer 17 is formed with the temperature of the insulating substrate 10 set at 250 ° C. As a result, the protrusion length Lp was 7 nm, and the defect rate due to film peeling of the transparent conductive material was reduced to 0.001%.

  That is, when the second insulating layer 17 is formed, the protruding length Lp (neck shape) of the protruding portion 17p formed in the second insulating layer hole 17h can be adjusted by controlling the film forming conditions. Therefore, the shape in which the second gate electrode 19 formed on the second insulating layer 17 (second insulating layer hole 17h) is bitten into the constriction formed below the projecting portion 17p of the second insulating layer hole 17h. As a result, film peeling of the second gate electrode 19 could be suppressed.

  Specifically, the semiconductor device 1 (double gate type TFT) is manufactured by changing the temperature of the insulating substrate 10 when the second insulating layer 17 and the second gate electrode 19 are formed, and the protruding length Lp, the insulating property is obtained. The temperature of the substrate 10 and the defect rate due to film peeling of the transparent conductive material were measured.

  As a result of measurement, by setting the protrusion length Lp to 5 nm or more, the second gate electrode 19 can be pinned with respect to the bottom surface and the side wall of the second insulating layer 17 (second insulating layer hole 17h). Thus, the adhesion between the second insulating layer 17 and the second gate electrode 19 was improved, and the defect rate due to film peeling of the transparent conductive material could be remarkably reduced to 0.001% or less.

  In addition, since the temperature of the insulating substrate 10 largely depends on the apparatus to be used and other conditions, it is not limited to the temperature of the embodiment.

  In addition, as a method of setting the protrusion length Lp to 5 nm or more, a method of increasing the RF power of a PECVD apparatus for forming a film or a sputtering apparatus, a technique of reducing the partial pressure of silane gas, or the like may be used. There is no limit.

  That is, if the protrusion length Lp is 5 nm or more, a pinning effect can be sufficiently generated, and the defect rate due to film peeling of the second gate electrode 19 can be reduced.

  Note that it is possible to prevent the influence of the level generated on the surface of the semiconductor layer 13 by forming the silicon oxide film 14 on the surface of the semiconductor layer 13. Details of the silicon oxide film 14 will be further described in the sixth embodiment.

<Embodiment 4>
A semiconductor device according to the present embodiment will be described with reference to FIG. Note that the basic configuration of the semiconductor device according to the present embodiment is the same as that of the semiconductor device 1 of the first to third embodiments, and therefore, the reference numerals are used to refer to the first to third embodiments. What is different is mainly explained.

  FIG. 4 is a schematic cross-sectional view schematically showing the cross-sectional state of the main part of the semiconductor device according to the fourth embodiment of the present invention. The position of the cross section is in the vicinity of the source electrode 15 shown in FIG. Further, the drain electrode 16 is omitted from the drawing because it is formed symmetrically with the source electrode 15.

  In the semiconductor device 1 according to the present embodiment, the source electrode 15 and the drain electrode 16 are joined to the surface of the semiconductor layer 13, and the semiconductor layer 13 is thinned in the channel region 13 c between the source electrode 15 and the drain electrode 16. The channel step Hs is 10 nm or more and 200 nm or less.

  Therefore, since the channel step Hs is set to 10 nm or more, the influence of residue variations on the surface of the channel region 13c (semiconductor layer 13) thinned by etching is suppressed, and the channel step Hs is set to 200 nm or less. It is possible to suppress a decrease in on-current due to an increase in the distance between the channel region 13c and the source electrode 15 and the distance between the channel region 13c and the drain electrode 16.

  In the semiconductor device 1 according to the present embodiment, in order to facilitate the ohmic contact between the semiconductor layer 13 and the source electrode 15 and between the semiconductor layer 13 and the drain electrode 16, a high concentration contact is formed after the semiconductor film is formed. After the film (n + type silicon film) is formed, the source electrode 15 and the drain electrode 16 are formed, and channel etching is performed using the source electrode 15 and the drain electrode 16 as a mask (channel etching process), whereby the high concentration contact layer 13d ( n + type contact layer) was formed.

  Since the n + type silicon film is a conductor, in order to insulate between the source electrode 15 and the drain electrode 16, channel etching for removing the n + type silicon film in the region corresponding to the channel region 13c is necessary. .

  In the semiconductor device 1 (double gate TFT) according to the first embodiment, the channel step Hs (upper surface step) of the semiconductor layer 13 due to channel etching of the channel region 13c of the semiconductor layer 13 is 8 nm, As a result of many cross-sectional and surface observations of the semiconductor layer 13 by SEM, the residue of the n + -type silicon film may exist on the surface of the semiconductor layer 13, and the semiconductor device 1 in which the off operation cannot be realized may occur. .

  In the semiconductor device 1 according to the present embodiment, it is possible to remove the residue of the n + -type silicon film by setting the channel step Hs of the semiconductor layer 13 by channel etching to 10 nm or more.

The on-current of the semiconductor device 1 according to the present embodiment exceeds the on-current of the semiconductor device 1 in the first embodiment, and is 9.65, which is about 1.7 times that of the conventional reverse stagger type TFT measured in the comparative example. × 10 ^-7 A.

  On the other hand, when the channel step Hs of the semiconductor layer 13 by channel etching is made thicker than 200 nm, the problem of the residue of the n + -type silicon film does not occur, but the surface of the semiconductor layer 13 that becomes the channel region 13c, the source electrode 15 and the drain electrode Since the distance to 16 increases, the channel resistance increases, resulting in a decrease in on-current.

  Therefore, by controlling the channel step Hs of the semiconductor layer 13 by channel etching within a range of 10 nm or more and 200 nm or less, the semiconductor device 1 (channel etching type double gate TFT) having a large on-state current can be manufactured.

  Even when the high concentration contact layer 13 d is not formed, a source / drain metal film residue may be generated on the surface of the channel region 13 c of the semiconductor layer 13 after the patterning of the source electrode 15 and the drain electrode 16. Even in such a case, similarly, the same effect can be obtained by controlling the channel step Hs of the semiconductor layer 13 in the channel region 13c.

  Details of the film thickness Tc in the channel region 13c of the semiconductor layer 13 will be further described in the seventh embodiment.

<Embodiment 5>
In Embodiment 2 (Embodiment 1), semiconductor device 1 (double-gate TFT) is manufactured using amorphous silicon for semiconductor layer 13. In the semiconductor device 1 according to the first embodiment, the channel region 13c is formed on both upper and lower sides of the semiconductor layer 13 by adopting a double gate structure. Therefore, the on-current can be increased as compared with the conventional inverted stagger type TFT. However, since the mobility of amorphous silicon is as small as about 0.5 cm ² / (V · s), the possibility of further increasing the on-current was examined.

  In this embodiment, in order to further increase the on-current, the semiconductor device 1 (double-gate TFT) using a semiconductor film whose main component is microcrystalline silicon having a mobility higher than that of amorphous silicon is used as the semiconductor layer 13. Produced. Note that the microcrystalline silicon film in this embodiment means a film containing silicon crystal grains of 5 nm or more as a main component in the film.

  Since the basic configuration of the semiconductor device according to the present embodiment is the same as that of the semiconductor device 1 of the first to fourth embodiments, the reference numerals are used and are different from the first to fourth embodiments. The matter is mainly explained.

The formed microcrystalline silicon film (semiconductor layer 13) had a mobility of about 0.6 cm ² / (V · s) on the lower surface side (first insulating layer 12 side) at the initial stage of film growth, The mobility on the upper surface side (second insulating layer 17 side) was about 1.0 cm ² / (V · s). The reason why the mobility on the upper surface side is larger than the lower surface side is considered to be because the crystal grains increase as the film thickness increases.

  In a normal inverted stagger type TFT, the upper surface side with high mobility cannot be used. Therefore, even when microcrystalline silicon is used for the semiconductor layer 13, the on-current is increased to some extent, and the on-current is large. The increase was not obtained, and the advantage of using microcrystalline silicon as the channel region 13c could not be fully utilized.

That is, microcrystalline silicon has a good film quality, and unless the upper surface side having high mobility is used as the channel region 13c, the advantages cannot be fully utilized. Since the semiconductor device 1 according to the present embodiment is a double-gate TFT, the channel region is formed not only on the lower surface side of the microcrystalline silicon layer but also on the upper surface side of the microcrystalline silicon layer having good film quality and high mobility. In the semiconductor device 1 according to the present embodiment capable of forming 13c, the on-current is 1.23 × 10 ⁻⁶ A, which is about 2.2 times that of the conventional inverted staggered amorphous silicon TFT.

  As described above, in the semiconductor device 1 according to the present embodiment, the semiconductor layer 13 is mainly composed of microcrystalline silicon. Therefore, since microcrystalline silicon having a high mobility can be used as the channel region 13c on the surface side (upper surface side) of the semiconductor layer 13 that cannot be used with a normal inverted staggered TFT, a large on-current can be extracted.

  Next, a microcrystalline silicon formation process for forming the microcrystalline silicon film (semiconductor layer 13) will be described.

  The microcrystalline silicon formation step is a step performed as the semiconductor layer formation step described in Embodiment 2. Microcrystalline silicon is formed on the insulating substrate 1 that has undergone the first gate electrode forming step and the first insulating layer forming step by using another film forming chamber in the film forming apparatus used in the first insulating layer forming step that is the previous step. A film was formed.

Specifically, using a film formation chamber having a parallel plate type (capacitive coupling type) electrode structure, the temperature of the insulating substrate 10 is set to 300 ° C., the pressure is 50 to 300 Pa, and the power density is 5 to 15 mW / cm ² . It was. Further, silane (SiH ₄ ) and hydrogen (H ₂ ) were used as the film forming gas, and the flow rate ratio of silane and hydrogen was 1:50 to 1: 100, and the film was formed under hydrogen dilution conditions. The film thickness of the microcrystalline silicon film was 230 nm.

  Note that in addition to the PECVD method, an inductively coupled plasma CVD apparatus, a microwave CVD apparatus, or an electron cycloton resonance CVD apparatus can be used as a method for forming the microcrystalline silicon film. The thickness of the microcrystalline silicon film is not particularly limited to the embodiment.

<Embodiment 6>
The basic configuration of the semiconductor device and the manufacturing method of the semiconductor device according to the present embodiment is the same as that of the semiconductor device 1 and the manufacturing method of the semiconductor device of Embodiments 1 to 5, and therefore, the reference numerals are used. Differences from the first to fifth embodiments will be mainly described.

  In the semiconductor device 1 according to the first embodiment, when a high-concentration contact film (n + type silicon film) is formed, the surface of the semiconductor layer 13 is exposed to an etching gas during channel etching, so that the surface of the semiconductor layer 13 is exposed. A level was formed. On the other hand, when channel etching was not performed, levels were similarly formed on the surface of the semiconductor layer 13 by the etching process when forming the source electrode 15 and the drain electrode 16.

  In the semiconductor device 1 in which the second insulating layer 17 is formed in a state where a level is formed on the surface of the semiconductor layer 13, a decrease in on-current due to a decrease in mobility caused by the level occurs.

In the semiconductor device 1 according to the present embodiment, the level of the semiconductor layer 13 can be reduced by forming the silicon oxide film 14 (see FIG. 3) thin on the semiconductor layer 13. As a result, the decrease in mobility was suppressed, and the on-current was 8.57 × 10 ⁻⁷ A, which is about 1.5 times that of the conventional TFT.

  As described above, the semiconductor device 1 according to the present embodiment includes the silicon oxide film 14 between the semiconductor layer 13 and the second insulating layer 17. Therefore, the level formed on the surface of the semiconductor layer 13 can be reduced, so that a decrease in mobility due to the presence of the level can be suppressed.

  A silicon oxide film forming process for forming the silicon oxide film 14 on the surface of the semiconductor layer 13 will be described below.

  In the silicon oxide film forming step, the silicon oxide film 14 is formed on the surface of the semiconductor layer 13 formed by the semiconductor layer forming step described in the second embodiment (or the microcrystalline silicon forming step described in the fifth embodiment). It is a process to do.

  The silicon oxide film forming step is a step immediately before forming the second insulating layer 17. Therefore, if the same film forming apparatus as that used for forming the second insulating layer 17 is used and the formation of the silicon oxide film 14 and the formation of the second insulating layer 17 can be performed in succession, The silicon oxide film 14 is formed on the surface of the semiconductor layer 13 while suppressing the increase in cost due to the addition and the increase in the time for carrying in / out the insulating substrate 10, thereby improving the transistor characteristics.

  As a specific example of the silicon oxide film forming step, by oxidizing the surface of the semiconductor layer 13 with plasma using oxygen or a gas containing an oxygen element in a chamber used when the second insulating layer 17 is formed. The silicon oxide film 14 can be formed.

In the examples using plasma, experiments were performed by a method of performing oxidation treatment with N ₂ O gas at RF power of 1200 W for 30 seconds and a method of performing oxidation treatment with O ₂ gas at RF power of 1200 W for 30 seconds. . The film thickness obtained by these oxidation treatments was 0.3 nm to 1 nm.

  In addition, since the silicon oxide film forming step is a step immediately before the second insulating layer 17 is formed, as another specific example of the silicon oxide film forming step, a cleaning step before forming the second insulating layer 17 is performed. In addition, the silicon oxide film 14 can be formed by performing an oxidation process on the surface of the semiconductor layer 13 using ozone water.

  In the embodiment using cleaning, a silicon oxide film 14 is formed on the surface of the semiconductor layer 13 while suppressing an increase in cost due to the addition of an apparatus and an increase in time for carrying in / out the insulating substrate 10, thereby improving transistor characteristics. It becomes possible to improve.

   The ozone water used in the cleaning was an ozone concentration of about 5 ppm to 50 ppm, and the water temperature was 23 ° C. The processing time was 30 seconds.

As described above, the manufacturing method of the semiconductor device according to the present embodiment includes the first gate electrode 11 formed on the insulating substrate 10 and the first insulating layer 12 formed on the first gate electrode 11. A semiconductor layer 13 formed on the first insulating layer 12, a source electrode 15 connected to one end of the semiconductor layer 13, and a drain connected to the other end of the semiconductor layer 13 opposite the source electrode 15 Between the electrode 16, the second insulating layer 17 formed on the semiconductor layer 13, the second gate electrode 19 formed on the second insulating layer 17, and between the semiconductor layer 13 and the second insulating layer 17 The silicon oxide film 14 (silicon oxide film 14 formed on the surface of the semiconductor layer 13) is formed, and at least one of the first gate electrode 11 and the second gate electrode 19 is formed of a transparent conductive material. Manufacturing semiconductor device 1 Semiconductor device manufacturing method.

Moreover, the method of manufacturing a semiconductor device according to this embodiment, the silicon oxide film 14 is formed by performing oxidation treatment with plasma using a gas containing oxygen or oxygen element on the surface of the semiconductor layer 13. Therefore, when the second insulating layer 17 is formed by a CVD apparatus, it is possible to perform an oxidation process using plasma as a pre-process in the same apparatus, so that silicon can be easily formed without adding a manufacturing apparatus. The oxide film 14 can be manufactured.

Moreover, the method of manufacturing a semiconductor device according to this embodiment, the silicon oxide film 14 is formed by performing oxidation treatment using ozone water on the surface of the semiconductor layer 13. Therefore, when the cleaning process is performed by the wet cleaning apparatus before the second insulating layer 17 is formed, it can be simultaneously performed by the same cleaning apparatus. Therefore, the silicon oxide film can be easily formed without adding a manufacturing apparatus. 14 can be manufactured.

<Embodiment 7>
Since the basic configuration of the semiconductor device according to the present embodiment is the same as that of the semiconductor device 1 of the first to sixth embodiments, the reference numerals are used and are different from the first to sixth embodiments. The matter is mainly explained.

  In the semiconductor device 1 according to the present embodiment, the film thickness Tc (see FIG. 4) of the channel region 13c is not less than 10 nm and not more than 1000 nm. Therefore, since the stable film quality can be obtained by setting the film thickness Tc of the semiconductor layer 13 in the channel region 13c to 10 nm or more, it becomes possible to ensure the stability of transistor characteristics, and the film thickness Tc to 1000 nm or less. By doing so, an increase in the deposition time of the semiconductor layer 13 can be suppressed.

  In Embodiment 1, when the film thickness Tc of the channel region 13c (semiconductor layer 13) after channel etching is less than 10 nm, the unstable part of the film quality at the initial stage of growth occupies most of the film. When the semiconductor device 1 (double-gate TFT) is manufactured with the semiconductor layer 13, the threshold voltage Vth varies in the range from 3.3 V to 4.8 V, and the standard deviation at that time is 0.40, and the transistor characteristics are It was unstable.

  When the semiconductor device 1 (double gate TFT) is manufactured by increasing the film thickness Tc of the channel region 13c (semiconductor layer 13) after channel etching in order to eliminate the variation in the threshold voltage Vth, the film thickness is set to 10 nm or more. By doing so, transistor characteristics could be stabilized.

  Actually, as a result of manufacturing the semiconductor device 1 by setting the film thickness Tc of the channel region 13c (semiconductor layer 13) after channel etching to 10 nm, the variation of the threshold voltage Vth is in the range from 3.7V to 4.3V. The standard deviation of was 0.17. The number of samples used for the measurement is 132.

  When the film thickness Tc of the semiconductor layer 13 was in the range of 10 nm or more, the transistor characteristics did not deteriorate (the threshold voltage Vth varied) due to the increase of the film thickness Tc. However, considering the time required for forming the semiconductor layer 13 (channel region 13c), the film thickness Tc is desirably 1000 nm or less.

<Eighth embodiment>
Since the basic configuration of the semiconductor device according to the present embodiment is the same as that of the semiconductor device 1 of the first to seventh embodiments, the reference numerals are used and are different from the first to seventh embodiments. The matter is mainly explained.

  In the semiconductor device 1 according to the present embodiment, the first insulating layer 12 and the second insulating layer 17 have the same main component. Therefore, since the same material can be used for the material used for forming the first insulating layer 12 and the second insulating layer 17, the gas used for etching, and the etching material, the increase in cost due to the addition of materials in the manufacturing process can be suppressed. It becomes possible.

  In the first insulating layer forming step and the second insulating layer forming step described in the second embodiment, various combinations of materials can be considered, and the semiconductor device 1 (double gate type TFT) is actually manufactured and operated. Is possible.

  However, when materials having different main components are used for the first insulating layer 12 and the second insulating layer 17, additional costs such as film materials and gases and materials used for etching are required. Therefore, by making the main components of the first insulating layer 12 and the second insulating layer 17 the same, it is possible to avoid an increase in cost.

<Embodiment 9>
The basic structure of a manufacturing method of a semiconductor device according to this embodiment, the semiconductor device 1 of Embodiment 1 to Embodiment 8 of the embodiment is the same as the manufacturing method of the semiconductor device, the aid of codes, the implementation Items different from Embodiment 1 to Embodiment 8 will be mainly described.

The method for manufacturing a semiconductor device according to the present embodiment includes a first gate electrode 11 formed on an insulating substrate 10, a first insulating layer 12 formed on the first gate electrode 11, and a first A semiconductor layer 13 formed on the insulating layer 12, a source electrode 15 connected to one end of the semiconductor layer 13, a drain electrode 16 facing the source electrode 15 and connected to the other end of the semiconductor layer 13, A second insulating layer 17 formed on the semiconductor layer 13 and a second gate electrode 19 formed on the second insulating layer 17, and at least one of the first gate electrode 11 and the second gate electrode 19. Is a semiconductor device manufacturing method for manufacturing the semiconductor device 1 formed of a transparent conductive material.

Moreover, the method of manufacturing a semiconductor device according to this embodiment, before forming the second insulating layer 17 on the semiconductor layer 13, the semiconductor layer using an alkaline chemical solution containing tetramethylammonium hydroxide 13 Clean the surface.

  Therefore, since it becomes possible to remove the damaged layer formed on the surface of the semiconductor layer 13, the characteristic variation of the semiconductor device 1 (double gate TFT) can be suppressed.

  When the surface of the semiconductor layer 13 was observed before the second insulating layer forming step described in the second embodiment, the channel etching step, which is the previous step of the second insulating layer forming step, or the source electrode 15 and the drain electrode was performed. It was found that the damaged layer was formed by the etching process when forming 16 (source electrode / drain electrode forming process).

  When the second insulating layer 17 is formed in a state where the damaged layer is present and the semiconductor device 1 (double gate type TFT) is manufactured, the threshold voltage Vth greatly varies in the base material (wafer) plane of the insulating substrate 10, The threshold voltage Vth was 3.4 V to 4.8 V, and the standard deviation at that time was 0.41.

  In the present embodiment, the cleaning step after channel etching is performed when the high concentration contact layer 13d is formed, and the etching step when the source electrode 15 and the drain electrode 16 are formed when the high concentration contact layer 13d is not formed. In the cleaning process, the surface of the semiconductor layer 13 is cleaned with an alkaline chemical solution containing TMAH (tetramethylammonium hydroxide) that can provide a large etching selectivity between the semiconductor layer 13 and the source electrode 15 and drain electrode 16. went. The damage layer formed on the surface of the semiconductor layer 13 could be removed by etching the surface of the semiconductor layer 13 by about 20 nm by a cleaning treatment with an alkaline chemical solution.

  As a result of removing the damaged layer on the surface of the semiconductor layer 13, the threshold voltage Vth, which had a large variation, was 3.7V to 4.4V, and the standard deviation at that time was 0.19. That is, variation in the base material (wafer) plane of the insulating substrate 10 with the threshold voltage Vth could be suppressed. The number of samples used for the measurement is 132.

  The cleaning process according to the present embodiment can be added to the cleaning process after the source electrode 15 and the drain electrode 16 are formed in the conventional source electrode / drain electrode forming process, and thus requires an additional device. There is also an advantage that the transistor characteristics are not increased, and it is possible to suppress variations in transistor characteristics while suppressing an increase in cost.

  The alkaline chemical solution containing TMAH used in the present embodiment is an aqueous solution containing 5% by weight of TMAH, 1% by weight of silicon, and 1% by weight of ammonium persulfate as an oxidizing agent, and the temperature of the chemical solution is 50 ° C. The process was performed.

  The components contained in the alkaline chemical containing TMAH have the following effects. TMAH adjusts the etching rate, silicon adjusts the etching rate and secures the etching selectivity between the damaged layer and the metal film such as aluminum, and ammonium persulfate secures the etching selective ratio between the damaged layer and the metal film such as aluminum and etches It stabilizes the surface condition and affects the transistor characteristics. Further, the etching rate can be adjusted by the chemical temperature.

  These processing conditions can be appropriately adjusted in consideration of the etching rate and device characteristics. That is, it is not limited to the conditions of an Example. For example, the chemical solution temperature may be 10 ° C. to 90 ° C., the TMAH concentration may be 0.1 wt% to 25 wt%, the silicon concentration may be 0.1 wt% to 25 wt%, and ammonium persulfate is 0.1 wt% It may be from 20% to 20% by weight.

  In addition to ammonium persulfate, ammonium phosphate, ammonium nitrate and the like can be used as the oxidizing agent.

<Embodiment 10>
The TFT substrate according to the present embodiment will be described with reference to FIGS. 5 to 6B. The TFT substrate is obtained by forming a thin film transistor (TFT) on an insulating substrate. The insulating substrate corresponds to the insulating substrate 10 (insulating substrate 110) in the first to ninth embodiments. Corresponds to the semiconductor device 1 (double-gate TFT) in the first to ninth embodiments. Therefore, the matters different from the first to ninth embodiments are mainly described with reference to the reference numerals.

  FIG. 5 is a schematic plan view schematically showing a planar state of the TFT substrate according to Embodiment 10 of the present invention.

  The TFT substrate 100 according to the present embodiment includes an insulating substrate 110, a display pixel electrode 130 formed on the insulating substrate 110, and the pixel electrode 130 formed on the insulating substrate 110 (insulating substrate 10). It has a thin film transistor as a pixel transistor 101 for controlling a voltage to be applied. A thin film transistor as the pixel transistor 101 is the semiconductor device 1 described in any of Embodiments 1 to 9.

  Therefore, since the semiconductor device 1 (double gate TFT) having a large on-state current is used as the pixel transistor 101, the pixel electrode 130 can be driven by the low-resistance pixel transistor 101, and a large screen display can be performed at high speed. The TFT substrate 100 can be obtained.

  In recent years, there is an increasing demand for high-speed driving for display pixels. By increasing the on-current of the thin film transistor (decreasing the on-resistance), the thin film transistor can be used as a pixel transistor 101 for a liquid crystal display, an organic EL display, or the like that is driven at a high speed, for example, a double speed, a quadruple speed, or an eight times speed drive.

  Since the semiconductor device 1 (double-gate TFT) disclosed in the first to ninth embodiments has a large on-current, the semiconductor device 1 as the pixel transistor 101 is formed in the pixel transistor region 101a. The TFT substrate 100 can be driven at high speed.

  According to this embodiment, since the semiconductor device 1 having a large on-state current is used as the pixel transistor 101, a low-resistance thin film transistor can be realized. Therefore, the TFT substrate 100 that can be driven at higher speed can be obtained.

  A source driver circuit 140 s connected to the source of the pixel transistor 101 and a gate driver circuit 140 g connected to the gate of the pixel transistor 101 are externally attached to the outer peripheral edge of the insulating substrate 110. Note that the gate driver circuit 140g and the source driver circuit 140s may be simply referred to as the driver circuit 140 when it is not necessary to distinguish between them.

  FIG. 6A is a schematic plan view schematically showing a planar state of the TFT substrate (Modification 1) according to Embodiment 10 of the present invention.

  In the TFT substrate 100 shown in FIG. 5, the driver circuit 140 is externally attached. On the other hand, in this modification, the semiconductor device 1 is applied not only to the pixel transistor 101 but also to the driver circuit 140.

  That is, the TFT substrate 100 according to this embodiment includes an insulating substrate 110, a display pixel electrode 130 formed on the insulating substrate 110, and a pixel electrode formed on the insulating substrate 110 (insulating substrate 10). 130 includes a thin film transistor as a pixel transistor 101 that controls a voltage applied to 130 and a driver transistor 141 that is formed on the insulating substrate 110 and controls the pixel transistor 101. The thin film transistor as the pixel transistor 101 and the driver transistor 141 are The semiconductor device 1 according to any one of Embodiments 1 to 9 is configured.

  The driver circuit 140 includes a source driver circuit 140s and a gate driver circuit 140g. In this modification, a source driver transistor 141s (semiconductor device 1) is formed for the source driver circuit 140s, and a gate driver transistor 141g (semiconductor device 1) is formed for the gate driver circuit 140g. Note that the driver transistor 141 may be simply referred to when the source driver transistor 141s and the gate driver transistor 141g do not need to be distinguished from each other.

  Therefore, since the semiconductor device 1 (double gate TFT) having a large on-current is used as the driver transistor 141 of the driver circuit 140, the area occupied by the driver circuit 140 in the insulating substrate 110 can be reduced. That is, the TFT substrate 100 in which the area of the pixel transistor region 101a with respect to the area of the insulating substrate 110 is increased to improve the display area ratio can be obtained.

  Note that the driver transistor 141 can also be applied to only one of the source driver circuit 140s and the gate driver circuit 140g, and in this case also, the area occupied by the driver circuit 140 can be reduced.

  Note that the conventional inverted staggered amorphous silicon TFT has a low on-current, and therefore cannot be used as the driver circuit 140 (gate driver circuit 140g, source driver circuit 140s). That is, it is impossible to form the pixel transistor 101 on the same insulating substrate 110.

  The semiconductor device 1 (double gate TFT) according to the first to ninth embodiments has a large on-current. Therefore, the TFT substrate 100 includes not only the semiconductor device 1 as the pixel transistor 101 in the pixel transistor region 101a but also the semiconductor device 1 formed in the driver circuit 140 as the driver transistor 141 that drives and controls the pixel transistor 101. Is possible. That is, in the TFT substrate 100, the pixel transistor 101 (semiconductor device 1) and the driver transistor 141 (semiconductor device 1) can be mounted on the insulating substrate 110 in a small area.

  FIG. 6B is a schematic plan view schematically showing a planar state of the TFT substrate (Modification 2) according to Embodiment 10 of the present invention.

  In this modification, the area of the driver circuit 140 shown in FIG. 6A is reduced.

  That is, when the on-current is increased by X times, the channel width W of the transistor (semiconductor device) can be increased by 1 / X times. Therefore, the semiconductor according to the first to ninth embodiments having a large on-current. By using the device 1 (double gate type TFT), the area occupied by the driver circuit 140 in which the driver transistor 141 is disposed can be reduced, and the TFT substrate 100 in which the area of the driver circuit 140 is reduced can be obtained. .

<Embodiment 11>
Based on FIG. 7, a display device according to the present embodiment will be described. The display device includes the TFT substrate 100 described in the tenth embodiment. Therefore, the matters different from the first to tenth embodiments are mainly described with reference to the reference numerals.

  FIG. 7 is a schematic front view schematically showing the front state of the display device according to Embodiment 11 of the present invention.

  The display device 200 according to the present embodiment includes a TFT substrate 100 having a display pixel electrode 130. The TFT substrate 100 is the TFT substrate 100 of the tenth embodiment.

  Therefore, since the semiconductor device 1 (double-gate TFT) having a large on-current is used as the pixel transistor 101 or the driver transistor 141, a large screen display is possible, and the area of the pixel transistor region is increased with respect to the area of the insulating substrate. It can be set as the display apparatus 200 which improved the area ratio.

  Examples of the display device 200 using the TFT substrate 100 to which the semiconductor device 1 is applied include a liquid crystal display and an organic EL display.

  Since the on-current of the semiconductor device 1 (double gate TFT) is large, the TFT substrate 100 can be enlarged. In addition, the driver circuit 140 (see FIG. 5), which has conventionally been an external component, can be formed on the insulating substrate 110 as the driver transistor 141 simultaneously with the pixel transistor 130 with a small area. Therefore, a large-screen display device using the TFT substrate 100 in which the pixel transistor 130 and the driver transistor 141 are mixedly mounted can be obtained.

  Since the TFT substrate 100 applied to this embodiment includes the low-resistance semiconductor device 1, the display device 200 including the driver circuit 140 having a larger screen or a smaller area can be obtained.

  As mentioned above, embodiment and the Example which concern on this invention are illustrations, Comprising: The scope of the present invention is not restricted to Embodiment and Example.

1 Semiconductor devices (thin film transistors / pixel transistors)
DESCRIPTION OF SYMBOLS 10 Insulating substrate 11 1st gate electrode 11w Gate signal line 12 1st insulating layer 13 Semiconductor layer 13c Channel area | region 13d High concentration contact layer 14 Silicon oxide film 15 Source electrode 15w Source signal line 16 Drain electrode 17 2nd insulating layer 17h 1st 2 Insulating layer hole 17p Protruding portion 18 Planarizing film 18r Residual planarizing film 19 Second gate electrode 21 First contact hole 22 Second contact hole 23 Second gate electrode hole 100 TFT substrate 101 Pixel transistor (thin film transistor)
101a Pixel transistor region 110 Insulating substrate 130 Pixel electrode 140 Driver circuit 140g Gate driver circuit 140s Source driver circuit 141 Driver transistor (semiconductor device / thin film transistor)
141 g Gate driver transistor 141 s Source driver transistor 200 Display device Hs Channel step Lp Projection length Tc Film thickness

Claims (5)

A first gate electrode formed on an insulating substrate, a first insulating layer formed on the first gate electrode, a semiconductor layer formed on the first insulating layer, and the semiconductor layer A source electrode connected to one end of the semiconductor layer, a drain electrode facing the source electrode and connected to the other end of the semiconductor layer, a second insulating layer formed on the semiconductor layer, and the second insulation A semiconductor device comprising: a second gate electrode formed on a layer; and a channel region formed in the semiconductor layer between the source electrode and the drain electrode,
At least one of the first gate electrode and the second gate electrode is formed of a transparent conductive material ,
The second insulating layer includes a second insulating layer hole in which the second gate electrode is fitted between the source electrode and the drain electrode, and a side surface of the second insulating layer hole protrudes in a central direction. And the protrusion has a protrusion length of 5 nm or more with respect to the end of the bottom surface of the second insulating layer hole . The semiconductor device according to claim 1 ,
The source electrode and the drain electrode are joined to a surface of the semiconductor layer, and the semiconductor layer is thinned in the channel region between the source electrode and the drain electrode to have a channel step, It is 10 nm or more and 200 nm or less. The semiconductor device according to claim 1 or 2 , wherein
The semiconductor device is characterized in that the main component is microcrystalline silicon. A TFT substrate having an insulating substrate, a pixel electrode for display formed on the insulating substrate, and a thin film transistor as a pixel transistor formed on the insulating substrate and controlling a voltage applied to the pixel electrode. ,
The thin film transistor, TFT substrate which is a semiconductor device according to any one of claims 1 to 3. A display device comprising a TFT substrate having a pixel electrode for display,
The display device according to claim 4 , wherein the TFT substrate is the TFT substrate according to claim 4 .

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