JP5259383B2 - Semiconductor device and semiconductor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability and manufacturing yield of a POP type semiconductor device constituting a system by stacking a second semiconductor package on a first semiconductor package. <P>SOLUTION: The POP type semiconductor device is constituted by stacking the second semiconductor package including a printed circuit board, on which a DRAM chip and a flash memory chip are mounted, on the first semiconductor package 100 including the printed circuit board 101 on which a controller chip is mounted. In this POP type semiconductor device, a lower surface side land 115d for DRAM chip interface of the first semiconductor package 100 is arranged in the outermost circumference of the lower surface of the printed circuit board 101 and a via wiring 113d for DRAM chip interface is arranged in the external side of an upper surface side land 112d for DRAM chip interface in order to achieve the shortest wiring length of the route extending to the lower surface side land 115d from the controller chip 102. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a semiconductor system, and more particularly, a package on package in which a system is configured by stacking a second semiconductor device (second semiconductor package) on a first semiconductor device (first semiconductor package). : POP) type semiconductor device.

  In recent years, a controller-type semiconductor chip and a memory-type semiconductor chip are mounted on separate semiconductor devices (semiconductor packages) to meet the demand for higher integration of semiconductor devices as well as changes in memory capacity. A POP type semiconductor device in which these semiconductor devices are combined to form a system in accordance with the purpose of use is attracting attention.

  The above POP type semiconductor device has an advantage that manufacturing yield can be improved because each completed semiconductor device (upper semiconductor package, lower semiconductor package) is selected in a test process, and both are assembled after obtaining only good products. Yes, and easy to change varieties.

  Japanese Patent Laid-Open No. 2006-303079 discloses a second semiconductor device (first semiconductor package) in which a memory chip is mounted on a first semiconductor device (first semiconductor package) in which an ASIC (Application Specific Integrated Circuit) chip is mounted. A POP type semiconductor device in which two semiconductor packages are stacked is disclosed.

In the case of the POP type semiconductor device described in Patent Document 1, in the first semiconductor device on the lower stage side, a frame-shaped guide made of an insulator having a plurality of holes is fixed to the upper surface of the wiring board. Wiring on the upper surface of the wiring board is located at the bottom of these holes, and the inside of the guide is covered with a sealing body. On the other hand, the upper second semiconductor device has a structure in which an electrode provided on the lower surface of the wiring board faces the hole of the first semiconductor device, and this electrode is filled in the guide of the first semiconductor device. The solder balls are electrically connected to the wiring at the bottom of the hole by reheating the solder balls.
JP 2006-303079 A

  The POP type semiconductor device includes, for example, a first semiconductor package (first semiconductor component) on which a controller chip is mounted and a second semiconductor package (second semiconductor component) on which a memory chip such as a DRAM or a flash memory is mounted. The second semiconductor package is stacked on the first semiconductor package. And it mounts on the motherboard of an external electronic device etc. via the external terminal provided in the lower surface of the lower 1st semiconductor package.

  Also, a POP type semiconductor device manufacturing method includes preparing a first semiconductor package on which a non-defective controller chip is mounted and a second semiconductor package on which a non-defective memory chip is mounted. The other semiconductor package (upper package) is stacked on top of the other package and shipped, and only one of the semiconductor packages is shipped. There is a method of stacking a corresponding package on the purchased package. This time, this inventor discovered that the following problems generate | occur | produce when performing the below-mentioned system (system which ships only one semiconductor package). That is, the first semiconductor package and the second semiconductor package are not only manufactured in separate processes, but in some cases, the first semiconductor package and the second semiconductor package may be manufactured by different semiconductor manufacturers. Therefore, for example, even if a disconnection failure occurs in the wiring substrate in the manufacturing process of the first semiconductor package, the disconnection failure may be detected in a test process performed by the manufacturer of the first semiconductor package depending on the location of the disconnection. May be difficult. The reason will be described using a semiconductor package having a wiring substrate as shown in FIG. This figure is an enlarged cross-sectional view of the main part showing the first semiconductor package (lower package) for the POP type semiconductor device examined by the present inventors.

  A first semiconductor package 100 shown in FIG. 25 includes a wiring board 101 and a controller chip 102 mounted on the upper surface of the wiring board 101. A plurality of wirings 110 are formed on the upper surface of the wiring substrate 101, and a plurality of electrode pads 103 are formed on the main surface of the controller chip 102. Then, one end (bonding lead 111) of each of the plurality of wirings 110 formed on the wiring substrate 101 and the corresponding electrode pad 103 of the controller chip 102 are electrically connected by an Au wire 104.

  Inside the wiring substrate 101, an internal wiring 114 electrically connected to the wiring 110 on the upper surface via the via wiring 113 is formed. In addition, a plurality of lower surface lands 115 electrically connected to the internal wiring 114 and the wiring 110 through the via wiring 113 are formed on the lower surface of the wiring substrate 101. Solder balls 105 functioning as external terminals of the POP type semiconductor device are provided on the respective surfaces of the lower surface side lands 115.

  The upper surface of the wiring substrate 101 is covered with a solder resist 106 except for the surfaces of one end (bonding lead 111) and the other end (upper surface land 112) of the wiring 110. In addition, the controller chip 102, the bonding leads 111 of the wiring board 101, and the Au wires 104 that electrically connect them are sealed with a sealing body 108 made of a thermosetting epoxy resin or the like.

  The upper surface side land 112 which is the other end of the wiring 110 is a terminal for electrically connecting the first semiconductor package 100 and a second semiconductor package (not shown). The second semiconductor package includes a wiring board and a memory chip mounted on the upper surface thereof, and a solder ball (shown by a two-dot chain line in the figure) electrically connected to the memory chip is provided on the lower surface of the wiring board. Solder balls 208) are provided. Then, in the assembly process of the POP type semiconductor device, by connecting this solder ball 208 to the upper surface side land 112 of the first semiconductor package 100, the first semiconductor package 100 and the second semiconductor package are electrically connected, A POP type semiconductor device is completed.

  The manufacturing process of the first semiconductor package 100 includes a die bonding process for mounting the controller chip 102 on the upper surface of the wiring substrate 101, a wire bonding process for connecting the bonding lead 111 and the controller chip 102 with the Au wire 104, and the controller chip 102. There are a plurality of processes in which the wiring board 101 is exposed to a high temperature atmosphere, such as a molding process for sealing the Au wire 104 with the sealing body 108 and a solder reflow process for connecting the solder balls 105 to the lower surface of the wiring board 101. For this reason, a part of the wiring 110 formed on the wiring substrate 101, for example, a portion indicated by an arrow in the drawing (the wiring 110 extending from the controller chip 102 to the upper surface land 112) may be disconnected due to thermal stress.

  Usually, in a test process performed after the completion of the first semiconductor package 100, an AC / DC test for the controller chip 102 and a test for confirming conduction / non-conduction of a wiring path from the controller chip 102 to the solder ball 105 are performed. However, when the wiring 110 is disconnected at the above-described location, even if no current flows from the controller chip 102 to the upper surface side land 112, the solder 110 passes from the controller chip 102 via the wiring 110, the via wiring 113, and the internal wiring 114. Since the wiring path leading to the ball 105 is conductive, it is difficult to detect the disconnection in this test process.

  Therefore, the present inventor examined layout of the wiring so that no branching occurs in the wiring path from the external terminal to the bonding lead as in the structure shown in FIG.

  However, as the functionality of semiconductor devices increases, the number of external terminals provided on the back surface of the wiring board tends to increase, and some of the plurality of lands (or external terminals) are located on the outermost peripheral portion of the lower surface of the wiring board. As well as inside it.

  For this reason, if it is attempted to lay out the wiring so that no branch occurs in the wiring path from the external terminal to the bonding lead for all lands, the wiring design becomes very complicated. In addition, since a large number of wirings having a long length are formed, the size of the wiring board and the number of wiring layers are increased, and it is difficult to reduce the size (outer dimensions and thickness) of the semiconductor device. Furthermore, the impedance component with respect to the long wiring becomes large, and the reliability of the semiconductor device may be lowered.

An object of the present invention is to provide a POP type semiconductor device in which a second semiconductor device (second semiconductor package, second semiconductor component) is stacked on a first semiconductor device (first semiconductor package, first semiconductor component) to constitute a system. In the present invention, prior to the step of stacking the second semiconductor device on the first semiconductor device, there is provided a technique capable of detecting a disconnection failure occurring in the wiring substrate of the first semiconductor device with high accuracy.
Another object of the present invention is to provide a technique capable of improving the reliability of a POP type semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A semiconductor device which is an invention of the present application is:
A semiconductor device in which another semiconductor device having another semiconductor chip is stacked,
(A) The semiconductor device includes:
(A1) An upper surface having a rectangular planar shape, a plurality of bonding leads formed on the upper surface, a plurality of upper surface lands formed on the upper surface and electrically connected to the bonding leads, and a planar shape Is formed in a rectangular shape, and electrically connects the lower surface located opposite to the upper surface, the plurality of lower surface lands formed on the lower surface, and the plurality of upper surface lands and the plurality of lower surface lands, respectively. A wiring board having a plurality of via wirings;
(A2) A main surface, a plurality of electrode pads formed on the main surface, a semiconductor element formed on the main surface and electrically connected to the plurality of electrode pads, and on the opposite side of the main surface A first semiconductor chip having a back surface positioned and mounted on the top surface of the wiring board;
(A3) a plurality of conductive members that respectively electrically connect the plurality of electrode pads of the first semiconductor chip and the plurality of bonding leads of the wiring board;
(A4) a sealing body that seals the first semiconductor chip and the plurality of conductive members;
(A5) a plurality of external terminals provided on each of the plurality of lower surface lands;
Including
The plurality of electrode pads include a first semiconductor chip interface electrode pad and a second semiconductor chip interface electrode pad ;
The plurality of bonding leads include a first semiconductor chip interface bonding lead electrically connected to the first semiconductor chip interface electrode pad via the conductive member, and the conductive member via the conductive member. A second semiconductor chip interface bonding lead electrically connected to the second semiconductor chip interface electrode pad ;
Wherein the plurality of upper surface side land, said first and upper surface lands semiconductor chip interface, the bonding leads and electrically for the second semiconductor chip interface connected first semiconductor chip bonding leads and electrically interface A second semiconductor chip interface top surface land connected to
Wherein the plurality of via wiring, said first and vias interconnect the semiconductor chip interfaces, electrical and top side land for the second semiconductor chip interface connected first semiconductor chip upper surface lands electrically interface A second semiconductor chip interface via wiring connected to
The first semiconductor chip interface via wiring is arranged at a position farther from the first semiconductor chip interface bonding lead than the first semiconductor chip interface upper surface side land,
The second semiconductor chip interface via wiring is disposed between the second semiconductor chip interface bonding lead and the second semiconductor chip interface upper surface land,
The width of at least a part of the wiring connecting the second semiconductor chip interface via wiring and the second semiconductor chip interface upper surface land is such that the second semiconductor chip interface via wiring and the second semiconductor chip interface via wiring Wider than the width of the wiring connecting the semiconductor chip interface bonding leads,
The plurality of lower surface lands include a plurality of first lower surface lands disposed along a side of the lower surface, and a plurality of second lower surfaces disposed on the inner side of the lower surface than the plurality of first lower surface lands. Including side lands,
The first semiconductor chip interface upper surface side land is electrically connected to the first lower surface side land via the first semiconductor chip interface via wiring ,
The second semiconductor chip interface upper surface side land is electrically connected to the second lower surface side land via the second semiconductor chip interface via wiring .

(2) A semiconductor system according to an aspect of the present invention is a semiconductor system including a first semiconductor component and a second semiconductor component stacked on the first semiconductor component,
(A) The first semiconductor component is:
(A1) A first upper surface having a rectangular planar shape, a plurality of first bonding leads formed on the first upper surface, and formed on the first upper surface and electrically connected to the plurality of first bonding leads, respectively. A plurality of first upper surface lands, a planar shape of a rectangular shape, a first lower surface located on the opposite side of the first upper surface, a plurality of first lower surface lands formed on the first lower surface, and A first wiring board having a plurality of first via wirings that electrically connect the plurality of first upper surface side lands and the plurality of first lower surface side lands, respectively;
(A2) a first main surface, a plurality of first electrode pads formed on the first main surface, and a first electrode formed on the first main surface and electrically connected to the plurality of first electrode pads, respectively. A first semiconductor chip mounted on the first upper surface of the first wiring substrate, and having a semiconductor element and a first back surface located on a side opposite to the first main surface;
(A3) a plurality of first conductive members that electrically connect the plurality of first electrode pads of the first semiconductor chip and the plurality of first bonding leads of the first wiring substrate;
(A4) a first sealing body that seals the first semiconductor chip and the plurality of first conductive members;
(A5) a plurality of first external terminals provided on each of the plurality of first lower surface side land,
Including
The plurality of first electrode pads include a first semiconductor chip interface electrode pad and a second semiconductor chip interface electrode pad ,
The plurality of first bonding leads include a first semiconductor chip interface bonding lead electrically connected to the first semiconductor chip interface electrode pad via the first conductive member, and the first conductive lead. A second semiconductor chip interface bonding lead electrically connected to the second semiconductor chip interface electrode pad via a conductive member ;
The plurality of first upper surface side lands include a first semiconductor chip interface upper surface land electrically connected to the first semiconductor chip interface bonding lead, and the second semiconductor chip interface bonding lead. A second semiconductor chip interface top land that is electrically connected ;
The plurality of first via wirings include a first semiconductor chip interface via wiring electrically connected to the first semiconductor chip interface upper surface land, and the second semiconductor chip interface upper surface land. A via wiring for a second semiconductor chip interface electrically connected ;
The first semiconductor chip interface via wiring is arranged at a position farther from the first semiconductor chip interface bonding lead than the first semiconductor chip interface upper surface side land,
The second semiconductor chip interface via wiring is disposed between the second semiconductor chip interface bonding lead and the second semiconductor chip interface upper surface land,
The width of at least a part of the wiring connecting the second semiconductor chip interface via wiring and the second semiconductor chip interface upper surface land is such that the second semiconductor chip interface via wiring and the second semiconductor chip interface via wiring Wider than the width of the wiring connecting the semiconductor chip interface bonding leads,
The plurality of first lower surface-side lands include a plurality of outer lands disposed along a side of the first lower surface, and a plurality of inner lands disposed on the inner side of the first lower surface than the plurality of outer lands. Including
The first semiconductor chip interface upper surface side land is electrically connected to the outer land via the first semiconductor chip interface via wiring,
The second semiconductor chip interface upper surface side land is electrically connected to the inner land via the second semiconductor chip interface via wiring,
(B) The second semiconductor component is
(B1) a second upper surface having a rectangular planar shape, a plurality of second bonding leads formed on the second upper surface, and a second planar surface having a rectangular shape and positioned opposite to the second upper surface. A plurality of second lower surface side lands formed on the lower surface, a plurality of second lower surface side lands formed on the second lower surface, and a plurality of second via wirings that electrically connect the plurality of second bonding leads and the plurality of second lower surface side lands, respectively. A second wiring board having,
(B2) a second main surface, a plurality of second electrode pads formed on the second main surface, a second electrode formed on the second main surface and electrically connected to the plurality of second electrode pads, respectively. A second semiconductor chip mounted on the second upper surface of the second wiring substrate, the semiconductor element, and a second back surface located opposite to the second main surface;
(B3) a plurality of second conductive members that respectively electrically connect the plurality of second electrode pads of the second semiconductor chip and the plurality of second bonding leads of the second wiring board;
(B4) a second sealing body that seals the second semiconductor chip and the plurality of second conductive members;
(B5) a plurality of second external terminals provided on each of the plurality of second lower surface side lands;
Including
The first semiconductor element controls the second semiconductor element;
The plurality of second external terminals are electrically connected to the plurality of first upper surface side lands formed on the first wiring board of the first semiconductor component , respectively.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to one invention of this application, before the process of laminating | stacking a 2nd semiconductor device on a 1st semiconductor device, the disconnection defect of the wiring of a 1st wiring board is reliably detected in the test process after completion of a 1st semiconductor device. be able to.

  In addition, a load (wiring impedance) on the first memory chip of the second semiconductor device stacked on the first semiconductor device can be reduced, and a decrease in reliability (electrical characteristics) of the semiconductor device can be suppressed. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary. Further, in the drawings for explaining the following embodiments, hatching may be given even in a plan view for easy understanding of the configuration.

In the present embodiment, a POP type semiconductor device in which a second semiconductor device (second package, upper package) is stacked on a first semiconductor device (first package, lower package) and both are electrically connected. And applied to a semiconductor system.
<First Semiconductor Device (First Semiconductor Package, First Semiconductor Component)>
FIG. 1 is a cross-sectional view showing the overall configuration of a POP type semiconductor device (semiconductor system), and FIG. 2 is an enlarged view of a part of the first semiconductor device (first semiconductor package) constituting the lower package of the POP type semiconductor device. It is sectional drawing shown.

  A first semiconductor package (hereinafter referred to as a first package) 100 includes a wiring board (lower substrate, first wiring board) 101, and a controller chip (first semiconductor chip) 102 mounted on the upper surface of the wiring board 101. It has. A plurality of wirings 110 are formed on the upper surface (front surface, main surface) of the wiring substrate 101, and a plurality of electrode pads 103 are formed on the main surface (front surface) of the controller chip 102. A part of the plurality of wirings 110 (in this embodiment, one end of the wiring 110) constitutes the bonding lead 111, and the other part (in this embodiment, the other end of the wiring 110) constitutes the upper surface side land 112. ing. Each of the plurality of bonding leads 111 and the corresponding electrode pad 103 of the controller chip 102 are electrically connected by a gold (Au) wire (conductive member) 104.

  The wiring substrate 101 (in particular, the upper surface and the lower surface) has a rectangular planar shape, and is, for example, a quadrangle in the present embodiment. The wiring board 101 is a multilayer wiring board mainly composed of a general-purpose resin such as a glass epoxy resin and a wiring layer, and the wiring 110 on the upper surface 110 (or vias) is formed inside via a via wiring 113. An internal wiring 114 electrically connected to the bonding lead 111 or the upper surface land 112) via the wiring 113 and the upper wiring 110 is formed over two layers. A plurality of lower surface lands 115 electrically connected to the internal wiring 114 and the wiring 110 through via wirings 113 are formed on the lower surface (back surface) of the wiring substrate 101. As shown in FIG. 3, the first lower surface side lands 115 are arranged in an array on the lower surface of the wiring substrate 101. That is, the wiring substrate 101 includes a first wiring layer in which the upper wiring 110 is formed, a second wiring layer in which the lower land 115 is formed, and a third and fourth wiring layers in which the internal wiring 114 is formed. It is a wiring board. The wiring 110, the via wiring 113, the internal wiring 114, and the lower surface land 115 are made of a low resistance metal such as Cu.

  Solder balls (external terminals) 105 functioning as external terminals of the POP type semiconductor device are provided on the respective surfaces of the plurality of lower surface lands 115 formed on the lower surface of the wiring substrate 101. However, in the POP type semiconductor device of the present embodiment, the solder ball 105 is not provided on the outermost lower surface land 115 (the lower surface land 115d with hatching in FIG. 3) for the reason described later. The solder ball 105 may be, for example, tin (Sn) alone or a small amount of bismuth (Bi), zinc (Zn), silver (Ag), copper (Cu), or these metals in consideration of whisker countermeasures. It consists of Sn alloy etc. which added two or more of these. The POP type semiconductor device is mounted on an external electronic device such as a digital camera or a mobile phone through these solder balls 105.

  The upper surface of the wiring substrate 101 is an insulating resin for protecting the wiring 110 except for the surface of a part of each of the plurality of wirings 110 (bonding leads 111) and the surface of the other part (upper surface land 112). It is covered with a solder resist 106 which is a film. The surface of the first bonding lead 111 and the surface of the upper surface land 112 that are not covered with the solder resist 106 are made of, for example, a two-layer metal film in which a gold (Au) layer is laminated on a nickel (Ni) layer. A plating layer (not shown) is formed. Similarly, the lower surface of the wiring board 101 is covered with the solder resist 106 except for the surface of the lower surface land 115. Note that the lower surface side land 115 is not limited to be disposed at a position overlapping with the via wiring 113 in a planar manner. For example, the lower surface land 115 is formed at a position not overlapping with the via wiring 113 in a planar manner. It may be configured to be electrically connected.

  The controller chip (semiconductor chip, lower chip) 102 mounted on the upper surface of the wiring substrate 101 is formed of a single crystal silicon substrate having a substantially square planar shape, and the back surface of the controller chip 102 faces the upper surface of the wiring substrate 101. Thus, it is mounted (face-up mounting) on the central portion of the upper surface of the wiring substrate 101 by the adhesive 107. The plurality of electrode pads 103 described above are formed in the peripheral portion of the main surface of the controller chip 102, and a second semiconductor device (second package, second semiconductor component), which will be described later, is formed inside them, although not shown. A control circuit (first semiconductor element) for controlling the mounted memory chip is formed.

  The controller chip 102, the first bonding lead 111 on the upper surface of the wiring substrate 101, and the Au wire 104 that connects the controller chip 102 and the bonding lead 111 are sealed with a sealing body 108. The sealing body 108 is made of a thermosetting epoxy resin filled with a filler such as silica.

  FIG. 4 is a plan view showing the upper surface of the wiring board 101. However, since a part of the wiring 110 is covered with the solder resist 106 as described above, only the first bonding lead 111 and the upper surface side land 112 are shown. Further, the outer edge of the sealing body 108 is indicated by a two-dot chain line. An upper surface side land denoted by reference numeral 112 is a memory chip interface upper surface side land for electrically connecting to a memory chip mounted on a second semiconductor device to be described later. For example, reference numeral 112d indicates a DRAM chip interface. This is an upper surface side land for use. Although not described in detail in FIG. 4, the upper surface side lands for the DRAM chip interface are on the outer side of the upper surface side lands arranged in two rows along each side of the wiring substrate 101. Not only the land rows but also the inner land rows.

As shown in FIG. 4, the upper surface lands 112 and 112 d are arranged in two rows along the four sides of the upper surface of the wiring substrate 101. Further, the electrode pads 103 of the controller chip 102 are arranged in a line along the four sides of the main surface of the controller chip 102. These electrode pads 103 are made of a metal material constituting the uppermost layer wiring of the controller chip 102, for example, a metal film mainly composed of an Al alloy, and are electrically connected to semiconductor elements constituting the control circuit. Note that the electrode pads 103 may be arranged in two rows in a staggered manner along the four sides of the main surface of the controller chip 102.
<Second Semiconductor Device (Second Semiconductor Package, Second Semiconductor Component)>
Next, the second semiconductor device (second semiconductor package, second semiconductor component) constituting the upper package of the POP type semiconductor device will be described with reference to FIGS. 1, 5, 6 and 7. FIG. 5 is a plan view showing the upper surface of the second semiconductor package, FIG. 6 is an enlarged cross-sectional view of the main part of the second semiconductor package along the line AA in FIG. 5, and FIG. 7 is the lower surface of the second semiconductor package. FIG.

  A second semiconductor package (hereinafter referred to as a second package) 200 includes a wiring board (upper side board, second wiring board) 201 having substantially the same outer dimensions as the wiring board 101 of the first package 100, and the wiring board. A DRAM chip (upper side chip, first memory chip) 202 mounted on the center of the upper surface of 201 and a flash memory chip (upper side chip, second memory chip) 203 stacked on the DRAM chip 202 I have. The wiring board 201 is a wiring board mainly composed of a general-purpose resin such as glass epoxy resin, and a plurality of bonding leads 211 are formed on the upper surface thereof. These bonding leads 211 are arranged in a line along each side of a memory chip (DRAM chip 202 and flash memory chip 203) whose planar shape is rectangular (rectangular).

  A plurality of electrode pads 204 are formed on the main surface of the DRAM chip (semiconductor chip) 202. These electrode pads 204 are arranged in a line along two opposing sides of the main surface of the DRAM chip 202. The bonding lead 211 of the wiring board 201 and the corresponding electrode pad 204 of the DRAM chip 202 are electrically connected by an Au wire (conductive member) 206.

  A plurality of electrode pads 205 are formed on the main surface of the flash memory chip (semiconductor chip) 203. These electrode pads 205 are arranged in a line along two opposing sides of the main surface of the flash memory chip 203. Here, the side on which the electrode pad 205 is arranged is a part aligned with a side different from the side on which the electrode pad 204 is arranged in the DRAM chip 202 as shown in FIG. The bonding lead 211 of the wiring board 201 and the corresponding electrode pad 205 of the flash memory chip 203 are electrically connected by an Au wire (conductive member) 207.

  The lower surface (back surface) of the wiring substrate 201 has a plurality of lower surfaces electrically connected to the bonding leads 211 on the upper surface (front surface, main surface) via a plurality of via wirings 212 penetrating the upper and lower surfaces of the wiring substrate 201. A side land 213 is formed. The bonding lead 211, the via wiring 212, and the lower surface side land 213 are made of a low resistance metal such as Cu. Further, on the surface of the bonding lead 211, for example, a plating layer (not shown) made of a two-layer metal film in which an Au layer is laminated on a Ni layer is formed.

  As shown in FIG. 7, the plurality of lower surface lands 213 are arranged in two rows along the four sides of the lower surface of the wiring board 201. The number of lower surface side lands 213 is the same as the number of upper surface side lands 112 formed on the upper surface of the wiring substrate 101 of the first package 100, and when the second package 200 is stacked on the first package 100, A lower surface side land 213 of the second package 200 and a corresponding upper surface side land 112 of the first package 100 are opposed to each other.

  As shown in FIG. 6, solder balls 208 functioning as external terminals of the second package 200 are provided on the respective surfaces of the plurality of lower surface lands 213. These solder balls 208 are made of a solder material having a melting point higher than that of the solder balls 105 provided on the lower surface side land 115 of the first package 100. The second package 200 is electrically connected to the first package 100 through these solder balls 208. In FIG. 7, the solder balls 208 are not shown. Here, in the case of the POP type semiconductor device, the second package (second semiconductor component) 200 is stacked on the first package (first semiconductor component) 100 and then mounted on the motherboard. Therefore, if the melting point of the solder ball 208 is lower than the melting point of the solder ball 105, the solder ball 208 that supports the stacked second semiconductor components melts due to the influence of heat for melting the solder ball 105, and the second The position of the package 200 may be shifted. Therefore, it is preferable to use a solder material having a melting point higher than that of the solder ball 105, but the solder ball 208 is made of the same solder material as the melting point of the solder ball 105 as long as the position of the second package 200 is not shifted. Solder balls 208 may be used.

  The upper surface of the wiring substrate 201 is covered with a solder resist 209 except for the surface of the bonding lead 211 that is a part of the wiring. Similarly, the lower surface of the wiring board 201 is covered with a solder resist 209 except for the surface of the lower surface side land 213. Note that the lower surface side land 213 is not limited to be disposed at a position that overlaps the via wiring 212 in a planar manner. For example, the lower surface land 213 is formed at a position that does not overlap the via wiring 212 in a planar manner. It may be configured to be electrically connected. Also, the wiring board 201 used in the present embodiment is different from the wiring board 101 having four wiring layers, and includes a first wiring layer formed on the upper surface and a second wiring layer formed on the lower surface. Become.

  The DRAM chip 202 mounted on the upper surface of the wiring substrate 201 is made of a single crystal silicon substrate having a rectangular planar shape, and is secondly bonded by an adhesive 220 so that the back surface of the DRAM chip 202 faces the upper surface of the wiring substrate 201. It is mounted (face-up mounting) on the center of the upper surface of the wiring board 201. A plurality of the electrode pads 204 described above are formed on two opposite sides of the main surface of the DRAM chip 202, and a DDR (Double Data Rate) standard DRAM (second semiconductor element), for example, is not shown inside them. ) Is formed. The electrode pad 204 is made of the same metal material as that of the uppermost layer wiring of the DRAM chip 202, for example, a metal film mainly composed of an Al alloy, and is electrically connected to a semiconductor element constituting the DRAM.

  The flash memory chip 203 stacked on the DRAM chip 202 so that the back surface faces the main surface of the DRAM chip 202 is a single crystal silicon having a rectangular planar shape and a smaller outer dimension than the DRAM chip 202. It consists of a substrate and is mounted on the DRAM chip 202 (face-up mounting) with an adhesive 220. The plurality of electrode pads 205 described above are formed on two opposite sides of the main surface of the flash memory chip 203, and a flash memory (third semiconductor element) is formed inside them, though not shown. The electrode pad 205 is made of the same metal material as that of the uppermost layer wiring of the flash memory chip 203, for example, a metal film mainly composed of an Al alloy, and is electrically connected to a semiconductor element constituting the flash memory.

  A sealing body 221 for sealing the two memory chips (DRAM chip 202 and flash memory chip 203) and Au wires 206 and 207 is formed on the upper surface of the wiring substrate 201. The sealing body 221 is made of a thermosetting epoxy resin filled with a filler such as silica. In FIG. 5, illustration of the sealing body 221 is omitted.

  FIG. 8 is a circuit block diagram showing a system configuration of a POP type semiconductor device (semiconductor system) composed of the first package 100 and the second package 200.

  The external electronic device and the POP type semiconductor device perform input / output of signals and transmission / reception of power through the solder balls 105 provided on the lower surface land 115 of the wiring substrate 101 of the first package 100. Here, input / output of signals between the DRAM chip 202 mounted on the second package 100 on the first package 100 and the external electronic device is performed via the controller chip 102 of the first package 100. ing. Therefore, the wiring board 101 of the first package 100 is not provided with the lower surface side land 115 for directly inputting / outputting signals between the external electronic device and the DRAM chip 202 without using the controller chip 102.

  On the other hand, the external electronic device manufacturer directly writes data into the flash memory chip 203 stacked on the DRAM chip 202 using a ROM writer or the like. Signals are directly input / output between the flash memory chip 203 and the external electronic device without intervention. Therefore, in order to directly input and output signals between the external electronic device and the flash memory chip 203 without using the controller chip 102, the plurality of lower surface lands 115 formed on the wiring substrate 101 of the first package 100 are used. Lower surface side lands (and external terminals formed on the lower surface side lands).

  Next, the layout of the wiring formed on the wiring substrate 101 of the first package 100 will be described. 9 is a plan view in which the upper surface of the wiring board 101 shown in FIG. 4 is simplified, FIG. 10 is an enlarged plan view showing a part of FIG. 9, and FIG. 11 is taken along line BB in FIG. FIG. 12 is a sectional view taken along the line CC of FIG. 9 and 10 show the number of the electrode pads 103 of the controller chip 102, the wirings 110 of the wiring board 101, and the Au wires 103 connecting them to be smaller than the actual number in order to make the wiring layout easier to see. ing.

  As shown in FIGS. 9 to 11, the plurality of electrode pads 103 formed on the main surface of the controller chip 102 include electrode pads 103d for DRAM chip interface. Further, the plurality of wirings 110 formed on the upper surface of the wiring substrate 101 include a wiring 110d for DRAM chip interface.

  One end of the DRAM chip interface wiring 110d constitutes a bonding lead 111d for DRAM chip interface, and the other end constitutes an upper surface side land 112d for DRAM chip interface. The bonding lead 111d for the DRAM chip interface is electrically connected to the electrode pad 103d of the controller chip 102 via the Au wire 104, and the upper surface side land 112d for the DRAM chip interface is a via wiring for the DRAM chip interface. 113d is electrically connected.

  The DRAM chip interface via wiring 113d is disposed on the upper surface of the wiring substrate 101 at a position farther from the bonding lead 111d than the upper surface land 112d (periphery side of the upper surface of the wiring substrate 101). These via wirings 113 d are electrically connected to the lower surface side lands 115 d for DRAM chip interface located on the outermost periphery among the plurality of lower surface lands 115 formed on the lower surface of the wiring substrate 101.

  The DRAM chip interface lower surface land 115d disposed on the outermost periphery of the lower surface of the wiring substrate 101 constitutes a test terminal used in a test process performed after the first package 100 is completed. That is, the lower surface side land 115d for the DRAM chip interface is electrically connected to the DRAM chip interface wiring 110d via the via line 113d for the DRAM chip interface and the upper surface side land 112d for the DRAM chip interface. It is electrically connected to the controller chip 102 (DRAM chip interface electrode pad 103d) via a bonding lead 111d for chip interface and an Au wire 104. Accordingly, in a test process performed after the completion of the first package 100, a probe is applied to the lower surface land 115d (test terminal) for the DRAM chip interface to reach the lower surface land 115d for the DRAM chip interface from the controller chip 102. By inspecting the continuity / non-continuity test of the wiring path, the disconnection failure of the DRAM chip interface wiring 110d can be reliably detected.

  Further, as described above, since the input / output of signals between the DRAM chip 202 and the external electronic device is performed via the controller chip 102 of the first package 100, the lower surface land 115d for the DRAM chip interface is provided. The above input / output signals do not flow. Therefore, it is not necessary to provide an external terminal (solder ball 105) for connecting the POP type semiconductor device to the external electronic device on the lower surface side land 115d for the DRAM chip interface. When the solder ball 105 is not provided on the lower surface side land 115d located on the outermost periphery of the lower surface of the wiring board 101, the land connected to the solder ball 105 does not have to be formed on the motherboard of the external electronic device. The wiring design of the motherboard (for example, the layout design for drawing the wiring on the motherboard electrically connected to the external terminals formed on the lower land disposed inside the periphery of the POP type semiconductor device) It becomes easy.

  In addition, since the lower surface side land 115d for the DRAM chip interface is arranged on the outermost periphery of the lower surface of the wiring substrate 101, it is possible to suppress a decrease in reliability (electrical characteristics) of the POP type semiconductor device. This is because, when the lower surface land 115d for the DRAM chip interface is arranged inside the outermost periphery of the lower surface of the wiring substrate 101, the upper surface land 112d for the DRAM chip interface passes through the via wiring 113d and the internal wiring 114. As a result, the wiring length of the path reaching the lower surface side land 115d becomes longer. However, since the driving frequency of DRAM is generally higher than the driving frequency of flash memory, if the wiring length for DRAM chip interface increases, the impedance component of the wiring increases correspondingly, and the wiring may pick up unnecessary noise. Therefore, the reliability (electrical characteristics) of the POP type semiconductor device may be lowered.

  On the other hand, in the present embodiment, the lower surface side land 115d for the DRAM chip interface is disposed on the outermost periphery of the lower surface of the wiring board 101, and the via wiring 113d for the DRAM chip interface is disposed on the upper surface side land for the DRAM chip interface. It is arranged outside 112d. This minimizes the wiring length of the path from the upper surface land 112d to the lower surface land 115d for the DRAM chip interface, and hence the path from the controller chip 102 to the lower surface land 115d. A decrease in reliability (electrical characteristics) of the POP type semiconductor device is suppressed.

  As shown in FIGS. 9, 10 and 12, the plurality of electrode pads 103 formed on the main surface of the controller chip 102 include electrode pads 103f for flash memory chip interface. Further, the plurality of wirings 110 formed on the upper surface of the wiring board 101 includes a flash memory chip interface wiring 110f.

  Each of the flash memory chip interface wirings 110f (one end in the present embodiment) constitutes a flash memory chip interface bonding lead 111f, and the other part (the other end in the present embodiment). Constitutes the upper surface side land 112f for the flash memory chip interface. The bonding lead 111f is electrically connected to the electrode pad 103f of the controller chip 102 via the Au wire 104.

  A flash memory chip interface via wiring 113f is electrically connected to each of the flash memory chip interface wirings 110f. Here, as shown in FIG. 10, each of the flash memory chip interface via wirings 113f is formed between the upper surface land 112f for flash memory chip interface and the bonding lead 111f (upper surface side) on the upper surface of the wiring substrate 101. (Position closer to the bonding lead 111f than the land 112f). Similarly to the via wiring 113d for the DRAM chip interface, if the via wiring 113f for the flash memory chip interface is also arranged on the peripheral edge side of the wiring substrate 101 with respect to the upper surface land 112f, the length of the wiring path for the flash memory chip interface is increased. In addition, although it is possible to shorten the length, it is difficult to route all the wiring paths in the same way as the wiring paths for the DRAM chip interface in consideration of reducing the external size of the semiconductor device (miniaturization). . Therefore, in the present embodiment, the via wiring 113d for DRAM having a higher drive frequency than the flash memory is preferentially disposed between the upper surface land 113d and the peripheral portion of the wiring substrate 101 (position farther from the bonding lead 112d). The via wiring 113f for the flash memory chip interface, which is disposed at a distance between the upper surface side 112f and the bonding lead 111f, is disposed. These via wirings 113f are for the flash memory chip interface disposed inside the lower surface side land 115d for the DRAM chip interface among the plurality of lower surface lands 115 formed on the lower surface of the wiring substrate 101. It is electrically connected to the lower surface side land 115f.

  Further, as shown in FIG. 10, each of the flash memory chip interface wirings 110f has a line width from the top surface land 112f to the via wiring 113f, and a line width from the via wiring 113f to the bonding lead 111f. It is configured to be thicker than the width. That is, each of the flash memory chip interface wirings 110f is thicker in the peripheral portion of the upper surface of the wiring substrate 101, which is a relatively sparse region, and the wiring density is relatively denser than the peripheral portion. It is thin in a certain area. In the example shown in FIG. 10, the wiring 110f between the upper surface side land 112f and the via wiring 113f is thickened as a whole, but the wiring 110f in this region is thickened as a whole due to restrictions on wiring design. If this is difficult, a part of the wiring 110f in this region may be partially thickened as shown in FIG.

  As described above, in the present embodiment, the via wiring 113f for the flash memory chip interface is arranged inside the upper surface side land 112f, and the wiring 110f between the via wiring 113f and the upper surface land 112f is thickened. As a result, the wiring substrate 101 is exposed to a high temperature atmosphere during the manufacture of the first package 100, and thermal stress is applied to the wiring 110f in which the via wiring 113f cannot be disposed at a position farther from the bonding lead 111f than the upper surface land 112f. Even if added, it becomes difficult to disconnect the wiring 110f, so that the manufacturing yield and reliability of the POP type semiconductor device can be improved.

  Next, an example of a manufacturing method of the POP type semiconductor device configured as described above will be described with reference to FIGS.

  FIG. 13 is an enlarged plan view of a main part showing the upper surface of the matrix substrate 130 used for manufacturing the first package 100, and FIG. 14 is an enlarged plan view of the main part showing the lower surface of the matrix substrate 130.

  The matrix substrate 130 has a structure in which the conductor pattern (the wiring 110, the bonding lead 111, the upper surface land 112, the via wiring 113, the internal wiring 114, and the lower surface land 115) of the wiring substrate 101 described above is repeatedly formed. The matrix substrate 130 is a base substrate of the wiring substrate 101 of the first package 100, and a large number of wiring substrates 101 can be obtained by dicing this. 13 and 14 are enlarged views of a part of the matrix substrate 130 (a region corresponding to two pieces of the wiring substrate 101).

  On the other hand, FIG. 15 is a main part enlarged plan view showing the upper surface of the matrix substrate 230 used for manufacturing the second package 200, and FIG. 16 is a main part enlarged plan view showing the lower surface of the matrix substrate 230.

  The matrix substrate 230 has a structure in which the conductor patterns (bonding leads 211, via wirings 212, lower surface side lands 213) of the wiring substrate 201 described above are repeatedly formed. The matrix substrate 230 is a substrate that serves as a base of the wiring substrate 201 of the second package 200, and a large number of wiring substrates 201 can be obtained by dicing the matrix substrate 230. 15 and 16 show a part of the matrix substrate 230 (a region corresponding to two wiring substrates 201) in an enlarged manner.

  In order to manufacture the first package 100, as shown in FIG. 17, after mounting the controller chip 102 on the upper surface of the matrix substrate 130, the electrode pads 103 of the controller chip 102 and the matrix substrate 130 as shown in FIG. The bonding lead 211 is connected by the Au wire 104. The Au wire 104 is connected using a ball bonding method using both heat and ultrasonic waves.

  Next, as shown in FIG. 19, the controller chip 102, the bonding lead 211, and the Au wire 104 are resin-sealed with a sealing body 108. Subsequently, after connecting the solder balls 105 to the lower surface side land 115 formed on the lower surface of the matrix substrate 130, the matrix substrate 130 is diced to obtain the first package 100 as shown in FIG.

  When the solder ball 105 is connected to the lower surface side land 115 of the matrix substrate 130, the solder ball 105 is not connected to the lower surface side land 115d for the DRAM chip interface described above. In a test process performed after the completion of the first package 100, a probe is applied to the lower surface side land 115d to inspect the conduction / non-conduction of the DRAM chip interface wiring 110d. In this test process, an AC / DC test for the controller chip 102 and a test for inspecting the conduction / non-conduction of the wiring path from the controller chip 102 to the solder ball 105 are also performed to select the good first package 100.

  On the other hand, to manufacture the second package 100, as shown in FIG. 21, the DRAM chip 202 is mounted on the upper surface of the matrix substrate 230, and then the flash memory chip 203 is mounted on the main surface of the DRAM chip 202.

  Next, as shown in FIG. 22, the electrode pads 204 of the DRAM chip 202 and the bonding leads 211 of the matrix substrate 230 are connected by Au wires 206, and the electrode pads 205 and the bonding leads 211 of the flash memory chip 203 are connected by Au wires 207. Connecting.

  Next, as shown in FIG. 23, the DRAM chip 202, the flash memory chip 203, the bonding lead 211, and the Au wires 206 and 207 are sealed with a sealing body 221. Since there is no land for connecting solder balls on the upper surface of the matrix substrate 230, the entire upper surface of the matrix substrate 230 may be resin-sealed with a sealing body 221.

  Next, as shown in FIG. 24, after connecting the solder balls 208 to the lower surface side land 213 formed on the lower surface of the matrix substrate 230, the matrix substrate 230 is diced, whereby the second package 200 is obtained. Thereafter, an electrical characteristic test of the second package 200 is performed in a test process, and the second packages 200 that are non-defective are selected.

  Next, the second package 200 is stacked on the first package 100 obtained as described above, and the solder ball 208 connected to the lower surface side land 213 of the second package 200 is connected to the upper surface side of the first package 100. Position on the land 112. Then, the solder ball 208 is reflowed, and the lower surface side land 213 of the second package 200 and the upper surface side land 112 of the first package 100 are electrically connected by the solder ball 208, whereby the present embodiment shown in FIG. The POP type semiconductor device of the form is completed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The external terminal connected to the lower surface side land of the wiring board may be made of a material other than the solder ball, for example, a bump electrode such as an Au bump.

  Further, the controller chip mounted on the wiring board of the lower package may be mounted by a face-down method.

  Further, the memory chip mounted on the wiring board of the upper package is not limited to the combination of the DRAM chip and the flash memory chip, and only one memory chip (for example, DRAM) having a high driving frequency may be mounted. .

  Further, the plating layer formed on the surface of the bonding lead and land of the wiring board may have a configuration in which a palladium (Pd) layer is laminated on a nickel (Ni) layer and a gold (Au) layer is further laminated.

  Further, if the bonding strength can be ensured on the surface of the bonding lead and the land of the wiring board, it is not necessary to form a plating layer.

  In this embodiment, the semiconductor chip mounted on the lower first package 100 is a controller chip having a control circuit, and the semiconductor chip mounted on the upper second package 200 is a memory chip having a memory circuit ( (DRAM, flash memory). However, the present invention is not limited to this. For example, the semiconductor chip mounted on the upper second package 200 is not limited to the memory chip as long as it is controlled by the semiconductor chip mounted on the lower second package 100. Similarly, the semiconductor chip mounted on the lower first package 100 is not limited to the controller chip as long as it is a semiconductor chip that controls the semiconductor chip mounted on the upper second package 200.

  The present invention can be applied to a package-on-package semiconductor device in which a system is configured by stacking a second semiconductor device on a first semiconductor device.

It is sectional drawing which shows the whole structure of the POP type semiconductor device of this invention. It is sectional drawing which expands and shows a part of 1st semiconductor package of the POP type semiconductor device of this invention. It is a lower surface side top view of the wiring board of the 1st semiconductor package. It is an upper surface side top view of the wiring board of a 1st semiconductor package. It is an upper surface side top view of the wiring board of the 2nd semiconductor package. FIG. 6 is an enlarged cross-sectional view of a main part of the second semiconductor package along the line AA in FIG. 5. It is a lower surface side top view of the wiring board of the 2nd semiconductor package. It is a circuit block diagram which shows the system configuration | structure of the POP type semiconductor device comprised by the 1st semiconductor package and the 2nd semiconductor package. It is an upper surface side schematic plan view of the wiring board of the first semiconductor package. It is a top view which expands and shows a part of FIG. It is sectional drawing along the BB line of FIG. It is sectional drawing along CC line of FIG. It is a principal part enlarged plan view which shows the upper surface of the matrix substrate used for manufacture of a 1st semiconductor package. It is a principal part enlarged plan view which shows the lower surface of the matrix substrate used for manufacture of a 1st semiconductor package. It is a principal part enlarged plan view which shows the upper surface of the matrix substrate used for manufacture of a 1st semiconductor package. It is a principal part enlarged plan view which shows the lower surface of the matrix substrate used for manufacture of a 1st semiconductor package. It is a principal part enlarged plan view of the matrix substrate which shows the manufacturing method of a 1st semiconductor package. It is a principal part enlarged plan view of the matrix substrate which shows the manufacturing method of a 1st semiconductor package. It is a principal part enlarged plan view of the matrix substrate which shows the manufacturing method of a 1st semiconductor package. It is sectional drawing of a 1st semiconductor package. It is a principal part enlarged plan view of the matrix substrate which shows the manufacturing method of a 2nd semiconductor package. It is a principal part enlarged plan view of the matrix substrate which shows the manufacturing method of a 2nd semiconductor package. It is a principal part expanded sectional view of the matrix substrate which shows the manufacturing method of a 2nd semiconductor package. It is sectional drawing of a 2nd semiconductor package. It is a principal part expanded sectional view which shows the 1st semiconductor package for POP type semiconductor devices which this inventor examined.

Explanation of symbols

100 First semiconductor package (first semiconductor device, lower package)
101 Wiring board 102 Controller chip 103 Electrode pad 103d Electrode pad 103f for DRAM chip interface Electrode pad 104f for flash memory chip interface Au wire 105 Solder ball (external terminal)
106 Solder resist 107 Adhesive 108 Sealing body 110 Wiring 110d DRAM chip interface wiring 110f Flash memory chip interface wiring 111 Bonding lead 111d DRAM chip interface bonding lead 111f Flash memory chip interface bonding lead 112 Upper surface side Land 112d Upper surface side land 112f for DRAM chip interface Upper surface side land 113 for flash memory chip interface 113 Via wiring 113d Via wiring 113f for DRAM chip interface Via wiring 114 for flash memory chip interface Internal wiring 115 Lower surface land 115d DRAM chip Lower side land 130 for interface Matrix substrate 20 0 Second semiconductor package (second semiconductor device, upper package)
201 Wiring board 202 DRAM chip 203 Flash memory chip 204 Electrode pad 205 Electrode pad 206 Au wire 207 Au wire 208 Solder ball (external terminal)
209 Solder resist 211 Bonding lead 212 Via wiring 213 Lower surface side land 220 Adhesive 221 Sealing body 230 Matrix substrate

Claims (4)

A semiconductor device in which another semiconductor device having another semiconductor chip is stacked,
(A) The semiconductor device includes:
(A1) An upper surface having a rectangular planar shape, a plurality of bonding leads formed on the upper surface, a plurality of upper surface lands formed on the upper surface and electrically connected to the bonding leads, and a planar shape Is formed in a rectangular shape, and electrically connects the lower surface located opposite to the upper surface, the plurality of lower surface lands formed on the lower surface, and the plurality of upper surface lands and the plurality of lower surface lands, respectively. A wiring board having a plurality of via wirings;
(A2) A main surface, a plurality of electrode pads formed on the main surface, a semiconductor element formed on the main surface and electrically connected to the plurality of electrode pads, and on the opposite side of the main surface A first semiconductor chip having a back surface positioned and mounted on the top surface of the wiring board;
(A3) a plurality of conductive members that respectively electrically connect the plurality of electrode pads of the first semiconductor chip and the plurality of bonding leads of the wiring board;
(A4) a sealing body that seals the first semiconductor chip and the plurality of conductive members;
(A5) a plurality of external terminals provided on each of the plurality of lower surface lands;
Including
The plurality of electrode pads include a first semiconductor chip interface electrode pad and a second semiconductor chip interface electrode pad ;
The plurality of bonding leads include a first semiconductor chip interface bonding lead electrically connected to the first semiconductor chip interface electrode pad via the conductive member, and the conductive member via the conductive member. A second semiconductor chip interface bonding lead electrically connected to the second semiconductor chip interface electrode pad ;
Wherein the plurality of upper surface side land, said first and upper surface lands semiconductor chip interface, the bonding leads and electrically for the second semiconductor chip interface connected first semiconductor chip bonding leads and electrically interface A second semiconductor chip interface top surface land connected to
Wherein the plurality of via wiring, said first and vias interconnect the semiconductor chip interfaces, electrical and top side land for the second semiconductor chip interface connected first semiconductor chip upper surface lands electrically interface A second semiconductor chip interface via wiring connected to
The first semiconductor chip interface via wiring is arranged at a position farther from the first semiconductor chip interface bonding lead than the first semiconductor chip interface upper surface side land,
The second semiconductor chip interface via wiring is disposed between the second semiconductor chip interface bonding lead and the second semiconductor chip interface upper surface land,
The width of at least a part of the wiring connecting the second semiconductor chip interface via wiring and the second semiconductor chip interface upper surface land is such that the second semiconductor chip interface via wiring and the second semiconductor chip interface via wiring Wider than the width of the wiring connecting the semiconductor chip interface bonding leads,
The plurality of lower surface lands include a plurality of first lower surface lands disposed along a side of the lower surface, and a plurality of second lower surfaces disposed on the inner side of the lower surface than the plurality of first lower surface lands. Including side lands,
The first semiconductor chip interface upper surface side land is electrically connected to the first lower surface side land via the first semiconductor chip interface via wiring ,
The semiconductor device, wherein the second semiconductor chip interface upper surface land is electrically connected to the second lower surface land through the second semiconductor chip interface via wiring . The external terminal is not provided on the first lower surface side land,
Wherein the second lower surface side lands, the semiconductor device according to claim 1, wherein said external terminals are provided. A semiconductor system comprising a first semiconductor component and a second semiconductor component stacked on the first semiconductor component,
(A) The first semiconductor component is:
(A1) A first upper surface having a rectangular planar shape, a plurality of first bonding leads formed on the first upper surface, and formed on the first upper surface and electrically connected to the plurality of first bonding leads, respectively. A plurality of first upper surface lands, a planar shape of a rectangular shape, a first lower surface located on the opposite side of the first upper surface, a plurality of first lower surface lands formed on the first lower surface, and A first wiring board having a plurality of first via wirings that electrically connect the plurality of first upper surface side lands and the plurality of first lower surface side lands, respectively;
(A2) a first main surface, a plurality of first electrode pads formed on the first main surface, and a first electrode formed on the first main surface and electrically connected to the plurality of first electrode pads, respectively. A first semiconductor chip mounted on the first upper surface of the first wiring substrate, and having a semiconductor element and a first back surface located on a side opposite to the first main surface;
(A3) a plurality of first conductive members that electrically connect the plurality of first electrode pads of the first semiconductor chip and the plurality of first bonding leads of the first wiring substrate;
(A4) a first sealing body that seals the first semiconductor chip and the plurality of first conductive members;
(A5) a plurality of first external terminals provided on each of the plurality of first lower surface side land,
Including
The plurality of first electrode pads include a first semiconductor chip interface electrode pad and a second semiconductor chip interface electrode pad ,
The plurality of first bonding leads include a first semiconductor chip interface bonding lead electrically connected to the first semiconductor chip interface electrode pad via the first conductive member, and the first conductive lead. A second semiconductor chip interface bonding lead electrically connected to the second semiconductor chip interface electrode pad via a conductive member ;
The plurality of first upper surface side lands include a first semiconductor chip interface upper surface land electrically connected to the first semiconductor chip interface bonding lead, and the second semiconductor chip interface bonding lead. A second semiconductor chip interface top land that is electrically connected ;
The plurality of first via wirings include a first semiconductor chip interface via wiring electrically connected to the first semiconductor chip interface upper surface land, and the second semiconductor chip interface upper surface land. A via wiring for a second semiconductor chip interface electrically connected ;
The first semiconductor chip interface via wiring is arranged at a position farther from the first semiconductor chip interface bonding lead than the first semiconductor chip interface upper surface side land,
The second semiconductor chip interface via wiring is disposed between the second semiconductor chip interface bonding lead and the second semiconductor chip interface upper surface land,
The width of at least a part of the wiring connecting the second semiconductor chip interface via wiring and the second semiconductor chip interface upper surface land is such that the second semiconductor chip interface via wiring and the second semiconductor chip interface via wiring Wider than the width of the wiring connecting the semiconductor chip interface bonding leads,
The plurality of first lower surface-side lands include a plurality of outer lands disposed along a side of the first lower surface, and a plurality of inner lands disposed on the inner side of the first lower surface than the plurality of outer lands. Including
The first semiconductor chip interface upper surface side land is electrically connected to the outer land via the first semiconductor chip interface via wiring,
The second semiconductor chip interface upper surface side land is electrically connected to the inner land via the second semiconductor chip interface via wiring,
(B) The second semiconductor component is
(B1) a second upper surface having a rectangular planar shape, a plurality of second bonding leads formed on the second upper surface, and a second planar surface having a rectangular shape and positioned opposite to the second upper surface. A plurality of second lower surface side lands formed on the lower surface, a plurality of second lower surface side lands formed on the second lower surface, and a plurality of second via wirings that electrically connect the plurality of second bonding leads and the plurality of second lower surface side lands, respectively. A second wiring board having,
(B2) a second main surface, a plurality of second electrode pads formed on the second main surface, a second electrode formed on the second main surface and electrically connected to the plurality of second electrode pads, respectively. A second semiconductor chip mounted on the second upper surface of the second wiring substrate, the semiconductor element, and a second back surface located opposite to the second main surface;
(B3) a plurality of second conductive members that respectively electrically connect the plurality of second electrode pads of the second semiconductor chip and the plurality of second bonding leads of the second wiring board;
(B4) a second sealing body that seals the second semiconductor chip and the plurality of second conductive members;
(B5) a plurality of second external terminals provided on each of the plurality of second lower surface side lands;
Including
The first semiconductor element controls the second semiconductor element;
The plurality of second external terminals are electrically connected to the plurality of first upper surface lands formed on the first wiring board of the first semiconductor component , respectively. The outer land is not provided with the first external terminal,
The semiconductor system according to claim 3 , wherein the inner land is provided with the first external terminal.

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