JP5241371B2 - Wiring display device for multilayer printed circuit board - Google Patents

Description

The present invention relates to a wiring display device for a multilayer printed circuit board, and more particularly to a wiring display device for displaying a wiring state of a multilayer printed circuit board by laminating each layer.

  In recent years, CAD (computer-aided design) is used for designing printed circuit boards. By using this CAD, the wiring layout of the printed circuit board can be easily designed. Design data generated by CAD includes circuit diagram data and board data. The circuit diagram data is information indicating a connection state between components in the actual circuit diagram and component information, and the board data is information indicating a wiring layout of the printed circuit board. By using the board data, a wiring layout diagram in which the signal layer of the designed printed circuit board is viewed from above can be displayed on a computer display. In addition, the function to calculate the characteristic impedance of each wiring on the printed circuit board and the function to display the signal waveform by executing the noise simulation in the predetermined wiring pattern by setting the frequency and on / off level of the input signal are incorporated. CAD is also in practical use. According to these functions, the quality of the designed wiring can be verified.

Recently, multilayer printed circuit boards are often used to realize high-density mounting. In a multilayer printed circuit board, a plurality of signal lines are distributed and arranged in a plurality of signal layers. However, in the above-described conventional wiring layout diagram, it is practically difficult for the user to confirm how the signal lines are distributed and arranged in each of the plurality of signal layers.
For this reason, as a conventional technique, a design support system having a function of displaying a cross-sectional shape corresponding to an arbitrary position of a multilayer printed circuit board has been proposed (see, for example, Patent Document 1). According to this prior art, by specifying a predetermined cutout position on the wiring layout diagram, it is possible to display a board cross-sectional view when the multilayer printed board is cut from the cutout position.
JP 2006-18379 A

However, the above prior art still shows only the wiring layout of an arbitrary layer of the multilayer printed circuit board, and it is easy to determine how the wiring pattern between arbitrary components is arranged on each layer. There was a problem that could not be determined.
Therefore, a conventional technique has been proposed in which wiring pattern portions constituting a wiring pattern between arbitrary components are linearly arranged and displayed. FIG. 19 shows an example of a straight line display of a wiring pattern between two parts, IC1001 and IC300 are IC parts, * TL1 to * TL12 are wiring pattern portions arranged in each layer, and RA1014 is a resistor inserted in the middle of the wiring pattern. It is a part. The components are arranged on the front surface or the back surface of the substrate, the wiring pattern portion is displayed as a drum figure, and the layers arranged by the drum pattern are shown. In addition, the length of each wiring pattern part, characteristic impedance, an arrangement layer, etc. are entered in a dotted line frame.

However, in the display example of FIG. 19, the through pattern and the wiring pattern portion (transmission line) of each layer are expressed in a straight line, which is very difficult to see. In particular, it is difficult to determine in which layer each wiring pattern portion is arranged. In addition, there is a problem that it is difficult to determine whether it exists in the same layer as other wiring pattern portions.
Further, in the display example of FIG. 19, there is a problem that it is unclear where the through hole is and which layer is connected. The characteristic (capacitance) of the through hole may affect the signal pattern, and it may be desired to adjust the diameter, position, and depth, but this is not possible with the prior art. Further, in the display example of FIG. 19, there is a problem that impedance characteristics such as the line type (separate of stripline and microstripline) of each wiring pattern portion cannot be displayed. For this reason, when it turns out that a waveform is distorted by noise simulation, the response | compatibility which considered the line type cannot be performed.
Further, in the linear display of the wiring pattern of FIG. 19, there is a problem that the thickness of the insulating layer in each layer, the presence / absence of the ground pattern and the power supply pattern in each layer, and the arrangement position thereof cannot be displayed. If the ground pattern is present in the vicinity, noise characteristics are improved because a high-frequency current flows through the wiring pattern portion and a current flows back to the ground pattern. On the other hand, if the power supply pattern exists nearby, the noise characteristics deteriorate. For this reason, when it is found that the waveform is distorted by noise simulation during board design or at the completion of board design, it may be necessary to redesign the wiring pattern part closer to the ground pattern or away from the power supply pattern. Then it is impossible.
Further, in the conventional display example of FIG. 19, it is not possible to display the presence / absence of a wiring pattern (cross wiring pattern, parallel wiring pattern) of an adjacent layer that adversely affects the wiring pattern of interest due to crosstalk. . For this reason, when it is found that the waveform is distorted by noise simulation during board design or when board design is completed, it may be necessary to redesign the circuit so that it is separated from the adjacent wiring pattern that gives crosstalk. .

From the above, an object of the present invention is to display a layer and a through-hole position where each wiring pattern portion constituting a wiring pattern between two components is easily identifiable.
Another object of the present invention is to make it possible to display impedance characteristics such as the line type (strip line or microstrip line) of each wiring pattern portion.
Another object of the present invention is to be able to display the thickness of an insulating layer in each layer of a multilayer substrate, the presence / absence of a ground pattern and a power supply pattern that affect the wiring pattern of interest, and the arrangement position thereof.
Another object of the present invention is to make it possible to display the presence / absence of a wiring pattern (cross wiring pattern, parallel wiring pattern) in an adjacent layer that adversely affects the wiring pattern of interest due to crosstalk.

The present invention is a wiring display device that topology-displays the wiring status of a multilayer printed circuit board in a diagram in which the multilayer of the multilayer printed circuit board is represented by a plurality of horizontal lines spaced apart from each other. For each wiring pattern that connects parts to be connected, a layer in which the wiring pattern part constituting the wiring pattern exists, a wiring pattern specifying part that specifies the position of the wiring pattern part, and a predetermined topology display for multilayer wiring When a wiring pattern is specified, each layer is displayed in a stack so as to be identifiable by a plurality of horizontal lines, and each wiring pattern part constituting the specified wiring pattern is indicated by the position information of the layer in which the wiring pattern part exists. Display that displays adjacent wiring pattern parts arranged at specified positions and with different layers by connecting them with vertical lines indicating through-holes. Having.
The wiring display device according to the present invention further includes a circuit diagram database creating unit for creating a circuit diagram database for identifying connection information and component information between the components in the circuit diagram, and the wiring pattern identifying unit is a component in the circuit diagram. When referring to the connection information between the two parts, when branching from the middle point of the two parts, there are two wiring pattern portions sandwiching the branch point, and there is an intermediate part at the middle point of the two parts Includes a wiring pattern portion identification portion for identifying the wiring pattern portion as having two wiring pattern portions on both sides of the intermediate part, and a wiring for identifying a layer and a position in which each of the identified wiring pattern portions is present. It has a pattern part specifying part.
The wiring display device of the present invention appropriately displays the thickness of each layer, the presence / absence of a ground pattern, the presence / absence of a power supply pattern, the presence / absence of a cross wiring pattern, the presence / absence of a parallel wiring pattern, the line type, line width, and line thickness of the wiring pattern portion. .

According to the present invention, when displaying a wiring pattern, each layer is displayed in a stacked manner, and each wiring pattern portion is arranged in a layer in which each layer is present, and the adjacent wiring pattern portions have different layers. Are connected by vertical lines indicating through-holes, so that the actual pattern image matches the displayed topology image, and the wiring pattern can be seen very easily. In particular, it can be seen at a glance at which layer each wiring pattern portion is arranged, and it can be easily determined whether it exists in the same layer as other wiring pattern portions. In addition, it is possible to easily determine where the through-hole is, which layer is connected and the capacity of the through-hole, and adjust the diameter, position, and depth of the through-hole to correct the noise characteristics. Can do.
Further, according to the present invention, it is possible to display the thickness of the insulating layer in each layer, the presence or absence of the ground pattern and the power supply pattern in each layer, the arrangement position, and the like. It is possible to redesign the wiring pattern portion so as to be close to the ground pattern or away from the power supply pattern.
Furthermore, according to the present invention, it is possible to display the presence / absence of a wiring pattern (cross wiring pattern, parallel wiring pattern) of an adjacent layer that adversely affects the wiring pattern of interest due to crosstalk. When it is found that the waveform is distorted, the design can be redesigned so as to be separated from the adjacent intersections and parallel wiring patterns that give crosstalk.
According to the present invention, since it is possible to display impedance characteristics such as the line type (separate stripline and microstripline), line width, and line thickness of each wiring pattern portion, when it is found that the waveform is distorted by noise simulation, It is possible to take into consideration the line type of the wiring pattern portion.

(A) Principle of the Present Invention FIG. 1 is an explanatory diagram of the principle of the present invention.
In the present invention, when displaying the topology of the wiring state of the multilayer printed circuit board, for each wiring pattern that connects between the component IC 1001 that outputs a signal and the component IC 3000 that receives the signal, the wiring pattern portion constituting the wiring pattern * The layer having TL1 to * TL12 and the two-dimensional coordinate position of the wiring pattern portion are specified and stored. When the wiring pattern to be topology-displayed is designated, the layers L1 to L6 of the multi-layer substrate are displayed so as to identify L6, and the wiring pattern portions * TL1 to * TL12 constituting the designated wiring pattern are Adjacent wiring pattern portions having different wiring layers arranged at the position indicated by the two-dimensional coordinate position information of the layer where the wiring pattern portion exists are connected and displayed by vertical lines TH1 to TH10 indicating through holes. .
If the wiring pattern is displayed in this manner, the actual wiring pattern image matches the displayed topology image, and the wiring pattern is very easy to see. In particular, it can be seen at a glance where the wiring pattern portions * TL1 to * TL12 are arranged, and it can be easily determined whether the wiring pattern portions are present in the same layer as other wiring pattern portions. Further, it is possible to easily determine where the through holes TH1 to TH10 are located and which layer is connected.

(B) Board Design Support System FIG. 2 is a configuration diagram of a board design support system having a wiring display function of a multilayer printed circuit board according to the present invention, which is realized by a computer such as a workstation, a personal computer, or a server computer. Can do. The board design support system is used to create design data of a multilayer printed circuit board by CAD, and to efficiently confirm / verify and correct the design data.
The board design support system includes a CPU (processing device) 1, a main memory 2, a display controller 3, a display device 4, an input device 5 such as a mouse and a keyboard, and a disk storage device 6 such as an HDD (hard disk drive). The CPU 1, the input device 5, and the disk device 6 are connected by a bus. The CPU 1 is a processor that controls the operation of the entire system. The disk storage device 6 includes various control programs for displaying a board design and wiring topology, a program unit PRG for storing an OS, and a circuit diagram of a plurality of generated circuit diagrams. A circuit diagram database CDB for storing information, a board database PRDB for storing board information of a plurality of created boards, and the like are provided. In the program part PRG, as a design support program, a circuit diagram CAD program 6a for creating circuit diagram information of a circuit diagram, a substrate CAD program 6b for creating a substrate database, and topology display for controlling topology display of wiring patterns A program 6c, a noise simulation program 6d for performing noise simulation of the designed board, and the like are stored, and loaded into the main memory 2 together with the OS when the apparatus is started up. The CPU 1 creates a circuit diagram database under the control of the design support program. Processing, board database creation processing, wiring pattern topology display processing, and noise simulation are executed. That is, the CPU 1 functionally includes a circuit diagram creation processing unit 1a, a board creation processing unit 1b, a topology display processing unit 1c, and a noise simulation processing unit 1d. The display controller 3 generates a wiring topology image of the multilayer board using the input graphic display data and displays it on the display device (monitor) 4, and the input device 5 inputs various information according to the user's operation.

  As shown in FIG. 3, the circuit diagram creation processing unit 1a of the CPU 1 creates circuit diagram information of a predetermined circuit diagram based on data input from the input device 5 under the control of the circuit diagram CAD program 6a. Save to CDB. Further, as shown in FIG. 4, the board creation processing unit 1b of the CPU 1 is input from the input device 5 while referring to predetermined circuit diagram information stored in the circuit diagram database CDB under the control of the board CAD program 6b. The board information is created based on the obtained data and stored in the board database PRDB.

(C) Circuit Diagram Information FIG. 5 is an explanatory diagram of circuit diagram information created by the circuit diagram creation processing unit 1a. The circuit diagram information consists of a component information section PTINF that describes the component characteristics and performance information of all the components on the circuit diagram, and a net information section NTINF that describes the connection status between the components. Each component has a reference number. It is attached. In the component information section PTINF, a component information number, component characteristics, and component performance information are described in association with a reference number (component). In the net information unit NTINF, a net number Ni (i = 1, 2,...) Is connected to a signal path connecting a signal output component (driver side component) and a signal input component (receiver side component). The reference number and pin number of the driver side component, the reference number and pin number of the component in the middle of the signal path, and the reference number and pin number of the receiver side component are described in association with the net number.
FIG. 6 is an explanatory diagram of net information, and FIG. 6A is a circuit diagram. The pin number P50 of the driver side component of the reference number IC1001 is the pin number P10 of the receiver side component of the reference number IC3001 and the resistor R100. A signal path (wiring pattern) with a net number Ni is formed through connection (with pin numbers P1 and P2). Further, the pin number P50 of the driver side component of the reference number IC1001 is directly connected to the pin number P13 of the receiver side component of the reference number IC3002, thereby forming a signal path (wiring pattern) of the net number Ni + 1. In such a case, the net information of the net numbers Ni and Ni + 1 is as shown in FIG.
When the signal branches from the middle point of the signal path (wiring pattern) of the net number Ni, two wiring pattern parts PP1 and PP2 (in the figure, a dotted drum shape) sandwiching the branching point BP (see (C) in FIG. 6) 6), and there is an intermediate component R100 at the intermediate point of the signal path, there are two wiring pattern portions PP2 and PP3 on both sides of the intermediate component. In the example of FIG. The Ni wiring pattern has three wiring pattern portions PP1, PP2, PP3. In addition, there are two wiring pattern portions PP1 and PP4 in the signal path (wiring pattern) of the net number Ni + 1. As will be described later, the substrate creation processing unit 1b specifies, for each wiring pattern Ni, the layer in which each wiring pattern portion constituting the wiring pattern exists and the two-dimensional coordinate position of the wiring pattern portion.

(D) Board Information FIG. 7 is an explanatory diagram of board information created by the board creation processing unit 1b, and includes a wiring pattern information part LPT, a ground / power supply wiring information part GPP, and a board layer information part PBD. .
In the wiring pattern information part LPT, the following information for specifying the wiring pattern is described for each wiring pattern of the net number Ni (i = 1, 2,...). For each wiring pattern,
(1) Parts symbol
(2) Component position information
(3) Wiring position information
(4) Wiring layer information
(5) Line type information
(6) The through-hole information is described. The component symbol is information for specifying the shape (vertical and horizontal size) and pin number of the component on the board, and the component position information is the two-dimensional coordinate position of the component when a two-dimensional coordinate system is set on the board. And information indicating the layer on which the part is placed. The wiring position information is information for specifying the two-dimensional positions and shapes of all wiring pattern portions (see FIG. 6C, hereinafter referred to as wiring symbols) constituting the wiring pattern specified by the net number Ni. The layer information is information indicating a layer in which each wiring symbol exists. The line type information indicates whether each wiring symbol is a strip line or a microstrip line and information indicating the width W and thickness t of the line, and the through hole information indicates the position of the through hole, the diameter φ, etc. Information.
In the ground / power supply wiring information part GPP, information specifying the layer where the ground pattern exists and the shape of the ground pattern, and information specifying the layer where the power pattern exists and the shape of the power supply pattern are described, respectively. . The substrate layer information PBD describes the thickness of the insulating layer and the thickness of the conductor layer in each layer constituting the substrate.

FIG. 8 is an example of a board information creation processing flow by the board creation processing unit 1b. First, a wiring pattern information part LPT is created (step 101), and then a ground / power supply wiring information part GPP is created (step 102). Finally, a substrate layer information part PBD is created (step 103).
In the wiring pattern information creation processing in step 101, first, i = 1 is set (step 111), and then the driver side, intermediate and receiver side components in the wiring pattern of the net number Ni are identified with reference to the circuit diagram information, The part symbol information and part position information of the part are determined. Information that can be automatically determined is automatically determined, and information that the board designer needs to input is input from the input device 5 and specified (step 112). Next, the wiring pattern information part LPT of the net number Ni is specified with reference to the circuit diagram information. That is, all wiring pattern portions (wiring symbols) constituting the wiring pattern of the net number Ni are extracted, and wiring position information, wiring layer information, line type information, etc. of each wiring symbol are specified. Information that can be automatically determined is automatically determined, and information that the board designer needs to input is input from the input device 5 and specified. Step 113 is repeated until necessary information is specified for all the wiring symbols (step 114).
Next, the through hole information (through hole position, through hole diameter, layer to which the through hole is connected, etc.) in the wiring pattern of the net number Ni is specified (step 115). The through-hole position and the layer to which the through-hole is connected can be automatically calculated with reference to the wiring position information and wiring layer information of the wiring symbol specified in step 113.
Next, it is checked whether the specific work of the wiring pattern information part LPT of all wiring patterns is completed (step 116). If not completed, i is incremented (step 117), and the processing after step 112 is performed for the next wiring pattern. repeat.
When the work of specifying the wiring pattern information of all the wiring patterns is completed, the ground pattern and the power supply pattern information are specified by data input from the input device (step 102), and finally the substrate layer information is specified in the same manner (step 103). ). Thus, the board information creation process is completed.

(E) Wiring Pattern Topology Display Control FIG. 9 is a block diagram of a topology display processing unit for executing wiring pattern topology display processing. The same reference numerals are given to the same parts as those in FIG. The topology display processing unit 1c is a part of the CPU 1, and executes predetermined processing in accordance with the topology display program 6c. The topology display data creation unit 11, the wiring symbol characteristic calculation unit 12, and the presence / absence of cross / parallel patterns. A determination unit 13 and a ground / power supply pattern presence / absence determination unit 14 are provided.
FIG. 10 is a processing flow of the topology display processing unit.
The input device 5 selects a predetermined wiring pattern Ni from the wiring pattern list of the substrate and requests the topology display processing unit 1c to display the topology of the wiring pattern. In order to specify the wiring pattern to be displayed, it is also possible to display a circuit diagram and specify the net in the circuit diagram by specifying the net.
The topology display processing unit 1c monitors whether the topology display is requested (step 201). When the topology display is requested, the topology display data creation unit 11 is activated. As a result, the topology display data creation unit 11 reads the wiring pattern information part LPT, the ground / power supply wiring information part GPP, and the board layer information part PBD of the net number Ni selected by the input device 5 from the board database PRDB. Next, the topology display data creation unit 11 creates data for topology display of the wiring pattern Ni as shown in FIG. 1 based on the read wiring pattern information, the thickness of each layer of the substrate, and the like. Input (step 202). That is, the topology display data creation unit 11 (1) data for displaying the layers L1 to L6 in a stacked manner in consideration of their thicknesses, (2) components constituting the wiring pattern of the net number Ni and the wiring symbols Is displayed at a predetermined position of the layer where the component and each wiring symbol exist, and (3) adjacent wiring pattern portions having different layers are represented by vertical lines TH1 to TH10 indicating through holes. Data to be connected and displayed is created, and the created data (topology display data) is input to the display controller 3.

Next, the topology display data creation unit 11 determines whether the thickness of each layer is thicker or thinner than the set thickness, and inserts a thick dotted line for a thick layer and inserts a thin dotted line for a thin layer for display. The thickness specifying dotted line data is created and input to the display controller 3 (step 203).
Thereafter, the wiring symbol characteristic calculator 12 calculates the length (mm) of each wiring symbol, the propagation speed (mm / ps) of the high frequency signal, the characteristic impedance (ohm), and the capacitance value (pF) of each through hole. These calculation results, line type information (line type, line width W, line thickness) and the like are input to the display controller 3 together with their display position data (step 204).
When the characteristic calculation processing is completed, the intersection / parallel pattern presence / absence determining unit 13 determines, for each wiring symbol, whether a wiring pattern crossing the wiring symbol exists in a layer adjacent to the layer where the wiring symbol exists, or the wiring It is checked whether there is a wiring pattern parallel to the symbol, and graphic data indicating the determination result is created and input to the display controller 3 (step 205). Whether cross wiring patterns or parallel wiring patterns exist can be checked by referring to the two-dimensional position information of each wiring symbol.
FIG. 11 is a detailed processing flow of step 205. First, i is set to 1 (step 301), and it is determined whether there is an intersecting pattern intersecting with the i-th wiring symbol in the adjacent layer (step 302), and then whether there is a parallel pattern parallel to the i-th wiring symbol in the adjacent layer. Determination is made (step 303). Next, it is checked whether the above determination processing is completed for all wiring symbols (step 304). If the processing is not completed, i is incremented (step 305), and the processing from step 302 is repeated for the next wiring symbol. When the above determination processing is completed for all the wiring symbols, graphic data indicating the determination result is created and input to the display controller 3 (step 306).

When the cross pattern and parallel pattern presence / absence determination processing is completed, the ground / power supply pattern presence / absence determination unit 14 checks for each wiring symbol whether the ground pattern and the power supply pattern exist above or below the wiring symbol in all layers. Graphic data indicating the determination result is input to the display controller 3 (step 206). Whether the ground pattern and the power supply pattern exist can be checked with reference to the two-dimensional position information of each wiring symbol and the two-dimensional position information of the ground pattern and the power supply pattern.
FIG. 12 is a detailed processing flow of step 205. First, i = 1 (step 401), it is determined whether a ground pattern exists above or below the i-th wiring symbol in all layers (step 402), and then above or below the i-th wiring symbol in all layers. It is determined whether a power supply pattern exists (step 403). Next, it is checked whether or not the above determination processing has been completed for all the wiring symbols (step 404). If the processing has not been completed, i is incremented (step 405), and the processing after step 402 is repeated for the next wiring symbol. When the above determination processing is completed for all the wiring symbols, graphic data indicating the determination result is created and input to the display controller 3 (step 406). Note that graphic data is created so that there is no ground pattern on both sides of the vertical line indicating the through hole.
If the determination process of the presence / absence of the ground pattern and the power supply pattern is completed in step 206, the display controller 3 generates a topology image of the wiring pattern using the input display data and displays it on the display device 4 (step 207). .

(F) Example of topology display FIG. 1 is an example of topology display of a wiring pattern using the display data created in step 202 of FIG. 10. The actual wiring pattern image matches the displayed topology image and The wiring pattern is easy to see.
FIG. 13 is an example in which the wiring pattern is topologically displayed using the display data that is the processing results of step 202 and step 204 of FIG. 10, and the points different from FIG. 1 are shown below the wiring symbols * TH1 to * TL12. This is the point that additional values C1 to C12 indicating the characteristic value, line type, line width, and line thickness of the wiring symbol and the numerical value indicating the through hole capacitance (pF) are displayed. FIG. 14A is an enlarged view of a dotted line A portion of FIG. 13, and FIG. 14B is an explanatory diagram of an additional portion of a wiring symbol * TL9. The additional part of each wiring symbol includes (1) the length of the wiring symbol (transmission path), (2) propagation speed, (3) characteristic impedance, (4) symbol name, and (5) layer information where the symbol exists. In addition, (6) a line type, a line width W, and a line thickness t indicating the stripline / microstripline are added. A numerical value CP indicating the capacity of the through hole calculated by the wiring symbol characteristic calculation unit 12 is displayed on the through hole TH1.

  FIG. 15 is an example in which the wiring pattern is topologically displayed using the display data that is the processing results of step 202 and step 203 in FIG. 10. The difference from FIG. 1 is a dotted line indicating whether the insulator of each layer is thick or thin. TDL and FDL are displayed. The layer where the thin dotted line TDL is inserted is a thin layer whose insulator thickness is less than or equal to the set value, and the layer where the thick dotted line FDL is inserted is a thick layer whose insulator thickness is equal to or greater than the set value Means. In addition, although thick or thin is displayed so as to be distinguishable by a thin dotted line and a thick dotted line, an appropriate display form such as changing the color can be adopted. In the above, two types of thickness, thick or thin, are shown. However, three or more thicknesses should be shown, or the actual insulator thickness should be entered in each layer. You can also. By displaying the thickness of the insulating layer, the magnitude of the distance from the wiring symbol to the ground pattern can be grasped.

  FIG. 16 is an example in which the wiring pattern is topologically displayed using the display data that is the processing result of step 202 and step 205 in FIG. 10. The difference from FIG. 1 is that the cross wiring pattern intersecting with the wiring symbol is in the adjacent layer. A figure (elliptical figure) CRP indicating the existence and a figure (dotted line) PLP indicating that parallel parallel wiring patterns exist in the adjacent layer are displayed. From FIG. 16, it can be seen that the cross wiring pattern exists in the layer below the wiring symbol * LT10, * TL11, * TL1, * TL4, * TL6 and the cross wiring pattern exists in the layer above the wiring symbol * TL8. . In particular, it can be seen that there are three cross wiring patterns under the wiring symbol * LT1. Also, one parallel wiring pattern may exist in the layer above the wiring symbol * TL11, * TL2, * TL4, * TL6, and one parallel wiring pattern may exist in the layer below the wiring symbol * TL7. I understand.

FIG. 17 shows an example in which the wiring pattern is topologically displayed using the display data that is the processing results of step 202 and step 206 in FIG. 10. The difference from FIG. 1 is that the ground pattern or power pattern is placed above or below the wiring symbol. This is a point displaying a straight line indicating that exists. Note that FIG. 17 shows a case where no power supply pattern exists above or below each wiring symbol, and only a straight line GPL indicating that a ground pattern exists is displayed. In addition, the ground pattern is cut and displayed on both sides of the vertical line indicating the through hole.
FIG. 18 shows an example in which the wiring pattern is topologically displayed using the display data that is the processing result of steps 202, 203, 205, and 206 in FIG.
As described above, when the topology of the wiring pattern is displayed, the topology of the wiring pattern of FIG. 1 is used as a basis, the figure indicating the thickness of the additional part and the layer, the figure indicating the existence of the cross wiring pattern, the figure indicating the existence of the parallel wiring pattern, A graphic indicating the presence of a pattern, a graphic indicating the presence of a power supply pattern, and the like can be added to the basic topology and displayed in appropriate combination.

It is a principle explanatory view of the present invention. It is a block diagram of the board | substrate design assistance system provided with the wiring display function of the multilayer printed circuit board of this invention. It is operation | movement explanatory drawing of a circuit diagram preparation process part. It is operation | movement explanatory drawing of a board | substrate creation process part. It is explanatory drawing of circuit diagram information. It is explanatory drawing of net information. It is explanatory drawing of board | substrate information. It is an example of a substrate information creation processing flow. It is a block diagram of the topology display process part which performs the topology display process of a wiring pattern. It is a processing flow of a topology display process part. It is a flow for determining whether or not there are cross wiring patterns and parallel wiring patterns. It is a flow for determining whether or not there is a ground pattern and a power supply pattern. It is the 1st topology display example of a wiring pattern. It is topology display explanatory drawing. It is the 2nd topology display example of a wiring pattern. It is a 3rd topology display example of a wiring pattern. It is a 4th topology display example of a wiring pattern. It is a 5th topology display example of a wiring pattern. It is topology display explanatory drawing of the conventional wiring pattern.

Explanation of symbols

1 CPU (Processor)
1a Circuit diagram creation processing unit 1b Board creation processing unit 1c Topology display processing unit 1d Noise simulation processing unit 2 Main memory 3 Display controller 3
4 Display device 5 Input device 6 Disk storage device 6a Circuit diagram CAD program 6b Substrate CAD program 6c Topology display program 6d Noise simulation program
PRG program part
CDB schematic database
PRBD substrate database

Claims (8)

In the wiring display device that displays the topology of the wiring state of the multilayer printed circuit board in a diagram that represents the multilayer of the multilayer printed circuit board with a plurality of horizontal lines at intervals ,
For each wiring pattern that connects between a component that outputs a signal and a component that receives a signal, the layer in which the wiring pattern portion constituting the wiring pattern exists and the wiring pattern specification that specifies the two-dimensional coordinate position of the wiring pattern portion Part,
When a predetermined wiring pattern to be displayed in the topology of the multilayer wiring is specified, each layer is displayed in a stack so as to be identifiable by a plurality of horizontal lines , and each wiring pattern portion constituting the specified wiring pattern is displayed in the wiring pattern. A display unit that is arranged at a predetermined position of a layer in which the part exists and that displays adjacent wiring pattern parts having different arranged layers by connecting with vertical lines indicating through holes;
A wiring display device for a multilayer printed circuit board, comprising: A circuit diagram database creating unit for creating a circuit diagram database for identifying connection information and component information between the components in the circuit diagram;
The wiring pattern specifying unit refers to the connection information between components, and when branching from an intermediate point between the two components, there are two wiring pattern portions sandwiching the branch point, and between the two components. A wiring pattern part identification unit for identifying the wiring pattern part as having two wiring pattern parts on both sides of the intermediate part when an intermediate part is present at the point;
A wiring pattern portion specifying unit for specifying the layer in which each specified wiring pattern portion exists and two-dimensional coordinate position information;
The wiring display device for a multilayer printed circuit board according to claim 1, comprising: A board information specifying unit for specifying board information including the thickness of the insulator of each layer;
The display unit displays a thickness figure indicating the thickness of each displayed layer using the substrate information in each layer.
3. The multilayer printed circuit board wiring display device according to claim 1, wherein the wiring display device is a multilayer printed circuit board. A substrate information specifying unit for specifying a layer in which the ground pattern exists and a two-dimensional position of the ground pattern in the layer;
A determination unit that refers to the position information of each wiring pattern portion and the position information of the ground pattern, and checks whether a ground pattern is present in a layer above or below each wiring pattern portion,
When the display unit is present, the position where the ground pattern exists in the layer is displayed in an identifiable manner, and the both sides of the vertical line indicating the through hole are displayed as no ground pattern is present.
3. The multilayer printed circuit board wiring display device according to claim 1, wherein the wiring display device is a multilayer printed circuit board. A board information specifying unit for specifying a layer where the power supply pattern exists and a two-dimensional position of the power supply pattern in the layer;
A determination unit that refers to the position information of each wiring pattern portion and the position information of the power supply pattern, and checks whether a power supply pattern exists above or below each wiring pattern portion,
3. The multilayer printed circuit board wiring display device according to claim 1, wherein, when the display unit is present, the position where the power supply pattern is present in the layer is displayed in an identifiable manner. A determination unit that refers to the position information of each wiring pattern portion and checks whether there is another wiring pattern that intersects the wiring pattern portion in an adjacent layer for each wiring pattern portion,
3. The multilayer printed circuit board wiring display device according to claim 1, wherein, when present, the display unit displays a graphic indicating that a cross wiring pattern is present at an existing position. . A determination unit that refers to the position information of each wiring pattern part and checks whether there is another wiring pattern parallel to the wiring pattern part in an adjacent layer for each wiring pattern part,
The display unit displays a graphic indicating that a parallel wiring pattern is present at an existing position, if present.
3. The multilayer printed circuit board wiring display device according to claim 1, wherein the wiring display device is a multilayer printed circuit board. The wiring pattern specifying unit specifies the line type, line width, and line thickness of each wiring pattern part, and the display unit displays the line type, line width, and line thickness in the vicinity of the wiring pattern part.
The wiring display device for a multilayer printed circuit board according to claim 1.

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