JP5128822B2 - Display device - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a display device that improves contrast when an image is displayed.

  Active matrix display devices such as liquid crystal display devices are widely used as display devices in mobile devices such as mobile phones and portable information terminals because of their thinness, high definition, and low power consumption. In particular, mobile phones have become more sophisticated, and the number of scenes in which moving images are used in one-segment broadcasting, playback of recorded videos, and applications including games has increased. When such a moving image is displayed, a high-quality image can be obtained by improving the contrast.

With respect to such an improvement in contrast, the following Patent Document 1 describes that the contrast is enhanced using a look-up table (hereinafter referred to as “LUT”).
JP 2006-24176 A

  When emphasizing the contrast by the LUT method, an LUT corresponding to the number of gradations, for example, “256 gradations × 8 bits = 2048 bits” if the number of gradations is 256 gradations and the gradation data is 8 bits. A size LUT is required, and there is a concern about an increase in cost.

  In addition, there is a current method in which a grayscale voltage generation circuit generates a grayscale voltage for a positive electrode and a negative electrode, switches this grayscale voltage, and outputs it to a liquid crystal display device, instead of the LUT method. However, since the gradation voltage generation circuit in this current method generates a gradation voltage by, for example, dividing the reference voltage by resistance, when the voltage dropped by resistance division is Vd, for example, the reference voltage When V0 is V0, the gradation voltage of V1 has a relationship of V1 = V0−Vd, and the same relationship applies to other gradation voltages (V2 to V63). Accordingly, the gradation voltages (V1 to V63) are all different, and any of the gradation voltages (V1 to V63) cannot be made the same.

  The present invention is characterized in that contrast characteristics are controlled by a resistor ladder circuit that generates a gradation voltage. That is, when the gradation voltage is generated by the resistance ladder circuit, the gradation voltage of the same voltage is generated by arbitrarily passing the resistance between gradations and not dividing the resistance.

  Accordingly, since contrast characteristics similar to those of the LUT method can be obtained, a large-capacity LUT is not required other than a register necessary for storing parameters for controlling the resistance ladder circuit. .

  As described above, according to the present invention, since the contrast characteristic can be controlled without using the LUT, a low-cost display device can be realized. In addition, the present invention can be used regardless of the size of the display device, but is particularly suitable for display devices such as mobile phones and portable information terminals that are severely limited in cost and circuit area.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a configuration diagram of a liquid crystal display device according to the present embodiment. In this embodiment, display is performed with 64 gradations.

  In FIG. 1, 100 is a CPU, 101 is a signal line driver circuit, 102 is a system interface, 103 is a control register, 104 is a timing controller, 105 is a γ adjustment register, 108 is a gradation voltage generation circuit, and 114 is a memory control circuit. 115 is a display RAM, 116 is a latch circuit, 117 is an output control circuit, 118 is a scanning line driving circuit, and 119 is a liquid crystal panel.

  Here, the signal line driving circuit 101 is a so-called display memory built-in controller / driver, and the configuration and operation of an internal block of the signal line driving circuit 101 will be described below.

  The system interface 102 receives display data and various set values (hereinafter referred to as “instructions”) output from the CPU 100 of the external system, and outputs them to the control register 103. Here, the instruction is information for determining the internal operation of the signal line driver circuit 101 and includes various parameters such as a frame frequency, the number of drive lines, and a drive voltage.

  The control register 103 is a block that stores instruction data and outputs it to each block. For example, instructions related to the frame frequency, the number of drive lines, and the data voltage switching timing are output to the timing controller 104, and instructions related to the potential of the gradation voltage are output to the γ adjustment register 105. The display data is also temporarily stored in the control register 103, and is output to the memory control circuit 114 together with instructions for indicating the display position.

  The memory control circuit 114 is a block that performs write and read operations of the display RAM 115. First, during a write operation, a signal for selecting an address of the display RAM 115 is output based on the display position instruction transferred from the control register 103. At the same time, display data is transferred to the display RAM 115. With this operation, display data can be written to a predetermined address in the display RAM 115. On the other hand, during the read operation, the operation of sequentially selecting a predetermined word line group in the display RAM 115 one by one is repeated. With this operation, the display data on the selected word lines can be read all at once via the bit lines. It should be noted that setting of the range of the word line to be read, one selection period (equivalent to one scanning period), selection operation repetition period (equivalent to one frame period), and the like are instructed by the instruction.

  The display RAM 115 has word lines and bit lines corresponding to the scanning lines and signal lines of the liquid crystal panel 119, and performs display data write operations and read operations. Note that the read display data is temporarily held by the latch circuit 116 and then output to the output control unit 117.

  The timing controller 104 self-generates and outputs a signal group indicating one scanning period, one frame period, and the like based on a reference clock generated by a built-in oscillator.

  The γ adjustment register 105 includes a positive register 106 and a negative register 107. The instruction input from the control register 103 is held in the positive register 106 and the negative register 107 and output to the gradation voltage generation circuit 108.

  The gradation voltage generation circuit 108 includes a positive ladder circuit 109 and a negative ladder circuit 110 as a reference ladder circuit, a selection circuit 111, a buffer circuit 112, and a gradation voltage ladder circuit 113.

  First, based on the γ adjustment signal inputted from the γ adjustment register 105, the differential voltage between the reference high voltage and the reference low voltage is resistance-divided by the positive ladder circuit 109 and the negative ladder circuit 110 to obtain 12 levels. And a reference voltage (hereinafter referred to as “reference voltage”).

  The selection circuit 111 selects one of the reference voltages generated by the positive ladder circuit 109 and the negative ladder circuit 110 based on the alternating signal and outputs the selected reference voltage to the buffer circuit 112. The buffer circuit 112 buffers the input reference voltage by a voltage follower circuit and outputs the buffered voltage to the gradation voltage ladder circuit 113.

  The gradation voltage ladder circuit 113 divides the resistance based on the inputted 12-level reference voltage, generates a gradation voltage of 64 levels, and outputs it to the output control circuit 117.

  The output control circuit 117 selects one level among the 64 levels of gradation voltages input from the gradation voltage generation circuit 108 based on the display data input from the latch circuit 116, and the signal line 121 of the liquid crystal panel 119. Output to.

  The scanning line driving circuit 118 outputs the scanning voltage (“high” level in this embodiment) indicating the selected state line-sequentially to the scanning line 120 of the liquid crystal panel 119 in synchronization with one scanning period. Here, the timing of outputting the “high” level to the head scanning line is synchronized with the timing of reading the head word line in the display RAM 115.

  The liquid crystal panel 119 is a so-called active matrix type flat panel in which a switching transistor 122 is disposed in each pixel portion located at the intersection of the signal line 121 and the scanning line 120. The source terminal of the transistor 122 is connected to the output of the output control circuit 117 through the signal line 121, and the gate terminal is connected to the output of the scanning line driving circuit 118 through the scanning line 120. The drain terminal of the transistor 122 is connected to the display element 123. Note that a common electrode is connected to the opposite side of the display element 123, and a Vcom voltage is output to the common electrode. Therefore, in the scanning line 120 in the selected state, the voltage difference between the gradation voltage and the Vcom voltage becomes the voltage applied to the display element 123. The type of the display element 123 is typically liquid crystal or organic EL, but other elements may be used as long as the display luminance can be controlled by voltage.

  In this embodiment, since the Vcom potential at the positive electrode is 0 V and the Vcom potential at the negative electrode is 4 V, the luminance is increased by increasing the gradation voltage at the positive electrode (by reducing the gradation voltage). When the negative electrode is negative, the luminance is increased by decreasing the gradation voltage (the luminance is decreased by increasing the gradation voltage).

  Next, the internal block configuration and operation of the timing controller 104 will be described with reference to FIG. In FIG. 2A, 200 is a register, 201 is an internal clock generation circuit, 202 is a clock counter, 203 is a horizontal synchronization signal generation circuit, 204 is an AC signal generation circuit, 205 is a line counter, and 206 is a vertical synchronization signal generation. Circuit.

  One scan period, one frame period, etc. input from the control register 103 shown in FIG. 1 are held in the register 200 and output to the clock counter 202 and the line counter 205.

  The internal clock generation circuit 201 generates a reference operation clock CLK and outputs it to each circuit. Each circuit operates based on the reference clock CLK generated by the internal clock generation circuit 201.

  The clock counter 202 counts the reference clock up to the CLK value of one scanning period input from the register 200, and outputs the clock count value to the horizontal synchronization signal generation circuit 203. Note that the clock count value of the clock counter 202 exceeds the CLK value of one scanning period, or is cleared (count value) at the falling edge of the input vertical synchronization signal Vsync (“low” active in this embodiment). = "0").

  The horizontal synchronization signal generation circuit 203 generates and outputs a horizontal synchronization signal CL1 based on the clock count value input from the clock counter 202. The horizontal synchronization signal CL1 rises when the clock count value is “0” (“high” active in this embodiment) and is output “high” until the active period of the horizontal synchronization signal input from the register 200. .

  The line counter 205 counts up to the number of lines in one frame period input from the register 200 in synchronization with the rising edge of the horizontal synchronization signal CL1, and outputs the line count value to the vertical synchronization signal generation circuit 206. The line count value of the line counter 205 is cleared (count value = “0”) at the falling edge of the input vertical synchronization signal Vsync or exceeds the number of lines in one frame period.

  The vertical synchronization signal generation circuit 206 generates and outputs a vertical synchronization signal FLM based on the count value input from the line counter 205. The vertical synchronization signal FLM rises when the line count value is “0” (“high” active in this embodiment), and is output “high” until the active period of the vertical synchronization signal input from the register 200. .

  The AC signal generation circuit 204 generates and outputs an AC signal M based on the AC signal input from the register 200 (in this embodiment, “0” during frame AC driving and “1” during line AC driving).

  Next, the operation timing of the signal group generated by the timing controller 104 will be described with reference to FIG. A horizontal synchronization signal CL1 is generated based on the input vertical synchronization signal Vsync. The horizontal synchronization signal CL1 is activated by the number of lines set in the register 200.

  The alternating signal M repeatedly outputs “high” and “low” according to the alternating method set in the register 200. In this embodiment, since line AC driving is set, “high” or “low” is output in one scanning period.

  The display data held in the display RAM 115 is read by one frame in one frame period.

  Next, the configuration of the internal block of the positive electrode register 106 shown in FIG. 1 will be described with reference to FIG. The circuit configuration and operation of the negative register 107 are the same as those of the positive register 106.

  In FIG. 3A, 300 is a normal γ register, 301 is a contrast enhancement γ register, 302 is an amplitude register, 303 and 305 are inclination registers, 304 and 306 are fine adjustment registers, and 307 and 308 are selection circuits.

  The γ register values input from the control register 103 shown in FIG. 1 are classified into amplitude register values, slope register values, and fine adjustment register values. By outputting these register values to the gradation voltage generation circuit 108, By adjusting the variable resistors in the positive ladder circuit 109 and the negative ladder circuit 110 in the regulated voltage generation circuit 108, the potential of the gradation voltage can be set.

  The amplitude register value is a setting value for adjusting the amplitude of the gradation voltage, and the inclination adjustment register value is for adjusting the inclination near the center of the gradation number-gradation voltage characteristics without greatly changing the dynamic range. The fine adjustment register value is a setting value for fine adjustment of the gradation voltage level.

  The amplitude adjustment register value, the inclination register value, and the fine adjustment register value are held in the normal γ register 300, the amplitude register 302 in the contrast enhancement γ register 301, the inclination registers 303 and 305, and the fine adjustment registers 304 and 306, respectively. The

  Note that the amplitude register value is the same in all cases (the amplitude of the gradation voltage is constant) regardless of the presence or absence of contrast enhancement. Therefore, the amplitude register value is held only in the amplitude register 302 of the normal γ register 300, and the contrast Even at the time of emphasis, by outputting the amplitude register value held in the amplitude register 302 to the gradation voltage generation circuit 108, an increase in circuit scale is suppressed.

  When the contrast enhancement register data input from the control register 103 (in this embodiment, “contrast enhancement is used when“ high ”and contrast enhancement is not used when“ low ”) is“ low ”, the selection circuit 307 is normal γ. The inclination register value held in the inclination register 303 of the register 300 is selected and output to the gradation voltage generation circuit 108. When the contrast enhancement register data is “high”, the inclination register value held in the inclination register 305 of the contrast enhancement γ register 301 is selected and output to the gradation voltage generation circuit 108.

  When the contrast enhancement register data input from the control register 103 is “low”, the selection circuit 308 selects the fine adjustment register value held in the fine adjustment register 304 of the normal γ register 300 and supplies the gradation voltage generation circuit 108 with the fine adjustment register value. Output. When the contrast enhancement register data is “high”, the fine adjustment register value held in the fine adjustment register 306 of the contrast enhancement γ register 301 is selected and output to the gradation voltage generation circuit 108.

  Next, the internal configuration of each register in the normal γ register 300 will be described with reference to FIG. The amplitude register 302 is composed of two registers VRP0 to VRP1, and adjusts the amplitude value of the gradation voltage according to register values held in the two registers VRP0 to VRP1. The slope register 303 is composed of two registers SRP0 to SRP1, and adjusts the slope near the center of the gradation number-gradation voltage characteristics by the register values held in the two registers SRP0 to SRP1. . The fine adjustment register 304 includes 10 registers PRP0 to PRP9, and finely adjusts the gradation voltage level according to register values held in the 10 registers PRP0 to PRP9. The internal configuration of the contrast enhancement γ register 301 is the same as the internal configuration of the inclination register 303 and the fine adjustment register 304.

  Next, the internal block configuration of the positive ladder circuit 109 shown in FIG. 1 will be described with reference to FIG. In FIG. 4, 400 to 409 are switches (hereinafter referred to as “SW”), 410 to 421 are fixed resistors, and 422 to 435 are variable resistors.

  The resistance values of the variable resistor 422 and the variable resistor 435 are set according to the amplitude register values VRP0 and VRP1 input from the amplitude register 302. The resistance values of the variable resistor 428 and the variable resistor 429 are set according to the slope register values SRP0 and SRP1 input from the slope register 303. The resistance values of the variable resistors 423 to 427 and the variable resistors 430 to 434 are set according to the fine adjustment register values PRP0 to PRP4 and PRP5 to PRP9 input from the fine adjustment register 304.

  Note that the minimum value of the resistances of the variable resistors 422 to 435 is set to a resistance value (ideal 0Ω) that does not cause a potential difference between gradations by resistance voltage division. Further, when the SWs 400 to 409 are “on”, the on-resistance is sufficiently smaller than the fixed resistors 410 to 420, and when the SW 400 to 409 is “off”, the off-resistance is sufficiently larger than the fixed resistors 410 to 420. It is a big one.

  When the contrast enhancement register data is “low” (when contrast enhancement is not used), all the SWs 400 to 409 are turned off, and a current flows through the fixed resistors 410 to 414 and the fixed resistors 416 to 420, whereby the resistance of each fixed resistor is set. The reference high voltage VDH is divided by the value and the resistance value of each variable resistor to generate 12-level reference voltages V0P / V1P / V2P / V4P / V8P / V20P / V43P / V55P / V59P / V61P / V62P / V63P. The reference voltages V0P to V63P all have different potentials, and none of them has the same potential.

  V0P is the positive potential of gradation number 0, V1P is the positive potential of gradation number 1, V2P is the positive potential of gradation number 2, and V4P is the positive potential of gradation number 4. V8P is the positive potential of gradation number 8, V20P is the positive potential of gradation number 20, V43P is the positive potential of gradation number 43, V55P is the positive potential of gradation number 55, and V59P is The positive potential of gradation number 59, V61P is the positive potential of gradation number 61, V62P is the positive potential of gradation number 62, and V63P is the positive potential of gradation number 63.

  The 12-level reference voltage is buffered by the buffer circuit 112 shown in FIG. 1 and then output to the gradation voltage ladder circuit 113. The gradation voltage ladder circuit 113 is a resistor based on the 12-level reference voltage. In the case of 64 gradation display, the remaining gradation number 3, gradation number 5-7, gradation number 9-19, gradation number 21-42, gradation number 44-54, gradation number are displayed. The gradation voltages of 56 to 58 and gradation number 60 are generated. The gradation number-gradation voltage characteristic at this time is as shown in FIG.

  When the contrast emphasis register data is “high” (when contrast emphasis is used) and the contrast emphasis switching register data is “high”, the SWs 400 to 404 are turned on, a current flows through the SWs 400 to 404, and the fixed resistors 410 to 414. There is no current flowing through. Further, since the SWs 405 to 409 are “off”, a current flows through the fixed resistors 416 to 420.

  At this time, when the resistance values of the variable resistors 422 to 427 are set to the minimum value with the fine adjustment register values PRP0 to PRP4 and the amplitude register value VRP0, the reference high voltage VDH is not divided by resistors, so that the six-level reference voltage V43P The potential of ˜V63P becomes the same potential as the reference high voltage VDH is output. The other six-level reference voltages V0P to V20P do not have the same potential because they are divided by resistance because current flows through the fixed resistors 416 to 420.

  Next, when the contrast emphasis register data is “high” (when contrast emphasis is used) and the contrast emphasis switching register data is “low”, the SWs 400 to 404 are “off”, and a current flows through the fixed resistors 410 to 414. Further, since the SWs 405 to 409 are “on”, current flows through the SWs 405 to 409 and no current flows through the fixed resistors 416 to 420.

  At this time, when the resistance values of the variable resistors 430 to 435 are set to the minimum values with the fine adjustment register values PRP5 to 9 and the amplitude register value VRP1, the reference high voltage VDH is not divided by the resistance, so that the six-level reference voltages V0P to VOP The potential of V20P becomes the same potential as the reference low voltage GND is output. The other six-level reference voltages V63P to V43P do not have the same potential because current flows through the fixed resistors 410 to 414 and is divided by the resistors.

  With the above operation, when the contrast enhancement switching register data is “high” as in the gradation number-gradation voltage characteristic shown in FIG. 6B, V43 to V63 and the contrast enhancement switching register data is “low”. In some cases, the same voltage can be output in the gradations of V0 to V20.

  Next, the configuration of the internal block of the negative ladder circuit 110 will be described with reference to FIG. In FIG. 5, 500 to 509 are SWs, 510 to 521 are fixed resistors, and 522 to 535 are variable resistors. The resistance values of the fixed resistors 510 to 521 and the variable resistors 522 to 535 are the same as the resistance values of the fixed resistors 410 to 421 and the variable resistors 422 to 435 of the positive ladder circuit 109 shown in FIG.

  The variable resistor 522 and the variable resistor 535 set resistance values according to the amplitude register value input from the γ adjustment register 105. The variable resistance 528 and the variable resistance 529 set resistance values according to the slope register value input from the γ adjustment register 105. The variable resistors 523 to 527 and the variable resistors 530 to 534 set resistance values according to the fine adjustment register value input from the γ adjustment register 105.

  Note that the minimum value of the resistances of the variable resistors 522 to 535 is set to a resistance value (ideal 0Ω) that does not cause a potential difference between gradations by resistance voltage division. Further, when the SWs 500 to 509 are “on”, the on-resistance is sufficiently smaller than the fixed resistors 510 to 520, and when the SW 500 to 509 is “off”, the off-resistance is relative to the fixed resistors 510 to 520. It's big enough.

  When the contrast enhancement register data is “low” (when contrast enhancement is not used), all the SWs 500 to 509 are turned off, and a current flows through the fixed resistors 510 to 514 and the fixed resistors 516 to 520, whereby the resistance of each fixed resistor. The reference high voltage VDH is divided by the value and the resistance value of each variable resistor to generate 12-level reference voltages V0N / V1N / V2N / V4N / V8N / V20N / V43N / V55N / V59N / V61N / V62N / V63N. The potentials of the reference voltages V0N to V63N are all different, and none of them has the same potential.

  V0N is the negative potential of gradation number 0, V1N is the negative potential of gradation number 1, V2N is the negative potential of gradation number 2, and V4N is the negative potential of gradation number 4. V8N is the negative potential of gradation number 8, V20N is the negative potential of gradation number 20, V43N is the negative potential of gradation number 43, V55N is the negative potential of gradation number 55, and V59N is The negative potential of gradation number 59, V61N is the negative potential of gradation number 61, V62N is the negative potential of gradation number 62, and V63N is the negative potential of gradation number 63.

  The 12-level reference voltage is buffered by the buffer circuit 112 shown in FIG. 1 and then output to the gradation voltage ladder circuit 113. The gradation voltage ladder circuit 113 is a resistor based on the 12-level reference voltage. In the case of 64 gradation display, the remaining gradation number 3, gradation number 5-7, gradation number 9-19, gradation number 21-42, gradation number 44-54, gradation number 56 are displayed. ˜58 and gradation number 60 are generated. The gradation number-gradation voltage characteristic at this time is as shown in FIG.

  When the contrast emphasis register data is “high” (when contrast emphasis is used) and the contrast emphasis switching register data is “high”, the SWs 505 to 509 are turned on, a current flows through the SWs 505 to 509, and the fixed resistors 516 to 520. There is no current flowing through. Further, since the SWs 500 to 504 are “off”, a current flows through the fixed resistors 510 to 514.

  At this time, when the resistance values of the variable resistors 530 to 535 are set to the minimum values with the fine adjustment register values PRN5 to 9 and the amplitude register value VRN1, the reference high voltage VDH is not divided by resistors, so that the 6-level reference voltage V43N The potential of ˜V63N becomes the same potential as the reference low voltage GND is output. The other six-level reference voltages V0N to V20N do not have the same potential because they are voltage-divided because current flows through the fixed resistors 510 to 514.

  Next, when the contrast enhancement register data is “high” (when contrast enhancement is used) and the contrast enhancement switching register data is “low”, the SWs 505 to 509 are “off”, so that a current flows through the fixed resistors 516 to 520. Further, since the SWs 500 to 504 are “on”, current flows through the SWs 500 to 504, and no current flows through the fixed resistors 510 to 514.

  At this time, when the resistance values of the variable resistors 522 to 527 are set to the minimum values with the fine adjustment register values PRN0 to PRN4 and the amplitude register value VRN0, the reference high voltage VDH is not divided by the resistors, so that the six-level reference voltages V0N to The potential of V20N becomes the same potential as the reference high voltage VDH is output. The other six-level reference voltages V43N to V63N do not have the same potential because current flows through the fixed resistors 516 to 520 and is divided by resistance.

  With the above operation, as in the gradation number-gradation voltage characteristic shown in FIG. 6D, when the contrast enhancement switching register data is “high”, V43 to V63, and the contrast enhancement switching register data is “low”. In some cases, the same voltage can be output in the gradations of V0 to V20.

  As described above, according to the present embodiment, the contrast characteristics on the low gradation side and the high gradation side can be controlled by a low-cost ladder circuit that does not use an LUT.

  In this embodiment, the circuit configurations of the positive ladder circuit 109 and the negative ladder circuit 110 are different from those of the first embodiment. That is, FIGS. 4 to 6 of the first embodiment are shown in FIGS. 7 to 9 in this embodiment, and the contrast enhancement switching register data is omitted. Instead, the SW 700 is connected in parallel to the fixed resistor 415 in FIG. In FIG. 8, SW 800 is connected in parallel to fixed resistor 515. As a result, as shown in FIGS. 9B and 9D, the other configurations that can broadly emphasize the high gradation side and the low gradation side of the contrast characteristics are the same as those in the first embodiment.

  First, the positive ladder circuit 109 will be described with reference to FIG. In FIG. 7, when the contrast enhancement register data is “low” (when contrast enhancement is not used), SW 400 to 409 and SW 700 are turned off, and a current flows through the fixed resistors 410 to 420. The reference high voltage VDH is divided by the resistance value of each variable resistor to generate a 12-level reference voltage V0P / V1P / V2P / V4P / V8P / V20P / V43P / V55P / V59P / V61P / V62P / V63P. The reference voltages V0P to V63P all have different potentials, and none of them has the same potential.

  Based on these 12 levels of reference voltages, the gradation voltage ladder circuit 113 shown in FIG. 1 divides the 12 levels of reference voltage by resistance. Tone voltages of tone numbers 5 to 7, tone numbers 9 to 19, tone numbers 21 to 42, tone numbers 44 to 54, tone numbers 56 to 58, and tone number 60 are generated. The gradation number-gradation voltage characteristics at this time are as shown in FIG.

  Next, when the contrast enhancement register data is “high” (when contrast enhancement is used), SW 400 to 409 and SW 700 are turned “ON”, current flows through SW 400 to 409 and SW 700, and current flows through fixed resistors 410 to 420. Does not flow.

  At this time, in order to enhance the contrast on the low gradation side (the same potential on the high gradation side), the variable resistors 422 are adjusted with the fine adjustment register values PRP0 to PRP4, the inclination register values SRP0 to 1 and the amplitude register value VRP0. When the resistance value of 429 is set to the minimum value, the reference high voltage VDH is not resistance-divided, so the potentials of the seven-level reference voltages V20P to V63P are the same potential as the reference high voltage VDH is output. The other five-level reference voltages V0P to V8P do not flow through the fixed resistors 416 to 420, but the variable resistors 430 to 435 are adjusted by setting the fine adjustment register values PRP5 to 9 and the amplitude register value VRP1. Therefore, since the reference high voltage VDH is divided by resistance, it does not become the same potential.

  Further, when the contrast enhancement register data is “high” (when contrast enhancement is used), fine adjustment register values PRP5 to 9 are used to enhance the contrast on the high gradation side (the same potential on the low gradation side). When the resistance values of the variable resistors 428 to 435 are set to the minimum values with the slope register values SRP0 to SRP1 and the amplitude register value VRP1, the reference high voltage VDH is not resistance-divided, so the potentials of the seven-level reference voltages V0P to V43P The reference low voltage GND is output to the same potential. The other five-level reference voltages V55P to V63P do not cause a current to flow through the fixed resistors 410 to 414, but adjust the variable resistors 422 to 426 by setting the fine adjustment register values PRP0 to 3 and the amplitude register value VRP0. Therefore, since the reference high voltage VDH is divided by resistance, it does not become the same potential.

  By such an operation, as shown in FIG. 9B, the high-tone side contrast is enhanced by making the high-tone side potential the same, or the high-tone side contrast is made by making the low-tone side potential the same. Can be emphasized.

  Next, the negative ladder circuit 110 will be described with reference to FIG. In FIG. 8, when the contrast enhancement register data is “low” (when contrast enhancement is not used), SW 500 to 509 and SW 800 are turned off, and a current flows through the fixed resistors 510 to 520. The reference high voltage VDH is divided by the resistance value of each variable resistor to generate a 12-level reference voltage V0N / V1N / V2N / V4N / V8N / V20N / V43N / V55N / V59N / V61N / V62N / V63N. The potentials of the reference voltages V0N to V63N are all different, and none of them has the same potential.

  Based on these 12 levels of reference voltages, the gradation voltage ladder circuit 113 shown in FIG. 1 divides the 12 levels of reference voltage by resistance. Tone voltages of tone numbers 5 to 7, tone numbers 9 to 19, tone numbers 21 to 42, tone numbers 44 to 54, tone numbers 56 to 58, and tone number 60 are generated. The gradation number-gradation voltage characteristics at this time are as shown in FIG.

  Next, when the contrast enhancement register data is “high” (when contrast enhancement is used), SW 500 to 509 and SW 800 are turned “ON”, current flows through SW 500 to 509 and SW 800, and current flows through fixed resistors 510 to 520. Does not flow.

  At this time, in order to enhance the contrast on the low gradation side (the same potential on the high gradation side), the fine adjustment register values PRN5 to 9, the inclination register values SRN0 to 1 and the amplitude register value VRN1 and the variable resistors 528 to When the resistance value of 535 is set to the minimum value, the reference high voltage VDH is not divided by resistance. Therefore, the potentials of the seven-level reference voltages V20N to V63N are the same potential as the reference low voltage GND is output. The other five-level reference voltages V0N to V8N do not cause a current to flow through the fixed resistors 510 to 514. However, the variable resistors 422 to 527 are adjusted by setting the fine adjustment register values PRP0 to PRP4 and the amplitude register value VRP0. Therefore, since the reference high voltage VDH is divided by resistance, it does not become the same potential.

  Further, when the contrast enhancement register data is “high” (when contrast enhancement is used), fine adjustment register values PRN0 to PRN0 to enhance the contrast on the high gradation side (the same potential on the low gradation side), When the resistance values of the variable resistors 522 to 527 are set to the minimum value with the inclination register values SRP0 to SRP1 and the amplitude register value VRN0, the reference high voltage VDH is not divided by the resistors, so the potentials of the seven-level reference voltages V0N to V43N The reference high voltage VDH is output to have the same potential. The other five-level reference voltages V55N to V63N do not allow current to flow through the fixed resistors 516 to 520, but adjust the variable resistors 513 to 535 by setting the fine adjustment register values PRN6 to 9 and the amplitude register value VRN1. Therefore, since the reference high voltage VDH is divided by resistance, it does not become the same potential.

  By such an operation, as shown in FIG. 9D, the high gradation side potential is made the same and the low gradation side contrast is enhanced, or the low gradation side potential is made the same and the high gradation side contrast is made the same. Can be emphasized.

  FIG. 10 is a configuration diagram of the liquid crystal display device of this embodiment in which the signal line driving circuit 101 shown in FIG. The γ register switching circuit 1000 includes a maximum / minimum gradation detection circuit 1100, a display selection circuit 1101, and a contrast enhancement γ register generation circuit 1102, as shown in FIG. Further, one frame period is divided into n field periods (n is an integer of 2 or more), at least one of the n field periods is set to have the same potential on the high gradation side, and at least another of the n fields One field period may have the same potential on the low gradation side. Thereby, it is possible to reduce motion blur while suppressing a decrease in luminance.

  In FIG. 11A, the maximum / minimum gradation detection circuit 1100 detects the maximum gradation and the minimum gradation within one frame period, and the display selection circuit 1101 contrasts according to the flow shown in FIG. 11B. The emphasized register data is generated and output, and the contrast-enhanced γ register generation circuit 1102 generates the contrast-enhanced γ-register data (2) according to the flow shown in FIG. 12 and FIG. By outputting to the registers 106/107, contrast enhancement according to display data can be controlled for each frame as shown in FIG. The contrast enhancement γ register data (2) is generated with the maximum gradation and the minimum gradation within one frame period, but may be generated with histogram data within one frame period.

  Hereinafter, the operation of the γ register switching circuit 1000 will be described with reference to FIGS. 10 to 13. The operation of the other configuration is the same as that shown in FIG.

  The maximum / minimum gradation detection circuit 1100 in the γ register switching circuit 1000 determines the maximum gradation within one frame period of the display data from the display RAM 115 based on the vertical synchronization signal FLM and the horizontal synchronization signal CL1 from the timing controller 104. The minimum gradation is detected, and the maximum gradation and the minimum gradation are output to the display selection circuit 1101 and the contrast enhancement γ register generation circuit 1102.

  The display selection circuit 1101 receives the detected maximum gradation and minimum gradation, and when the minimum gradation is 0 and the maximum gradation is 63 as shown in FIG. The data is set to “low”. In other cases, the contrast enhancement register data is output as “high”. That is, when the display data includes the minimum gradation 0 and the maximum gradation 63, contrast enhancement is not performed in order to faithfully reproduce the display data from the minimum gradation 0 to the maximum gradation 63. In other cases, contrast enhancement is performed in accordance with the minimum gradation and the maximum gradation in the display data.

  When the contrast enhancement register data input from the display selection circuit 1101 is “low”, the contrast enhancement γ register generation circuit 1102 uses the contrast enhancement γ register data (1) from the control register 103 as the contrast enhancement γ register data. As (2), the data is output as it is. When the contrast enhancement register data is “high”, the contrast enhancement γ register data (1) is corrected based on the minimum gradation and the maximum gradation input from the maximum / minimum gradation detection circuit 1100, and the contrast Output as emphasized γ register data (2).

  An operation of generating the contrast enhancement γ register data (2) by the contrast enhancement γ register generation circuit 1102 will be described with reference to FIGS.

  First, in step 1200 shown in FIG. 12, the register values of the contrast enhancement γ register data (1) input to the contrast enhancement γ register generation circuit 1102 are set to positive fine adjustment registers PRP0 to PRP9 and negative fine adjustment registers PRN0 to PRN0. It is set to PRN9 and output from the contrast enhancement γ register generation circuit 1102 as contrast enhancement γ register data (2). Next, in step 1201, it is determined whether or not the contrast enhancement register data input from the display selection circuit 1101 to the contrast enhancement γ register generation circuit 1102 is “high”. The contrast enhancement γ register data (1) is not corrected and is output as it is as the contrast enhancement γ register data (2) from the contrast enhancement γ register generation circuit 1102, and the processing is terminated without performing the contrast enhancement.

  However, when the contrast enhancement register data is “high” in step 1201, in order to perform contrast enhancement, in steps 1203 to 1207, the maximum gradation in the display data is 43 or less, or 55 It is sequentially determined whether it is below, 59 or below, 61 or below, or 62 or below.

  That is, in step 1203, if the maximum gradation is 43 or less, the values of registers PRP0 to PRP4 and PRN5 to PRN9 are set to 0 in step 1208, and the minimum gradation process 1 shown in FIG. .

  In the next step 1204, when the maximum gradation is 55 or less, that is, when the maximum gradation in the display data exceeds 43 and is 55 or less, the values of the registers PRP0 to PRP3 and PRN6 to PRN9 are set to 0 in step 1209. In step 1213, the minimum gradation process 1 shown in FIG.

  In the next step 1205, when the maximum gradation is 59 or less, that is, when the maximum gradation in the display data exceeds 55 and is 59 or less, the values of the registers PRP0 to PRP2 and PRN7 to PRN9 are set to 0 in step 1210. In step 1213, the minimum gradation process 1 shown in FIG.

  In the next step 1206, when the maximum gradation is 61 or less, that is, when the maximum gradation in the display data exceeds 59 and is 61 or less, the values of the registers PRP0 to PRP1 and PRN8 to PRN9 are set to 0 in step 1211. In step 1213, the minimum gradation process 1 shown in FIG.

  In the next step 1207, if the maximum gradation is 62 or less, that is, if the maximum gradation in the display data is 62, the values of the registers PRP0 and PRN9 are set to 0 in step 1212, and in FIG. The minimum gradation process 1 shown is performed. If the maximum gradation is 63 in step 1207, the minimum gradation process 1 shown in FIG. 13 is performed in step 1213 without correcting the values of the registers PRP0 to PRP4 and PRN5 to PRN9.

  Next, the minimum gradation processing 1 in step 1213 will be described with reference to FIG. In steps 1303 to 1307, it is sequentially determined whether the minimum gradation in the display data is 20 or more, 8 or more, 4 or more, 2 or more, or 1 or more.

  That is, in step 1303, when the minimum gradation is 20 or more, the values of the registers PRP5 to PRP9 and PRN0 to PRN4 are set to 0 in step 1308, and the process is terminated.

  In the next step 1304, if the minimum gradation is 8 or more, that is, if the minimum gradation in the display data is 8 or more and less than 20, the values of the registers PRP6 to PRP9 and PRN0 to PRN3 are set to 0 in step 1309. The process is terminated.

  In the next step 1305, if the minimum gradation is 4 or more, that is, if the minimum gradation in the display data is 4 or more and less than 8, the values of the registers PRP7 to PRP9 and PRN0 to PRN2 are set to 0 in step 1310. The process is terminated.

  In the next step 1306, when the minimum gradation is 2 or more, that is, when the minimum gradation in the display data is 2 or more and less than 4, the values of the registers PRP8 to PRP9 and PRN0 to PRN1 are set to 0 in step 1311. The process is terminated.

  In the next step 1307, when the minimum gradation is 1, in step 1312, the values of the registers PRP9 and PRN0 are set to 0, and the process is terminated. In step 1307, if the minimum gradation is 0, the processing ends without correcting the values of the registers PRP5 to PRP9 and PRN0 to PRN4.

  As described above, the contrast enhancement register data and the contrast enhancement γ register data (2) generated by the γ register switching circuit 1000 shown in FIGS. 10 and 11A are used as the positive register 106 and the negative register 107 shown in FIG. To enter. The difference between the configuration of FIG. 14 and the configuration of FIG. 3A is that the γ setting register data in FIG. 3 is changed to normal γ register data and contrast enhancement γ register data (2) in FIG. The configuration of is the same as that of FIG.

  FIG. 15 is a characteristic diagram during normal display and contrast enhancement of the positive and negative gradation voltages. FIGS. 15A and 15C show the positive and negative gradation voltages during normal display. FIG. 15B and FIG. 15D are examples of characteristic diagrams of the positive gradation voltage and the negative gradation voltage during contrast enhancement according to the present embodiment. FIGS. 15B and 15D show a case where the maximum gradation in the display data is 43 or less and the minimum gradation is 20 or more.

  FIG. 16 is a configuration diagram of the liquid crystal display device of this embodiment in which the grayscale voltage generation circuit 108 shown in FIG. 10 is a grayscale voltage generation circuit 1600 having a different configuration. Other configurations are the same as those shown in FIG.

  In the gradation voltage generation circuit 1600 shown in FIG. 16, as reference ladder circuits 1601 to 1604, 1601 is a ladder circuit for positive electrode (1), 1602 is a ladder circuit for negative electrode (1), 1603 is a ladder circuit for positive electrode (2), Reference numeral 1604 denotes a negative (2) ladder circuit, 1605 denotes a selection circuit, 1606 denotes a buffer circuit, and 1607 denotes a gradation voltage ladder circuit.

  In normal display without contrast enhancement, the γ adjustment register 105 stores the register value held in the positive polarity register 106 in the positive polarity (1) ladder circuit 1601 and the register value held in the negative polarity register 107. Is output to the ladder circuit 1602 for the negative electrode (1).

  When contrast enhancement is performed, the γ adjustment register 105 sets the register value held in the positive register 106 to the positive (2) ladder circuit 1603 and the register value held in the negative register 107 to the negative ( 2) Output to ladder circuit 1604 for use.

  These ladder circuits generate a reference voltage corresponding to the input register value and output the reference voltage to the selection circuit 1605. The selection circuit 1605 selects one type of reference voltage from the two types of reference voltages input from these ladder circuits in accordance with the AC signal M input from the timing controller 104 and outputs the selected reference voltage to the buffer circuit 1606. . The buffer circuit 1606 buffers the input reference voltage by a voltage follower circuit and outputs the buffered voltage to the gradation voltage ladder circuit 1607. The gradation voltage ladder circuit 1607 divides the input reference voltage by resistance, generates a gradation voltage of 64 levels, and outputs it to the output control circuit 117.

  As described above, when contrast enhancement is performed, by providing the dedicated positive (2) ladder circuit 1603 and the negative (2) ladder circuit 1604, when switching between normal display and contrast emphasized display frequently, Accordingly, since it is not necessary to generate a reference voltage in accordance with the above, it is possible to improve the driving capability of the gradation voltage (reduction of the gradation voltage fluctuation time) as compared with the previous embodiments.

  The circuit configuration of the positive electrode (1) ladder circuit 1601, the negative electrode (1) ladder circuit 1602, the positive electrode (2) ladder circuit 1603, and the negative electrode (2) ladder circuit 1604 in this embodiment is shown in FIG. The circuit configuration of the positive ladder circuit 109 shown in FIG. 5, the negative ladder circuit 110 shown in FIG. 5, or the positive ladder circuit 109 shown in FIG. 7 and the negative ladder circuit 110 shown in FIG.

Configuration diagram of liquid crystal display device according to the present invention Configuration diagram and timing chart of the timing controller shown in FIG. Configuration diagram of positive electrode register and its normal γ register shown in FIG. 1 ladder circuit diagram for positive electrode shown in FIG. The ladder circuit diagram for the negative electrode shown in FIG. Gradation number-gradation voltage characteristic diagram of Example 1 Example 2 Ladder circuit diagram for positive electrode Example 2 Negative Ladder Circuit Diagram Gradation number-gradation voltage characteristic diagram of Example 2 Configuration diagram of liquid crystal display device of embodiment 3 FIG. 10 is a γ register switching circuit diagram and a flowchart of its display selection circuit. FIG. 11A is a flowchart of the contrast enhancement γ register generation circuit. FIG. 11A is a flowchart of the contrast enhancement γ register generation circuit. Configuration diagram of positive and negative registers in FIG. Gradation number-gradation voltage characteristic diagram of Example 3 Configuration diagram of liquid crystal display device of Example 4

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... CPU, 101 ... Signal line drive circuit, 102 ... System interface, 103 ... Control register, 104 ... Timing controller, 105 ... Gamma adjustment register, 106 ... Positive register, 107 ... Negative register, 108 ... Gradation voltage Generation circuit 109... Positive ladder circuit 110 110 Negative ladder circuit 111 Selection circuit 112 Buffer circuit 113 Gradation voltage ladder circuit 114 Memory control circuit 115 Display RAM 116 Latch Circuit 117, output control circuit 118, scanning line drive circuit, 119 ... liquid crystal panel, 120 ... scanning line, 121 ... signal line, 122 ... TFT, 123 ... display element, 200 ... register, 201 ... internal clock generation circuit, 202 ... Clock counter, 203 ... Horizontal synchronization signal generation circuit, 204 ... AC signal Generation circuit 205... Line counter 206 206 vertical synchronization signal generation circuit 300 normal γ register 301 contrast enhancement γ register 302 amplitude register 303 305 tilt register 304 306 fine adjustment register 307 308 ... selection circuit, 400-409 ... SW, 410-421 ... fixed resistor, 422-435 ... variable resistor, 500-509 ... SW, 510-521 ... fixed resistor, 522-535 ... variable resistor, 700, 800 ... SW, 1000... Γ register switching circuit, 1100... Maximum / minimum gradation detection circuit, 1101... Display selection circuit, 1102 .. contrast enhancement .gamma. Register generation circuit, 1600 ... gradation voltage generation circuit, 1601. Circuit, 1602 ... Ladder circuit for negative electrode (1), 1603 ... Ladder circuit for positive electrode (2) 1604 ... ladder circuit negative electrode (2), 1605 ... selection circuit, 1606 ... buffer circuit, 1607 ... gradation voltage ladder circuit

Claims (8)

A display panel having a plurality of pixels and a drive circuit for driving the display panel;
The driving circuit includes a register that stores a setting value for generating and outputting a gradation voltage corresponding to input display data, a reference ladder circuit that generates a reference gradation voltage according to the setting value, and
A buffer circuit for buffering and outputting the reference gradation voltage, a gradation voltage ladder circuit for generating a gradation voltage based on the reference gradation voltage, and corresponding to input display data from the gradation voltage An output control circuit that selects and outputs the gradation voltage to be output,
The reference ladder circuit includes a variable resistor, a fixed resistor connected in series to the variable resistor, and a switch connected in parallel to the fixed resistor, and controls the variable resistor and the switch based on the set value. In a display device that controls contrast characteristics,
The reference ladder circuit is
A first variable resistor having one end connected to a reference high voltage source, a first fixed resistor connected in series to the first variable resistor, and a first switch connected in parallel to the first fixed resistor When,
A second variable resistor connected in series with the first fixed resistor; a second fixed resistor connected in series with the second variable resistor; and a second variable resistor connected in parallel with the second fixed resistor. A switch,
A third variable resistor connected in series with the second fixed resistor, a third fixed resistor connected in series with the third variable resistor, and a third variable resistor connected in parallel with the third fixed resistor A switch,
A fourth variable resistor connected in series with the third fixed resistor; a fourth fixed resistor connected in series with the fourth variable resistor; and a fourth variable resistor connected in parallel with the fourth fixed resistor. A switch,
A fifth variable resistor connected in series with the fourth fixed resistor; a fifth fixed resistor connected in series to the fifth variable resistor; and a fifth variable resistor connected in parallel with the fifth fixed resistor. A switch,
Sixth variable resistor which is the fifth fixed resistor in series connection, the sixth seventh variable resistor connected in series to a variable resistor, and the seventh variable resistor connected in series with the sixth Fixed resistance,
An eighth variable resistor connected in series to the sixth fixed resistor;
A ninth variable resistor connected in series to the eighth variable resistor; a seventh fixed resistor connected in series to the ninth variable resistor; and a sixth variable resistor connected in parallel to the seventh fixed resistor. A switch,
A tenth variable resistor connected in series to the seventh fixed resistor; an eighth fixed resistor connected in series to the tenth variable resistor; and a seventh variable resistor connected in parallel to the eighth fixed resistor. A switch,
An eleventh variable resistor connected in series to the eighth fixed resistor, a ninth fixed resistor connected in series to the eleventh variable resistor, and an eighth variable resistor connected in parallel to the ninth fixed resistor A switch,
A twelfth variable resistor connected in series with the ninth fixed resistor; a tenth fixed resistor connected in series with the twelfth variable resistor; and a ninth variable resistor connected in parallel with the tenth fixed resistor. A switch,
A thirteenth variable resistor connected in series with the tenth fixed resistor, an eleventh fixed resistor connected in series with the thirteenth variable resistor, and a tenth resistor connected in parallel with the eleventh fixed resistor A switch,
A fourteenth variable resistor connected in series with the eleventh fixed resistor, a twelfth fixed resistor connected in series with the fourteenth variable resistor, and connected at one end to a reference low voltage; and
A first reference voltage is generated from a connection point of the first variable resistor and the first fixed resistor;
A second reference voltage is generated from a connection point between the second variable resistor and the second fixed resistor;
A third reference voltage is generated from a connection point between the third variable resistor and the third fixed resistor;
A fourth reference voltage is generated from a connection point between the fourth variable resistor and the fourth fixed resistor;
A fifth reference voltage is generated from a connection point of the fifth variable resistor and the fifth fixed resistor;
A sixth reference voltage is generated from a connection point between the sixth variable resistor and the seventh variable resistor;
A seventh reference voltage is generated from a connection point of the eighth variable resistor and the ninth variable resistor;
The eighth reference voltage is generated from the connection point of the seventh fixed resistor and the tenth variable resistor,
A ninth reference voltage is generated from a connection point of the eighth fixed resistor and the eleventh variable resistor;
A tenth reference voltage is generated from a connection point of the ninth fixed resistor and the twelfth variable resistor;
The eleventh reference voltage is generated from the connection point of the tenth fixed resistor and the thirteenth variable resistor,
A twelfth reference voltage is generated from a connection point between the eleventh fixed resistor and the fourteenth variable resistor ,
A first switching signal input to the first to fifth switches, displays a second switching signal inverted with respect to the first switching signal to the sixth to tenth switch and said Rukoto entered apparatus. A display panel having a plurality of pixels and a drive circuit for driving the display panel;
The driving circuit includes a register that stores a setting value for generating and outputting a gradation voltage corresponding to input display data, a reference ladder circuit that generates a reference gradation voltage according to the setting value, and the reference A buffer circuit for buffering and outputting a gradation voltage; a gradation voltage ladder circuit for generating a gradation voltage based on the reference gradation voltage; and a level corresponding to input display data from the gradation voltage. An output control circuit that selects and outputs a regulated voltage;
The reference ladder circuit includes a variable resistor, a fixed resistor connected in series to the variable resistor, and a switch connected in parallel to the fixed resistor, and controls the variable resistor and the switch based on the set value. In a display device that controls contrast characteristics,
The reference ladder circuit is
A first variable resistor having one end connected to a reference high voltage source, a first fixed resistor connected in series to the first variable resistor, and a first switch connected in parallel to the first fixed resistor When,
A second variable resistor connected in series with the first fixed resistor; a second fixed resistor connected in series with the second variable resistor; and a second variable resistor connected in parallel with the second fixed resistor. A switch,
A third variable resistor connected in series with the second fixed resistor, a third fixed resistor connected in series with the third variable resistor, and a third variable resistor connected in parallel with the third fixed resistor A switch,
A fourth variable resistor connected in series with the third fixed resistor; a fourth fixed resistor connected in series with the fourth variable resistor; and a fourth variable resistor connected in parallel with the fourth fixed resistor. A switch,
A fifth variable resistor connected in series with the fourth fixed resistor; a fifth fixed resistor connected in series to the fifth variable resistor; and a fifth variable resistor connected in parallel with the fifth fixed resistor. A switch,
A sixth variable resistor connected in series with the fifth fixed resistor;
A seventh variable resistor connected in series with the sixth variable resistor; a sixth fixed resistor connected in series with the seventh variable resistor; and a sixth variable resistor connected in parallel with the sixth fixed resistor. A switch,
An eighth variable resistor connected in series with the sixth fixed resistor;
A ninth variable resistor connected in series with the eighth variable resistor; a seventh fixed resistor connected in series with the ninth variable resistor; and a seventh variable resistor connected in parallel with the seventh fixed resistor. A switch,
A tenth variable resistor connected in series with the seventh fixed resistor; an eighth fixed resistor connected in series with the tenth variable resistor; and an eighth variable resistor connected in parallel with the eighth fixed resistor. A switch,
An eleventh variable resistor connected in series with the eighth fixed resistor, a ninth fixed resistor connected in series with the eleventh variable resistor, and a ninth variable resistor connected in parallel with the ninth fixed resistor A switch,
A twelfth variable resistor connected in series with the ninth fixed resistor; a tenth fixed resistor connected in series with the twelfth variable resistor; and a tenth resistor connected in parallel with the tenth fixed resistor. A switch,
A thirteenth variable resistor connected in series with the tenth fixed resistor, an eleventh fixed resistor connected in series with the thirteenth variable resistor, and an eleventh connected in parallel with the eleventh fixed resistor. A switch,
A fourteenth variable resistor connected in series with the eleventh fixed resistor, a twelfth fixed resistor connected in series with the fourteenth variable resistor, and connected at one end to a reference low voltage; and
A first reference voltage is generated from a connection point of the first variable resistor and the first fixed resistor;
A second reference voltage is generated from a connection point between the second variable resistor and the second fixed resistor;
A third reference voltage is generated from a connection point between the third variable resistor and the third fixed resistor;
A fourth reference voltage is generated from a connection point between the fourth variable resistor and the fourth fixed resistor;
A fifth reference voltage is generated from a connection point of the fifth variable resistor and the fifth fixed resistor;
A sixth reference voltage is generated from a connection point between the sixth variable resistor and the seventh variable resistor;
A seventh reference voltage is generated from a connection point of the eighth variable resistor and the ninth variable resistor;
The eighth reference voltage is generated from the connection point of the seventh fixed resistor and the tenth variable resistor,
A ninth reference voltage is generated from a connection point of the eighth fixed resistor and the eleventh variable resistor;
A tenth reference voltage is generated from a connection point of the ninth fixed resistor and the twelfth variable resistor;
The eleventh reference voltage is generated from the connection point of the tenth fixed resistor and the thirteenth variable resistor.
And
The twelfth reference voltage is generated from a connection point of the eleventh fixed resistor and the fourteenth variable resistor, and the same switching signal is input to the first to eleventh switches . The display device according to claim 1,
The display device according to claim 1, wherein the reference ladder circuit includes a positive ladder circuit that generates a positive gradation voltage and a negative ladder circuit that generates a negative gradation voltage . The display device according to claim 1 ,
The variable resistance of the reference ladder circuit is controlled according to the maximum gradation value and the minimum gradation value of the input display data . The display device according to claim 1 ,
The reference ladder circuit includes a positive polarity and a negative polarity ladder circuit for normal display, and a positive polarity and a negative polarity ladder circuit for contrast enhancement . The display device according to claim 2 ,
The display device according to claim 1, wherein the reference ladder circuit includes a positive ladder circuit that generates a positive gradation voltage and a negative ladder circuit that generates a negative gradation voltage . The display device according to claim 2 ,
The variable resistance of the reference ladder circuit is controlled according to the maximum gradation value and the minimum gradation value of the input display data . The display device according to claim 2 ,
The reference ladder circuit includes a positive polarity and a negative polarity ladder circuit for normal display, and a positive polarity and a negative polarity ladder circuit for contrast enhancement .

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