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JP5113509B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP5113509B2
JP5113509B2 JP2007332195A JP2007332195A JP5113509B2 JP 5113509 B2 JP5113509 B2 JP 5113509B2 JP 2007332195 A JP2007332195 A JP 2007332195A JP 2007332195 A JP2007332195 A JP 2007332195A JP 5113509 B2 JP5113509 B2 JP 5113509B2
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bonding
semiconductor device
bonding pad
constituting
pad
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JP2009158561A (en
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隆之 松田
泰之 石井
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2924/151—Die mounting substrate
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

本発明は、半導体装置に関し、特に、ボンディングワイヤが接続される複数のボンディングパッドを備える半導体装置に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including a plurality of bonding pads to which bonding wires are connected.

半導体装置の主面に設けられたボンディングパッドは、ボンディングワイヤを介してリードフレームのリード、あるいはラミネート基板またはセラミック基板等の実装基板の主面に設けられた電極と電気的に接続される。   Bonding pads provided on the main surface of the semiconductor device are electrically connected to leads of a lead frame or electrodes provided on a main surface of a mounting substrate such as a laminate substrate or a ceramic substrate via bonding wires.

例えば特開平７−１１１２８２号公報（特許文献１）には、ボンディングパッドとは別個に、該ボンディングパッドと電気的に接続され、プローブ検査用のプローブ針が接触するプローブパッドが形成された半導体チップが開示されている。   For example, Japanese Patent Laid-Open No. 7-111282 (Patent Document 1) discloses a semiconductor chip in which a probe pad that is electrically connected to a bonding pad and is in contact with a probe needle for probe inspection is formed separately from the bonding pad. Is disclosed.

また、特開平７−３７９２９号公報（特許文献２）には、半導体チップに外部接続用ワイヤをボンディングするためのボンディング用パッドと、検査時にテスト用プローブを接触させるテスト用パッドとを独立して設け、これらのパッドをスルーホールを介して同一の下部配線層に接続した半導体集積回路装置が開示されている。   Japanese Patent Laid-Open No. 7-37929 (Patent Document 2) discloses that a bonding pad for bonding an external connection wire to a semiconductor chip and a test pad for contacting a test probe during inspection are independently provided. A semiconductor integrated circuit device is disclosed in which these pads are connected to the same lower wiring layer through through holes.

また、特開２００５−１３６２９９号公報（特許文献３）には、方形状で形成された主面に第１の辺と、第１の辺と対向する第２の辺とを備えており、第１の辺に沿って主面に配置される複数の主電極パッドからなる主電極パッド群と、第１の辺および主電極パッド群の間に配置される複数の第１電極パッドからなる第１電極パッド群と、第２の辺に沿って主面に配置される複数の第２電極パッドからなる第２電極パッド群と、主電極パッドおよび第１電極パッドを接続する第１パッド間配線と、主電極パッドおよび第２電極パッドを接続する第２パッド間配線とを備えた半導体チップが開示されている。
特開平７−１１１２８２号公報 特開平７−３７９２９号公報 特開２００５−１３６２９９号公報 Japanese Patent Laying-Open No. 2005-136299 (Patent Document 3) includes a main surface formed in a square shape having a first side and a second side facing the first side. A main electrode pad group including a plurality of main electrode pads disposed on the main surface along one side, and a first electrode including a plurality of first electrode pads disposed between the first side and the main electrode pad group. An electrode pad group, a second electrode pad group comprising a plurality of second electrode pads arranged on the main surface along the second side, and a first inter-pad wiring connecting the main electrode pad and the first electrode pad A semiconductor chip including a second inter-pad wiring connecting the main electrode pad and the second electrode pad is disclosed.
Japanese Patent Laid-Open No. 7-111282 JP-A-7-37929 JP 2005-136299 A

本発明者らは、メモリ回路と論理回路とを同一の半導体基板上に設けるロジック（Logic：論理回路）混載形メモリの開発、生産を行っている。しかしながら、ロジック混載形メモリでは、１つの製品において互いに異なる複数の電圧（例えば１．７Ｖおよび３．３Ｖ）が出力され、さらに展開する製品毎にその出力される電圧を取り出すボンディングパッドの位置が変わる。そのため、リードフレームのリードまたは実装基板の主面に設けられた電極の配置に合わせて、展開する製品毎に製品部に形成された種々の回路からボンディングパッドに繋がるパッド用配線のレイアウトを修正している。しかし、その修正には多くの時間を要しており、展開する製品の製造遅延の原因の一つとなっている。   The present inventors have developed and produced a logic (logic: logic circuit) embedded memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate. However, in the logic-embedded memory, a plurality of different voltages (for example, 1.7 V and 3.3 V) are output in one product, and the position of the bonding pad for extracting the output voltage changes for each product to be developed. . Therefore, in accordance with the arrangement of the electrodes provided on the lead frame lead or the main surface of the mounting substrate, the layout of the pad wiring connected to the bonding pad from various circuits formed in the product section for each product to be developed is corrected. ing. However, the correction takes a lot of time, which is one of the causes of manufacturing delay of products to be deployed.

本発明の目的は、ワイヤボンディングを採用する半導体装置において、製品展開に要する時間を短縮することのできる技術を提供することにある。   An object of the present invention is to provide a technique capable of reducing the time required for product development in a semiconductor device employing wire bonding.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

本発明は、第１の方向に沿って配置された複数のボンディングパッドからなるボンディングパッドセットが、第１の方向と直交する第２の方向に沿って３セット以上設けられた半導体装置である。一のボンディングパッドセットを構成する各々のボンディングパッドが他のボンディングパッドセットを構成する各々のボンディングパッドと第２の方向と同一線上に並んで設けられており、一のボンディングパッドセットは、他のボンディングパッドセットを構成し第２の方向と同一線上に並んで配置されていないボンディングパッドとパッド用配線を介して電気的に接続されたボンディングパッドを含む。また、一のボンディングパッドセットを構成する複数のボンディングパッドの全部または一部にボンディングワイヤを接続する。   The present invention is a semiconductor device in which three or more bonding pad sets each including a plurality of bonding pads arranged along a first direction are provided along a second direction orthogonal to the first direction. Each bonding pad constituting one bonding pad set is provided side by side with the other bonding pad constituting the other bonding pad set in the same line as the second direction. It includes a bonding pad that constitutes a bonding pad set and is electrically connected via a pad wiring to a bonding pad that is not arranged along the same line as the second direction. Further, bonding wires are connected to all or a part of the plurality of bonding pads constituting one bonding pad set.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。   Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

ワイヤボンディングを採用する半導体装置において、展開する製品毎にボンディングパッドに繋がるパッド用配線のレイアウトを修正することなくワイヤボンディングが可能となるので、製品展開に要する時間を短縮することができる。   In a semiconductor device that employs wire bonding, wire bonding can be performed without correcting the layout of the pad wiring connected to the bonding pad for each product to be developed, so that the time required for product development can be reduced.

以下の実施の形態において、便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。   In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。   Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

また、以下の実施の形態を説明するための全図において、同一機能を有するものは原則として同一の符号を付し、その繰り返しの説明は省略する。以下、本発明の実施の形態を図面に基づいて詳細に説明する。   In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

（実施の形態１）
本発明の実施の形態１による半導体装置に設けられたボンディングパッドの配置の一例を図１〜図３に示す。図１はボンディングパッドの配置の一例を説明する半導体装置全体の平面図、図２は図１の一部を拡大した要部平面図、図３（ａ）、（ｂ）、（ｃ）および（ｄ）はそれぞれ図２のＡ−Ａ′線、Ｂ−Ｂ′線、Ｃ−Ｃ′線およびＤ−Ｄ′線における要部断面図である。 (Embodiment 1)
One example of the arrangement of bonding pads provided in the semiconductor device according to the first embodiment of the present invention is shown in FIGS. FIG. 1 is a plan view of the entire semiconductor device for explaining an example of the arrangement of bonding pads, FIG. 2 is a plan view of a principal part in which a part of FIG. 1 is enlarged, and FIGS. 3 (a), (b), (c) and ( d) is a cross-sectional view of an essential part taken along lines AA ′, BB ′, CC ′ and DD ′ in FIG. 2, respectively.

図１に示すように、半導体装置１は、例えばシリコンよりなる半導体基板上に形成されており、論理回路、メモリ回路または入出力回路等の種々の回路が形成された方形状の製品部２と、それら回路が形成されていない周辺部３とにより構成されている。本実施の形態１では、周辺部３は製品部２の各辺（第１の辺Ｓ１、第２の辺Ｓ２、第３の辺Ｓ３および第４の辺Ｓ４）の周囲に設けられている。第１の方向に沿って延びる製品部２の第１辺Ｓ１に沿う周辺部３および第１辺Ｓ１に対向する第３の辺Ｓ３に沿う周辺部３には、第１の方向に沿って一列に配置された複数のボンディングパッド４からなる第１の列Ｌ１、および第１の方向に沿って一列に配置された複数のボンディングパッド５からなる第２の列Ｌ２が２列となって配置されている。複数のボンディングパッド５からなる第２の列Ｌ２は、複数のボンディングパッド４からなる第１の列Ｌ１よりもさらに製造部２の第１の辺Ｓ１または第３の辺Ｓ３から離れた位置に設けられている。ボンディングパッド４，５はボンディングワイヤを接続するための金属被膜による電極であり、最上層配線により形成されている。   As shown in FIG. 1, a semiconductor device 1 is formed on a semiconductor substrate made of, for example, silicon, and has a rectangular product portion 2 on which various circuits such as a logic circuit, a memory circuit, and an input / output circuit are formed. The peripheral portion 3 is not formed with these circuits. In the first embodiment, the peripheral portion 3 is provided around each side of the product portion 2 (first side S1, second side S2, third side S3, and fourth side S4). The peripheral part 3 along the first side S1 of the product part 2 extending along the first direction and the peripheral part 3 along the third side S3 opposite to the first side S1 are arranged in a row along the first direction. A first row L1 composed of a plurality of bonding pads 4 arranged in a row and a second row L2 composed of a plurality of bonding pads 5 arranged in a row along the first direction are arranged in two rows. ing. The second row L2 including the plurality of bonding pads 5 is provided at a position further away from the first side S1 or the third side S3 of the manufacturing unit 2 than the first row L1 including the plurality of bonding pads 4. It has been. The bonding pads 4 and 5 are electrodes made of a metal film for connecting bonding wires, and are formed by the uppermost layer wiring.

半導体装置１において第１の半導体装置から、製品部２に形成される種々の回路構成等を第１の半導体装置と異にする第２の半導体装置へ製品が展開される場合を例にとると、第１の列Ｌ１を構成する複数のボンディングパッド４からなるパッド群が第１の半導体装置に対応する１つのボンディングパッドセットとして取り扱われ、同様に、第２の列Ｌ２を構成する複数のボンディングパッド５からなるパッド群が第２の半導体装置に対応する１つのボンディングパッドセットとして取り扱われる。すなわち、第１の半導体装置を、例えば実装基板に搭載して第１の半導体装置の主面に設けられたボンディングパッドと実装基板の主面に設けられた電極とをボンディングワイヤで接続する場合は、第１の列Ｌ１からなるボンディングパッドセットが用いられ、第２の半導体装置を、例えば実装基板に搭載して第２の半導体装置の主面に設けられたボンディングパッドと実装基板の主面に設けられた電極とをボンディングワイヤで接続する場合は、第２の列Ｌ２からなるボンディングパッドセットが用いられる。   For example, in the semiconductor device 1, a product is developed from the first semiconductor device to a second semiconductor device having various circuit configurations formed in the product portion 2 different from those of the first semiconductor device. A pad group consisting of a plurality of bonding pads 4 constituting the first row L1 is treated as one bonding pad set corresponding to the first semiconductor device, and similarly, a plurality of bondings constituting the second row L2. A pad group including the pads 5 is handled as one bonding pad set corresponding to the second semiconductor device. That is, when the first semiconductor device is mounted on a mounting substrate, for example, and a bonding pad provided on the main surface of the first semiconductor device and an electrode provided on the main surface of the mounting substrate are connected by a bonding wire. A bonding pad set consisting of the first row L1 is used, and the second semiconductor device is mounted on the mounting substrate, for example, on the main surface of the second semiconductor device and mounted on the main surface of the mounting substrate. When connecting the provided electrode with a bonding wire, a bonding pad set consisting of the second row L2 is used.

このとき、第１の列Ｌ１を構成する複数のボンディングパッド４または第２の配列Ｌ２を構成する複数のボンディングパッド５の全てにボンディングワイヤを接続する必要はなく、第１の半導体装置の動作に必要な第１の列Ｌ１を構成する一部のボンディングパッド４または第２の半導体装置の動作に必要な第２の列Ｌ２を構成する一部のボンディングパッド５にボンディングワイヤを接続してもよい。ボンディングワイヤが接続されないボンディングパッド４，５は、例えば検査用パッドとして用いることができる。すなわち、ボンディングワイヤが接続されないボンディングパッド４，５に、例えば検査用のプローブ針を接触させて第１の半導体装置または第２の半導体装置の電気的特性をテストしてもよい。   At this time, it is not necessary to connect bonding wires to all of the plurality of bonding pads 4 constituting the first row L1 or the plurality of bonding pads 5 constituting the second array L2, so that the operation of the first semiconductor device can be performed. Bonding wires may be connected to some bonding pads 4 constituting the necessary first row L1 or some bonding pads 5 constituting the second row L2 necessary for the operation of the second semiconductor device. . The bonding pads 4 and 5 to which the bonding wires are not connected can be used as, for example, an inspection pad. That is, the electrical characteristics of the first semiconductor device or the second semiconductor device may be tested by bringing a probe needle for inspection into contact with the bonding pads 4 and 5 to which no bonding wire is connected.

このように、予め周辺部３に２つのボンディングパッドセットを設けておくことにより、第１の半導体装置から第２の半導体装置へ製品を展開しても、パッド用配線のレイアウトを修正しなくてもボンディングワイヤを接続するボンディングパッドセットを変更するだけで第２の半導体装置のワイヤボンディングを行うことができる。   Thus, by providing two bonding pad sets in the peripheral portion 3 in advance, even if the product is developed from the first semiconductor device to the second semiconductor device, the layout of the pad wiring is not corrected. Also, the wire bonding of the second semiconductor device can be performed only by changing the bonding pad set for connecting the bonding wires.

図２および図３に、第１の列Ｌ１を構成する複数のボンディングパッドからなるボンディングパッドセットおよび第２の列Ｌ２を構成する複数のボンディングパッドからなるボンディングパッドセットの一部を拡大した要部平面図および要部断面図をそれぞれ示す。図２には、ボンディングパッドよりも下層に形成される周辺部３のパッド用配線の一例も示している。パッド用配線には４層構造の多層配線を用いた例を示しているが、配線の層数および配置等はこれに限定されるものではない。   2 and 3 are enlarged views of a part of a bonding pad set including a plurality of bonding pads constituting the first row L1 and a bonding pad set including a plurality of bonding pads constituting the second row L2. A plan view and a cross-sectional view of relevant parts are shown. FIG. 2 also shows an example of pad wiring in the peripheral portion 3 formed below the bonding pad. Although an example in which a multilayer wiring having a four-layer structure is used as the pad wiring, the number of wiring layers and the arrangement thereof are not limited to this.

第１の方向に沿って一列に配置された第１の列Ｌ１を構成する各々のボンディングパッド４と、第１の方向に沿って一列に配置された第２の列Ｌ２を構成する各々のボンディングパッド５とは、第２の方向の同一線上に２つ並んで配置されている。   Each bonding pad 4 constituting the first row L1 arranged in a line along the first direction and each bonding pad constituting the second row L2 arranged in a line along the first direction Two pads 5 are arranged side by side on the same line in the second direction.

また、第２の列Ｌ２を構成する各々のボンディングパッド５は、第１の列Ｌ１を構成する各々のボンディングパッド４のいずれか１つを介して製品部２の配線に接続することができる。この際、第２の列Ｌ２を構成する各々のボンディングパッド５は、第２の方向の同一線上に並ぶ第１の列Ｌ１を構成するボンディングパッド４と接続する必要はなく、周辺部３に形成された１層目から４層目のパッド用配線Ｍ１〜Ｍ４を用いて第２の方向の同一線上に並ばない第１の列Ｌ１を構成するボンディングパッド４と接続してもよい。   Further, each bonding pad 5 constituting the second row L2 can be connected to the wiring of the product part 2 via any one of the respective bonding pads 4 constituting the first row L1. At this time, the bonding pads 5 constituting the second row L2 do not need to be connected to the bonding pads 4 constituting the first row L1 arranged on the same line in the second direction, and are formed in the peripheral portion 3. The pad wirings M1 to M4 in the first to fourth layers may be used to connect to the bonding pads 4 constituting the first row L1 that are not arranged on the same line in the second direction.

例えば図２に示した第２の列Ｌ２を構成する右端のボンディングパッド５ａは、第２の方向の同一線上に並ぶ第１の列Ｌ１を構成する右端のボンディングパッド４ａと４層目のパッド用配線Ｍ４を用いて接続されている。また、第２の列Ｌ２を構成する左端のボンディングパッド５ｂは、第２の方向の同一線上に並ばない第１の列Ｌ１を構成する左端から３番目のボンディングパッド４ｂと３層目のパッド用配線Ｍ３を用いて接続されている。１層目から４層目のパッド用配線Ｍ１〜Ｍ４は、半導体基板Ｓｕｂの主面に形成された種々の回路を電気的に接続するために製品部２に形成された多層配線と同一工程で形成され、各層の間は絶縁膜ＩＳにより電気的に絶縁されている。   For example, the rightmost bonding pad 5a constituting the second row L2 shown in FIG. 2 is used for the rightmost bonding pad 4a and the fourth layer pad constituting the first row L1 arranged on the same line in the second direction. The wiring M4 is used for connection. Further, the leftmost bonding pad 5b constituting the second row L2 is used for the third bonding pad 4b and the third layer pad from the left end constituting the first row L1 which are not aligned on the same line in the second direction. The wiring M3 is used for connection. The first to fourth pad wirings M1 to M4 are formed in the same process as the multilayer wiring formed in the product section 2 in order to electrically connect various circuits formed on the main surface of the semiconductor substrate Sub. The layers are electrically insulated from each other by an insulating film IS.

また、互いに同じ機能を有する第１の列Ｌ１を構成するボンディングパッド４と第２の列Ｌ２を構成するボンディングパッド５とを第２の方向の同一線上に並べて配置してもよく、互いに異なる機能を有する第１の列Ｌ１を構成するボンディングパッド４と第２の列Ｌ２を構成するボンディングパッド５とを第２の方向の同一線上に並べて配置してもよい。   Further, the bonding pads 4 constituting the first row L1 having the same function and the bonding pads 5 constituting the second row L2 may be arranged side by side on the same line in the second direction. The bonding pads 4 constituting the first row L1 and the bonding pads 5 constituting the second row L2 may be arranged side by side on the same line in the second direction.

本発明の実施の形態１による半導体装置に設けられたボンディングパッドの配置の他の例を図４に示す。図４はボンディングパッドの配置の他の例を説明する半導体装置全体の平面図である。   FIG. 4 shows another example of the arrangement of bonding pads provided in the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a plan view of the entire semiconductor device for explaining another example of the arrangement of bonding pads.

前述した図１に示した半導体装置１では、第１の列Ｌ１を構成する複数のボンディングパッド４からなるボンディングパッドセットおよび第２の列Ｌ２を構成する複数のボンディングパッド５からなるボンディングパッドセットは周辺部３に設けたが、いずれか１つのボンディングパッドセットまたは両ボンディングパッドセットを製品部２に設けることもできる。このように、製品部２にボンディングパッドセットを設けることにより、周辺部３の面積を縮小することができるので、半導体装置１のサイズを小さくすることができる。   In the semiconductor device 1 shown in FIG. 1 described above, the bonding pad set consisting of the plurality of bonding pads 4 constituting the first row L1 and the bonding pad set consisting of the plurality of bonding pads 5 constituting the second row L2 are: Although provided in the peripheral portion 3, any one bonding pad set or both bonding pad sets may be provided in the product portion 2. As described above, by providing the bonding pad set in the product portion 2, the area of the peripheral portion 3 can be reduced, so that the size of the semiconductor device 1 can be reduced.

なお、本実施の形態１では、第１の方向に沿って延びる製品部２の第１辺Ｓ１に沿う周辺部３および第１辺Ｓ１に対向する第３の辺Ｓ３に沿う周辺部３には、それぞれ第１の方向に沿って配置された複数のボンディングパッドからなる第１の列Ｌ１および第２の列Ｌ２の２列を例示したが、３列以上配置してもよく、ボンディングパッドセットを３セット以上設けることもできる。   In the first embodiment, the peripheral part 3 along the first side S1 of the product part 2 extending along the first direction and the peripheral part 3 along the third side S3 facing the first side S1 The two rows of the first row L1 and the second row L2 each including a plurality of bonding pads arranged along the first direction are illustrated, but three or more rows may be arranged. Three or more sets can be provided.

また、本実施の形態１では、第１の方向に沿って延びる製品部２の第１辺Ｓ１に沿う周辺部３および第１辺Ｓ１に対向する第３辺Ｓ３に沿う周辺部３に、それぞれ第１の方向に沿って配置された複数のボンディングパッドからなる第１の列Ｌ１および第２の列Ｌ２を例示したが、第１の方向と直交する第２の方向に沿って延びる製品部２の第２辺Ｓ２
に沿う周辺部３および第２辺Ｓ２に対向する第４辺Ｓ４に沿う周辺部３にも、それぞれ第２の方向に沿って複数のボンディングパッドからなる第１の列Ｌ１および第２の列Ｌ２の２列を配置してもよい。 Further, in the first embodiment, the peripheral part 3 along the first side S1 of the product part 2 extending along the first direction and the peripheral part 3 along the third side S3 facing the first side S1, respectively, The first row L1 and the second row L2 made up of a plurality of bonding pads arranged along the first direction are exemplified, but the product portion 2 extending along the second direction orthogonal to the first direction Second side S2 of
The first row L1 and the second row L2 each including a plurality of bonding pads along the second direction also in the peripheral portion 3 along the fourth side S4 and the peripheral portion 3 along the fourth side S4 facing the second side S2. These two rows may be arranged.

このように、本実施の形態１によれば、半導体装置１にボンディングワイヤを接続することのできる複数のボンディングパッドセットを予め設けておくことにより、回路構成等を異にする製品展開を行っても、半導体装置１のパッド用配線のレイアウトを修正することなくボンディングワイヤを接続するボンディングパッドセットを変更するだけでワイヤボンディングを行うことができる。   As described above, according to the first embodiment, by providing in advance a plurality of bonding pad sets capable of connecting bonding wires to the semiconductor device 1, product development with different circuit configurations and the like is performed. However, it is possible to perform wire bonding only by changing the bonding pad set for connecting the bonding wires without correcting the layout of the pad wiring of the semiconductor device 1.

（実施の形態２）
本発明の実施の形態２による半導体装置に設けられたボンディングパッドの配置の一例を図５に示す。図５はボンディングパッドの配置の一例を説明する半導体装置の一部を拡大した要部平面図である。 (Embodiment 2)
FIG. 5 shows an example of the arrangement of bonding pads provided in the semiconductor device according to the second embodiment of the present invention. FIG. 5 is an enlarged plan view of a principal part of a semiconductor device for explaining an example of the arrangement of bonding pads.

前述の実施の形態１と相違する点は、ボンディングパッドが千鳥状に配置されていることである。すなわち、前述の実施の形態１では、第１の方向に沿って一列に配置された複数のボンディングパッド４からなる第１の列Ｌ１と、第１の方向に沿って一例に配置された複数のボンディングパッド５からなる第２の列Ｌ２とを形成し、第１の列Ｌ１を構成する複数のボンディングパッド４を１つのボンディングパッドセットとし、第２の列Ｌ２を構成する複数のボンディングパッド５を１つのボンディングパッドセットとしている。これに対して、本実施の形態２では、第１の方向に沿って千鳥状に配置された複数のボンディングパッド６からなる第１の千鳥状の列Ｌ３と、第１の方向に沿って千鳥状に配置された複数のボンディングパッド７からなる第２の千鳥状の列Ｌ４とを形成し、第１の千鳥状の列Ｌ３を構成する複数のボンディングパッド６が１つのボンディングパッドセットとなり、第２の千鳥状の列Ｌ４を構成する複数のボンディングパッド７が１つのボンディングセットとなっている。   The difference from the first embodiment is that the bonding pads are arranged in a staggered manner. That is, in the first embodiment described above, the first row L1 composed of the plurality of bonding pads 4 arranged in a line along the first direction and the plurality of examples arranged along the first direction as an example. The second row L2 composed of the bonding pads 5 is formed, and the plurality of bonding pads 4 constituting the first row L1 are set as one bonding pad set, and the plurality of bonding pads 5 constituting the second row L2 are formed. One bonding pad set is used. On the other hand, in the second embodiment, the first staggered row L3 composed of a plurality of bonding pads 6 arranged in a staggered manner along the first direction and the staggered along the first direction. And a plurality of bonding pads 6 constituting the first staggered row L3 form one bonding pad set, and a second staggered row L4 is formed. A plurality of bonding pads 7 constituting two staggered rows L4 form one bonding set.

従って、半導体装置１において第３の半導体装置から、製品部２に形成される種々の回路構成等を第３の半導体装置と異にする第４の半導体装置へ製品を展開する際、第１の千鳥状の列Ｌ３を構成する複数のボンディングパッド６からなるパッド群を第３の半導体装置に対応する１つのボンディングパッドセットとして取り扱い、同様に、第２の千鳥状の列Ｌ４を構成する複数のボンディングパッド７からなるパッド群を第４の半導体装置に対応する１つのボンディングパッドセットとして取り扱うことができる。その他のパッド用配線の構成等は前述した実施の形態１と同様であるため、その説明は省略する。   Accordingly, when the product is developed from the third semiconductor device to the fourth semiconductor device in which various circuit configurations formed in the product portion 2 are different from those of the third semiconductor device in the semiconductor device 1, A group of pads consisting of a plurality of bonding pads 6 constituting the staggered row L3 is handled as one bonding pad set corresponding to the third semiconductor device, and similarly, a plurality of pieces constituting the second staggered row L4. A pad group consisting of the bonding pads 7 can be handled as one bonding pad set corresponding to the fourth semiconductor device. Since the configuration of the other pad wirings and the like are the same as those of the first embodiment described above, description thereof is omitted.

このように、本実施の形態２によれば、千鳥状に配置されたボンディングパッドを有する半導体装置にも適用することが可能であり、前述した実施の形態１と同様の効果を得ることができる。   Thus, according to the second embodiment, it can be applied to a semiconductor device having bonding pads arranged in a staggered manner, and the same effect as in the first embodiment can be obtained. .

以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

本発明は、ワイヤボンディングを採用する半導体装置に適用することができる。   The present invention can be applied to a semiconductor device that employs wire bonding.

本発明の実施の形態１によるボンディングパッドの配置の一例を説明する半導体装置全体の平面図である。It is a top view of the whole semiconductor device explaining an example of arrangement | positioning of the bonding pad by Embodiment 1 of this invention. 図１の一部を拡大した要部平面図である。It is the principal part top view which expanded a part of FIG. （ａ）、（ｂ）、（ｃ）および（ｄ）はそれぞれ図２のＡ−Ａ′線、Ｂ−Ｂ′線、Ｃ−Ｃ′線およびＤ−Ｄ′線における要部断面図である。(A), (b), (c), and (d) are principal part sectional drawings in the AA 'line, the BB' line, the CC 'line, and the DD' line of FIG. 2, respectively. . 本発明の実施の形態１によるボンディングパッドの配置の他の例を説明する半導体装置全体の平面図である。It is a top view of the whole semiconductor device explaining the other example of arrangement | positioning of the bonding pad by Embodiment 1 of this invention. 本発明の実施の形態２によるボンディングパッドの配置の一例を説明する半導体装置の一部を拡大した要部平面図である。It is the principal part top view which expanded a part of semiconductor device explaining an example of arrangement | positioning of the bonding pad by Embodiment 2 of this invention.

符号の説明Explanation of symbols

１ 半導体装置
２ 製品部
３ 周辺部
４，５，６，７ ボンディングパッド
ＩＳ 絶縁膜
Ｌ１ 第１の列
Ｌ２ 第２の列
Ｌ３ 第１の千鳥状の列
Ｌ４ 第２の千鳥状の列
Ｍ１ １層目のパッド用配線
Ｍ２ ２層目のパッド用配線
Ｍ３ ３層目のパッド用配線
Ｍ４ ４層目のパッド用配線
Ｓ１ 第１の辺
Ｓ２ 第２の辺
Ｓ３ 第３の辺
Ｓ４ 第４の辺
Ｓｕｂ 半導体基板 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Product part 3 Peripheral part 4, 5, 6, 7 Bonding pad IS insulating film L1 1st row | line | column L2 2nd row | line | column L3 1st staggered row | line | column L4 2nd staggered row | line | column M1 1 layer Eye pad wiring M2 Second layer pad wiring M3 Third layer pad wiring M4 Fourth layer pad wiring S1 First side S2 Second side S3 Third side S4 Fourth side Sub Semiconductor substrate

Claims (10)

第１の方向に沿って配置された複数のボンディングパッドからなるボンディングパッドセットが、前記第１の方向と直交する第２の方向に沿って複数設けられており、
一のボンディングパッドセットを構成する各々のボンディングパッドが他のボンディングパッドセットを構成する各々のボンディングパッドと前記第２の方向と同一線上に並んで設けられており、
前記一のボンディングパッドセットは、前記他のボンディングパッドセットを構成し、前記第２の方向と同一線上に並んで配置されていないボンディングパッドとパッド用配線を介して電気的に接続されたボンディングパッドを含むことを特徴とする半導体装置。 A plurality of bonding pad sets each including a plurality of bonding pads arranged along the first direction are provided along a second direction orthogonal to the first direction;
Each bonding pad constituting one bonding pad set is provided side by side on the same line as each second bonding pad constituting the other bonding pad set,
The one bonding pad set constitutes the other bonding pad set, and is electrically connected via a pad wiring to a bonding pad that is not arranged on the same line as the second direction. A semiconductor device comprising: 請求項１記載の半導体装置において、前記一のボンディングパッドセットは、さらに前記他のボンディングパッドセットを構成し、前記第２の方向と同一線上に並んで配置されたボンディングパッドとパッド用配線を介して電気的に接続されたボンディングパッドを含むことを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the one bonding pad set further constitutes another bonding pad set via a bonding pad and a pad wiring arranged side by side on the same line as the second direction. And a bonding pad electrically connected to the semiconductor device. 請求項１記載の半導体装置において、前記一のボンディングパッドセットを構成する複数のボンディングパッドの全部または一部にボンディングワイヤが接続されることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein bonding wires are connected to all or a part of the plurality of bonding pads constituting the one bonding pad set. 請求項３記載の半導体装置において、前記ボンディングワイヤが接続されない前記一のボンディングパッドセットを構成するボンディングパッドおよび前記他のボンディングパッドセットを構成するボンディングパッドは、検査時に検査用のプローブ針を接触させる検査用パッドに用いられることを特徴とする半導体装置。 4. The semiconductor device according to claim 3 , wherein a bonding pad constituting the one bonding pad set to which the bonding wire is not connected and a bonding pad constituting the other bonding pad set are brought into contact with a probe needle for inspection at the time of inspection. A semiconductor device used for an inspection pad. 請求項１記載の半導体装置において、前記ボンディングパッドセットが前記第２の方向に沿って３セット以上設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein three or more sets of the bonding pad sets are provided along the second direction. 請求項１記載の半導体装置において、前記ボンディングパッドセットを構成する複数のボンディングパッドは最上層配線を用いて形成され、前記パッド用配線は前記最上層配線よりも下層の配線を用いて形成されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the plurality of bonding pads constituting the bonding pad set are formed using uppermost layer wiring, and the pad wiring is formed using lower layer wiring than the uppermost layer wiring. A semiconductor device characterized by comprising: 請求項１記載の半導体装置において、前記ボンディングパッドセットを構成する複数のボンディングパッドは種々の回路が形成された製品部に最上層配線を用いて形成されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the plurality of bonding pads constituting the bonding pad set are formed using a top layer wiring in a product part in which various circuits are formed. 請求項１記載の半導体装置において、前記ボンディングパッドセットを構成する複数のボンディングパッドは、種々の回路が形成された製品部以外の領域に最上層配線を用いて形成されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the plurality of bonding pads constituting the bonding pad set are formed using an uppermost layer wiring in a region other than a product portion where various circuits are formed. Semiconductor device. 請求項１記載の半導体装置において、前記ボンディングパッドセットを構成する複数のボンディングパッドは、前記第１の方向に沿って一列に配置されていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein a plurality of bonding pads constituting the bonding pad set are arranged in a line along the first direction. 請求項１記載の半導体装置において、前記ボンディングパッドセットを構成する複数のボンディングパッドは、前記第１の方向に沿って千鳥状に配置されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the plurality of bonding pads constituting the bonding pad set are arranged in a staggered manner along the first direction.
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