JP5107958B2 - Plasma display device - Google Patents

Description

  The present invention relates to an A / C type plasma display device (PDP device) of an address / display separation system used for display devices such as personal computers and workstations, flat-screen televisions, and plasma displays for displaying advertisements and information. .

  In an AC type color PDP device, an address / display separation method is widely adopted in which a period for selecting a cell to be displayed (address period) and a display period (sustain period) for discharging for display lighting are separated. In this system, charges are accumulated in the cells to be lit in the address period, and discharge for display is performed in the sustain period using the charges.

  Further, the PDP device is provided with a plurality of first electrodes extending in the first direction in parallel with each other, and a plurality of second electrodes extending in the second direction perpendicular to the first direction are provided in parallel with each other. A two-electrode type device, and a plurality of first electrodes and second electrodes extending in the first direction are alternately provided in parallel, and a plurality of third electrodes extending in a second direction perpendicular to the first direction are provided. There are three-electrode type devices provided in parallel to each other, and in recent years, a three-electrode type PDP has been widely used. The present invention can be applied to both a two-electrode type and a three-electrode type PDP device. Here, a three-electrode type PDP device will be described as an example.

  FIG. 1 is an exploded perspective view showing an example of a panel structure of a three-electrode type plasma display panel (PDP). As shown in the figure, X electrodes (first electrodes) 11 and Y electrodes (second electrodes) 12 that perform sustain discharge are alternately arranged in parallel on the front substrate 1. These electrode groups are covered with a dielectric layer 13, and the surface thereof is further covered with a protective layer 14 such as MgO. On the back substrate 2, address electrodes 15 extending in a substantially vertical direction with respect to the X electrodes 11 and the Y electrodes 12 are arranged, and these electrodes are further covered with a dielectric layer 16. On both sides of the address electrode 15, partition walls 17 are arranged to partition cells in the column direction. Further, on the side surfaces of the dielectric layer 16 and the partition wall 17 on the address electrode 15, phosphors 18, 19, and 20 that are excited by ultraviolet rays and generate visible light of red (R), green (G), and blue (B). It has been applied. The front substrate 1 and the rear substrate 2 are bonded together so that the protective layer 14 and the partition wall 17 are in contact with each other, and a discharge gas such as neon (Ne) or xenon (Xe) is enclosed therein to constitute a panel.

  In this structure, the X electrode 11 and the Y electrode 12 are each composed of a bus electrode and a transparent electrode formed of a metal layer, and the transparent electrodes of the pair of the X electrode 11 and the Y electrode 12 are arranged close to each other. . The display cell is formed at the intersection of the pair of X electrode 11 and Y electrode 12 and address electrode 15.

  Since it is difficult to perform gradation display by controlling the discharge intensity in the plasma display panel, one image (one frame: 1/60 second) is composed of a plurality of subfields, and a subfield that is lit for each cell is provided. Tone display is performed by combining. FIG. 2 is a diagram showing a conventional example of a subfield configuration, which is an example of an address / display separation method widely used in current PDP apparatuses. As shown in the figure, one frame is composed of n subfields SF1-SFn. Each subfield has a reset period R, an address period A, and a sustain period S. In the reset period R, the charge formed in the sustain period of the immediately preceding subfield is erased (or reduced), and charge rearrangement is performed to assist discharge in the next address period, so that all cells are omitted. Make the same state. In the address period A, an address discharge for determining a cell to be lit (lit cell) is performed, and wall charges for selectively generating a sustain discharge are formed in the lit cell. In the sustain period S, a sustain discharge is repeatedly generated in the lighted cell. The operations in the reset period R and the address period A are the same in each subfield. The display luminance is determined by the number of sustain pulses applied during the sustain period, and the number of sustain pulses applied for each subfield is generally different, but a subfield having the same or similar number of sustain pulses in one frame, that is, In some cases, subfields having the same or similar display luminance are provided. Also, various configurations have been proposed as to how to arrange various luminance weighting subfields within each frame. Here, in order to simplify the explanation, the subfields are arranged in a direction in which the luminance increases. Although the following description will be given by taking the case of arrangement as an example, the present invention is not limited to such arrangement of subfields.

  FIG. 3 is a diagram showing a conventional example of driving waveforms of an address / display separation type three-electrode type PDP device. As shown in the figure, in the reset period R, an on-cell reset blunt wave 81 whose voltage gradually decreases is applied to the X electrode while the on-cell reset voltage 87 is applied to the Y electrode, and the sustain in the previous subfield is performed. The wall charge of the discharged cell (lighted cell) is erased or reduced. This process is called an on-cell reset process. Next, in the state where the write reset voltage 82 is applied to the X electrode, the write blunt wave 88 is applied to the Y electrode to generate a discharge in all the cells, thereby forming the same wall charge in the vicinity of the electrode. Further, an adjustment blunt wave 89 is applied to the Y electrode in a state where the adjustment voltage 83 is applied to the X electrode, and the formed wall charge is adjusted to a predetermined amount. Here, a negative wall charge is formed in the vicinity of the Y electrode, and a positive wall charge is formed in the vicinity of the X electrode and the address electrode. The above is the reset process, and all the cells are in the same state by this reset process. Here, in order to facilitate the processing in the next address period, a predetermined wall charge amount is left in all cells, but there are various modifications such as a case where no wall charge is left.

  Furthermore, there is a case where the process of erasing or reducing the wall charge of the cell in which the sustain discharge has been performed in the previous subfield may be included in the process of the sustain period. Here, a part of the process of the reset period including the following explanation is included. And In any case, this process is performed between the sustain period and the reset period.

  In the next address period A, with the X bias voltage 84 applied to the X electrode and the Y bias voltage (non-selection potential) 90 applied to the Y electrode, scanning of the voltage −Vs is performed while sequentially changing the position of the applied Y electrode. A pulse 91 is applied, and an address pulse 94 of voltage VA is applied to the address electrode of the lighted cell in synchronization with the scan pulse 91. Thereby, in the lighting cell, a large voltage VA + Vs is applied between the Y electrode and the address electrode, so that an address discharge is generated. At this time, since a large electric field is generated between the X electrode and the Y electrode, the address discharge is also generated between the Y electrode and the X electrode by being induced by the address discharge between the Y electrode and the address electrode. By shifting to the address discharge between the Y electrode and the X electrode, wall charges having opposite polarities to the voltages applied to the respective electrodes are accumulated in the vicinity of the Y electrode and the X electrode. This wall charge is used to selectively generate the next sustain discharge. Here, the X bias voltage 84 is Vx, the Y bias voltage (non-selection potential) 90 is a negative voltage -Vy, the scan pulse 91 voltage is -Vs, and the address pulse 94 voltage is VA. These voltages generate address discharge in the cells to which the scan pulse 91 and the address pulse 94 are simultaneously applied, do not generate discharge in the other cells, and in the cells in which address discharge has occurred (lighted cells), the X electrodes and Y It is set so that a wall charge capable of selectively generating the next sustain discharge is formed in the vicinity of the electrode. Note that the wall charges left in all the cells at the end of the reset period work to ensure that an address discharge is generated even if the voltage applied between the Y electrode and the address electrode is small by the scan pulse 91 and the address pulse 94. . The wall charges of the cells in which no address discharge has occurred (wall charges formed during the reset period) are held until the next discharge occurs. Furthermore, although the example which forms the wall charge required to generate the address discharge in the lighting cell and selectively perform the sustain discharge is described here, the uniform wall charge is formed in all the cells during the reset period. There is also a method of erasing wall charges by generating an address discharge in a non-lighted cell.

  In the next sustain period, a sustain pulse 85 having a voltage −Vs is applied to the X electrode, and a sustain pulse 92 having a voltage Vs is applied to the Y electrode. As a result, a voltage of 2 Vs is applied between the X electrode and the Y electrode, and in the lighting cell in which the address discharge is generated, the voltage due to the wall charge formed by the address discharge is added, so the sustain discharge is generated exceeding the discharge start voltage. However, no discharge occurs in a non-lighted cell in which no address discharge has occurred. In the cell in which the sustain discharge is generated, wall charges having a reverse polarity are formed by the sustain discharge. Next, when a sustain pulse 86 having a voltage Vs is applied to the X electrode and a sustain pulse 93 having a voltage −Vs is applied to the Y electrode, the voltage due to the reverse polarity wall charges formed by the sustain discharge is generated in the lighting cell in which the sustain discharge has occurred. Addition causes the next sustain discharge to occur, and no discharge occurs in the non-lighted cells in which no sustain discharge has occurred. Thus, since the polarity of the wall charges formed by applying the sustain pulse is reversed, the sustain discharge continues in the lighted cell by alternately applying the sustain pulse having the opposite polarity between the X electrode and the Y electrode. Occur.

  The luminance of the subfield is set by the number of sustain discharges. As shown in FIG. 3, the sustain discharge is generated twice in SF1, and the sustain discharge is generated four times in SF2, and the number of sustain discharges is further increased in the subfield having a higher luminance. In general, since the cycle of the sustain pulse is constant, the length of the sustain period is determined by the number of sustain discharges. In the AC type, since the two discharges whose polarity is inverted are generally one set, the number of sustain discharges is increased by a multiple of two.

  Here, the discharge in the PDP will be described. During the reset period, discharge for forming a predetermined amount of wall charges in all cells, in other words, discharge due to the reset voltage 82 and the write blunt wave 88 and discharge due to the adjustment voltage 83 and the adjustment blunt wave 89 are discharges not related to display. The light emission by this is the same in all the cells, so that the contrast is lowered. Although not shown in FIG. 3, there is a case where a large voltage is applied between the X electrode and the Y electrode for initialization to generate an initialization discharge in all cells, and such discharge is also related to display. Does not discharge, reducing the contrast. Such a discharge is desirably as small as possible. Therefore, the initialization discharge is not performed as much as possible. In addition, the discharge for forming a predetermined amount of wall charges in all the cells uses an obtuse wave as described above, thereby making the emission intensity very small.

  The discharge by the on-cell reset process for erasing or reducing the wall charge of the lighted cell in the previous subfield in the reset period, in other words, the discharge by the on-cell reset voltage 87 and the on-cell reset blunt wave 81 is displayed in the previous subfield. It is a discharge related to. The address discharge and the sustain discharge are discharges related to display.

  Conventionally, the luminance of each subfield generally takes into account only the luminance of light emitted by the sustain discharge. Further, charge erasure was performed with a low intensity discharge using an obtuse wave, such as an electric discharge by the on-cell reset voltage 87 and the on-cell reset obtuse wave 81.

  The display quality of the PDP device has been improved year by year, but further improvement is required. In particular, there is a demand for improvement in gradation expression in low luminance display. In view of this, Japanese Patent Laid-Open No. 11-65517 describes that it is necessary to consider luminance due to other discharges related to display in gradation expression, while considering only light emission luminance due to sustain discharge. is doing.

  Further, in the AC color plasma display, when gradation display is performed by combining subfields having different luminances, the low luminance gradation expression ability is determined by the luminance of the subfield with the lowest luminance. Therefore, the above-mentioned Japanese Patent Application Laid-Open Nos. 11-65517 and 2003-66897 describe a configuration in which a sustain field is not provided, but a subfield configured only by a reset period and an address period is provided.

  FIG. 4 is a diagram showing a subfield configuration when a subfield having no sustain period is provided in the frame, and FIG. 5 is a diagram showing examples of driving waveforms of SF1 and SF2 in that case. FIG. 5 shows an example in which the configuration described in Japanese Patent Laid-Open Nos. 11-65517 and 2003-66897 is applied to the drive waveform of FIG. As shown in FIGS. 4 and 5, SF1 has only a reset period R and an address period A. Thereby, the luminance of SF1 can be reduced, and the expression capability of low luminance gradation is improved. As shown in FIG. 5, the operation during the address period of SF1 and the operation during the address period of SF2 are the same.

JP 11-65517 A JP 2003-66897 A Japanese Patent No. 2801893

  As described above, by providing a subfield including only a reset period and an address period without providing a sustain period, the ability to express low luminance gradation is improved, but further improvement is demanded.

  SUMMARY OF THE INVENTION An object of the present invention is to realize a plasma display device that further improves the ability to express low luminance gradation.

  In order to achieve the above object, the plasma display device (PDP device) according to the first aspect of the present invention is a three-electrode type PDP device, which is not provided with a sustain period, but includes a reset field and an address period. Are provided in one frame, and the address discharge is performed only between the Y (second) electrode and the address (third) electrode. Thereby, the minimum luminance of the subfield can be reduced, and the low luminance gradation expression capability of the plasma display apparatus can be further improved.

  In other words, the PDP device according to the first aspect of the present invention includes a first electrode group and a second electrode group arranged in parallel on a first substrate, and a second substrate facing the first substrate. A third electrode group arranged to intersect the first and second electrode groups, and one frame is composed of a plurality of subfields, and the plurality of subfields are cells to be lit A first subfield including an address period in which address discharge is performed to select a cell, a sustain period in which sustain discharge is performed in a cell selected in the address period, and the address period includes the address period without the sustain period. A second subfield, and in the address period in the first subfield, the first electrode continues between the second electrode group and the third electrode group. Between the first electrode group and the second electrode group. In the address period in the second subfield, the discharge is performed between the first electrode group and the second electrode group. The address discharge is performed between the second electrode group and the third electrode group without shifting.

  In order to achieve the above object, the PDP device according to the second aspect of the present invention provides at least two second subfields configured only by a reset period and an address period in one frame. By changing the strength of the address discharge, a subfield with lower luminance is provided.

  In other words, in the PDP device according to the second aspect of the present invention, one frame includes a plurality of subfields, and the plurality of subfields includes an address period for performing an address discharge for selecting a cell to be lit, A first subfield including a sustain period in which a sustain discharge is performed in a cell selected in the address period; and a second subfield including the address period without the sustain period; It comprises at least two second subfields having different intensities.

  According to Japanese Patent Application Laid-Open No. 11-65517 and Japanese Patent Application Laid-Open No. 2003-66897, as shown in FIG. 5, the address period of the subfield having only the reset period and the address period has a sustain period. The same processing as that in the field address period is performed to form wall charges for selectively generating a sustain discharge. Therefore, the intensity of the address discharge is two discharges between the Y (second) electrode and the address (third) electrode, and between the X (first) electrode and the Y electrode. Compared to the sustain discharge, it has the same magnitude. However, in the case of the second subfield having no sustain period, it is not necessary to form wall charges for selectively generating the sustain discharge, so that the strength of the address discharge can be further reduced. Thereby, the luminance of the subfield can be further reduced. As described above, since there is no restriction of forming wall charges for selectively generating the sustain discharge, the intensity of the address discharge can be arbitrarily set, and the intensity of the address discharge can be changed to further increase the conventional level. A low-luminance subfield can be provided.

  The present invention can be applied to the three-electrode type PDP device described in FIG. 1 or the two-electrode type PDP device as long as it is an address / display separation type PDP device.

  In the case of the three-electrode type PDP device described in JP-A-11-65517 and JP-A-2003-66897, scanning is performed by applying a large voltage between the X electrode group and the Y electrode group in the address period. When an address discharge is generated by a pulse and an address pulse, the address discharge is also induced between the X electrode and the Y electrode, and wall charges for selectively generating a sustain discharge are formed in the vicinity of the X and Y electrodes. I try to do it. On the other hand, even if an address discharge is generated between the Y electrode and the address electrode by reducing the voltage applied between the X electrode group and the Y electrode group, no address discharge is generated between the X electrode and the Y electrode. By doing so, the intensity of the address discharge is reduced and the luminance can be lowered. That is, one low-luminance subfield having no sustain period is provided so that no discharge is generated between the X electrode and the Y electrode during address discharge.

  Since the luminance of the subfield can be further reduced in this way, for example, at least two low luminance subfields having no sustain period are provided, one of which is an address period having the same condition as the subfield having the sustain period. In other words, a subfield for forming a wall charge for a sustain discharge and a lower subfield in which address discharge does not occur between the X electrode and the Y electrode are low luminance and It is possible to provide a plurality of subfields having different luminances.

  Furthermore, since the restriction of forming wall charges for selectively generating the sustain discharge is eliminated, the strength of the address discharge between the Y electrode and the address electrode is reduced, and the strength of the address discharge between the Y electrode and the address electrode is reduced. Can also be reduced. In order to reduce the strength of the address discharge between the Y electrode and the address electrode, the absolute value of the voltage between the Y electrode and the address electrode when the address pulse and the sustain pulse are simultaneously applied is made small. Specifically, the voltage of the address pulse and / or the scan pulse is changed.

  In addition, the intensity of the address discharge between the X electrode and the Y electrode and the intensity of the address discharge between the Y electrode and the address electrode are changed in smaller steps, and the number of luminance steps in the low luminance subfield can be reduced by combining these changes. Further increase is possible.

  In the case of a two-electrode type PDP device, the absolute value of the voltage between the first electrode (horizontal electrode) and the second electrode (vertical electrode) when the address pulse and the sustain pulse are simultaneously applied is made small.

  According to the present invention, since the minimum luminance of the subfield can be further reduced, the expression capability of low luminance gradation is improved, and the display quality can be improved.

It is a disassembled perspective view of 3 electrode type PDP. It is a figure which shows the prior art example of a field structure. It is a figure which shows the prior art example of a drive waveform. It is a figure which shows the other conventional example of a field structure. It is a figure which shows the other conventional example of a drive waveform. It is a figure which shows the whole structure of the PDP apparatus of 1st Example of this invention. It is a figure which shows the drive waveform of the PDP apparatus of 1st Example. It is a figure which shows the modification of the drive waveform of the PDP apparatus of 1st Example. It is a figure which shows the modification of the drive waveform of the PDP apparatus of 1st Example. It is a disassembled perspective view of PDP used in 2nd Example of this invention. It is a figure which shows the whole structure of the PDP apparatus of 2nd Example. It is a figure which shows the drive waveform of the PDP apparatus of 2nd Example. It is a figure which shows the drive waveform of the PDP apparatus of 2nd Example. It is a disassembled perspective view of PDP used in 3rd Example of this invention. It is a figure which shows the electrode shape of PDP of 3rd Example. It is a figure which shows the whole structure of the PDP apparatus of 3rd Example. It is a figure which shows the drive waveform of the PDP apparatus of 3rd Example.

  FIG. 6 is a diagram showing the overall configuration of the plasma display apparatus (PDP apparatus) of the first embodiment of the present invention. The plasma display panel (PDP) 30 has the structure shown in FIG. The address driver 31 applies an address pulse of the ground level or voltage Va to each address electrode 15. The Y scan driver 32 sequentially applies a scan pulse of the voltage −Vs to each Y electrode, and a predetermined voltage such as a sustain pulse supplied to all the second electrodes (Y electrodes) 12 via the Y sustain circuit 33. Are applied in common. The X sustain circuit 34 applies a predetermined voltage such as a sustain pulse to the first electrode (X electrode) 11 in common. The control circuit 35 controls each part described above.

  The PDP apparatus of the first embodiment has a configuration that has been widely known, and one frame is composed of a plurality of subfields, but the drive waveforms in the subfields with low luminance are different. Further detailed description of the configuration of the PDP apparatus will be omitted, and only the drive waveform will be described.

  FIG. 7 is a diagram showing drive waveforms in the PDP apparatus of the first embodiment, and shows drive waveforms of the four subfields SF1-SF4 on the low luminance side. A subfield with high luminance of SF5 or higher has the same drive waveform as SF4, and only the number of sustain pulses is different.

  As apparent from the comparison with the conventional drive waveform of FIG. 5, SF3 and SF4 of the first embodiment have the same drive waveform as SF1 and SF2 of the conventional example of FIG. Therefore, in SF4, the same operation as that described with reference to FIG. 3 is performed, and in SF3, an operation excluding the sustain period from the operation in SF4 is performed. Also, SF1 and SF2 have no sustain period.

  In SF2, the same operation as SF3 and SF4 is performed in the reset period R. Thereafter, in address period A, a scan pulse of voltage -Vs is sequentially applied to the Y electrode while changing the application position in a state where the ground potential is applied to the X electrode and the Y bias voltage (non-selection potential) -Vy is applied to the Y electrode. The address pulse of voltage VA is applied in synchronization with the scan pulse. Further, as in SF3, no sustain period is provided. In other words, the voltage Vx is applied to the X electrode in SF3 and SF4, but the ground potential is applied in the first embodiment.

  In SF3 and SF4, since the voltage Vx is applied to the X electrode, a large voltage of Vx + Vs is applied between the Y electrode to which the scan pulse is applied and the X electrode group, and the scan pulse and the address pulse are simultaneously applied. When an address discharge is generated between the Y electrode and the address electrode in the lighted cell, the address discharge is induced and an address discharge is also generated between the Y electrode and the X electrode (transition to the address discharge between the Y electrode and the X electrode). Thus, a positive wall charge is formed in the vicinity of the Y electrode, and a negative charge is formed in the vicinity of the X electrode. In SF4, a sustain discharge is selectively generated using this wall charge. Accordingly, the intensity of the address discharge in SF3 and SF4 is the intensity of the discharge intensity between the Y electrode and the address electrode and the intensity of the discharge between the Y electrode and the X electrode. The luminance is the sum of luminance due to discharge.

  In SF2, since the ground potential is applied to the X electrode, only the voltage of Vs is applied between the Y electrode to which the scan pulse is applied and the X electrode group, and even if an address discharge occurs. A discharge between the Y electrode and the X electrode is not induced. Therefore, the address discharge in SF2 is only the discharge between the Y electrode and the address electrode, and the luminance due to the address discharge is lower than that in SF3 and SF4. Since the address discharge between the Y electrode and the X electrode does not occur in the address period of SF2, no wall charge for selectively performing the sustain discharge is formed in the vicinity of the Y electrode and the X electrode. However, in SF2, there is no sustain period. No problem.

Actually, the luminance when address discharge was performed at Vs = 80V, Vx = 80V, VA = 60V as in SF3 and SF4 was 0.97 cd / m ² , but as in SF2, Vx = 0V. The luminance when address discharge was performed was 0.36 cd / m ² , which was a low luminance of less than half.

  In SF1, the same operation as in SF2 to SF4 is performed in the reset period R. Thereafter, in address period A, with the ground potential applied to the X electrode and Vy applied to the Y electrode, a scan pulse of voltage -Vs is sequentially applied to the Y electrode while changing the application position, and the voltage is synchronized with the scan pulse. An address pulse of VA1 is applied. Further, as in SF2 and SF3, no sustain period is provided. In other words, an address pulse of voltage VA is applied in SF2, whereas an address pulse of voltage VA1 lower than VA is applied in SF1.

  Therefore, in SF1, as in SF2, address discharge between the Y electrode and the X electrode does not occur. Further, since the voltage of the address pulse is VA1 lower than VA, the intensity of the address discharge between the Y electrode and the address electrode is reduced, and the luminance of SF1 is further lower than that of SF2.

  As described above, in the subfield configuration of the PDP apparatus according to the first embodiment, the subfield having a lower luminance than the minimum luminance subfield having the sustain period is provided in three stages. Compared with the sub-field configuration, sub-fields with lower luminance are provided in two stages. For this reason, the ability to express low luminance gradation is improved.

  In the driving waveform of the first embodiment shown in FIG. 7, in SF1 and SF2, the potential of the X electrode in the address period is set to the ground. However, the potential of the X electrode may be a voltage that is induced by an address discharge between the Y electrode and the address electrode and does not generate an address discharge between the Y electrode and the X electrode. FIG. 8 is a diagram illustrating a modified example of the drive waveform in which the potential of the X electrode is changed in the address period. In this modification, the potential of the X electrode in the address period is set to Y bias voltage (non-selection potential) −Vy applied to the Y electrodes other than the Y electrode to which the scan pulse is applied in the address period. As a result, the possibility of address discharge occurring between the Y electrodes and the X electrodes caused by the address discharge between the Y electrodes and the address electrodes is further reduced.

  In the driving waveform of the first embodiment shown in FIG. 7, the address pulse voltage is set to VA1 in SF1 to reduce the strength of the address discharge between the Y electrode and the address electrode. However, as shown in FIG. 9, when the address pulse voltage is VA, the scan pulse voltage is −Vs1 (Vs1 is smaller than Vs), and the address pulse and the scan pulse are applied simultaneously, the Y electrode and the address electrode It is also possible to reduce the strength of the address discharge by reducing the voltage between them.

  FIG. 10 is an exploded perspective view of the PDP used in the PDP apparatus of the second embodiment of the present invention, and FIG. 11 is a diagram showing the overall configuration of the PDP apparatus of the second embodiment. The second embodiment is an embodiment in which the present invention is applied to an ALIS PDP apparatus described in Japanese Patent No. 2801893. The ALIS system PDP device is described in Japanese Patent No. 2801893 and will not be described in detail. However, n + 1 X electrodes 11 and n Y electrodes 12 are arranged at equal intervals, and both sides of each Y electrode 12 are arranged. Discharge is performed between the X electrode 11 and the 2n display lines. Therefore, each X electrode 11 also discharges between the Y electrodes 12 located on both sides. In the ALIS PDP apparatus, interlaced display is performed, and among the 2n display lines, odd-numbered display lines are displayed in odd-numbered fields, and even-numbered display lines are displayed in even-numbered fields. The odd-numbered display lines are formed between the odd-numbered X electrodes and the odd-numbered Y electrodes and between the even-numbered X electrodes and the even-numbered Y electrodes, and the even-numbered display lines are connected to the odd-numbered Y electrodes and the even-numbered Y electrodes. It is formed between the Xth electrodes and between the even-numbered Y electrodes and the odd-numbered X electrodes.

  As shown in FIG. 10, the ALIS PDP has substantially the same configuration as the PDP in FIG. 2 except that the X electrode 11 and the Y electrode 12 are arranged at equal intervals. As shown in FIG. 11, the address driver 11 drives the address electrode 15. The Y scan driver 32 applies a scan pulse to each Y electrode 12, and applies a voltage supplied from the odd-numbered Y sustain circuit 33O to the odd-numbered Y electrodes in common, and a voltage supplied from the even-numbered Y sustain circuit 33E. Is applied in common to even-numbered Y electrodes. The odd-numbered X sustain circuit 34O applies a voltage to the odd-numbered X electrodes in common, and the even-numbered X sustain circuit 34E applies a voltage to the even-numbered X electrodes in common. The control circuit 35 controls each part.

  FIGS. 12 and 13 are diagrams showing driving waveforms of SF1 to SF4 in the odd field of the second embodiment, where X1 is a waveform applied to the odd-numbered X electrode, and X2 is applied to the even-numbered X electrode. Y1 represents a waveform applied to odd-numbered Y electrodes, and Y2 represents a waveform applied to even-numbered Y electrodes. Note that the drive waveform in the even field is omitted. This waveform diagram corresponds to FIG. 7 showing the drive waveform of the first embodiment, and the drive waveform of the sub-field with high luminance of SF5 or higher is not shown, but the waveform is the same as that of SF4 and the sustain waveform. Only the number of pulses is different. As shown in the figure, the sustain period S is not provided in SF1 to SF3. The odd display lines L1, L5, L9,..., L4n-3 among the odd display lines are formed between the X1 electrode and the Y1 electrode, and the even display lines L3, L7 among the odd display lines. , L11,..., L4n-1 are formed between the X2 electrode and the Y2 electrode. For reference, the odd display lines L2, L6, L10,..., L4n-2 of the even display lines are formed between the Y1 electrode and the X2 electrode, and the even display lines of the even display lines. L4, L8, L11,..., L4n are formed between the Y2 electrode and the X1 electrode.

  First, the driving waveform of SF4 will be described. As shown in the figure, waveforms applied to the X1 and X2 electrodes, the Y1 and Y2 electrodes, and the address electrodes in the reset period R are the same as those in FIGS. At the end of the reset period, negative wall charges are formed near the Y1 and Y2 electrodes, and positive wall charges are formed near the X1 and X2 electrodes and the address electrodes.

  The next address period A is divided into the first half and the second half. In the first half, the odd-numbered display lines L1, L5, L9,..., L4n-3 are written in the odd-numbered display lines. Writing is performed to even-numbered display lines L3, L7, L11,..., L4n-1 among the display lines.

  In the first half, after applying the ground potential to the X2 and Y2 electrodes, the Y1 electrode to be applied with the X bias voltage Vx applied to the X1 electrode and the Y bias voltage (non-selection potential) −Vy applied to the Y1 electrode The scan pulse of voltage -Vs is applied while sequentially changing the position of, and the address pulse of voltage VA is applied to the address electrode of the lighting cell in synchronization with the scan pulse. In other words, the same drive waveform as that of SF4 of the first embodiment is applied to the odd-numbered X1 electrode, Y1 electrode, and address electrode. As a result, an address discharge is generated between the Y1 electrode and the address electrode in the lighted cell of the odd display line among the odd display lines, and an address discharge is also generated between the Y1 electrode and the X1 electrode. A negative wall charge is formed in the vicinity of the odd-numbered X1 electrode, and a positive wall charge is formed in the vicinity of the odd-numbered Y1 electrode.

  In the second half of the address period, the ground potential is applied to the X1 and Y1 electrodes, the X bias voltage Vx is applied to the X2 electrode, and the Y bias voltage −Vy is applied to the Y2 electrode. A voltage -Vs scan pulse is applied while sequentially changing the voltage, and an address pulse of voltage VA is applied to the address electrode of the lighting cell in synchronization with the scan pulse. In other words, the same drive waveform as that of SF4 of the first embodiment is applied to the even-numbered X2 electrode, Y2 electrode, and address electrode. As a result, an address discharge is generated between the Y2 electrode and the address electrode in the even-numbered display line of the odd display lines, and an address discharge is also generated between the Y2 electrode and the X2 electrode. A negative wall charge is formed in the vicinity of the even-numbered X2 electrode, and a positive wall charge is formed in the vicinity of the even-numbered Y2 electrode.

  As described above, writing is performed on the odd-numbered display lines.

  In the sustain period, a sustain pulse of voltage -Vs is applied to the X1 electrode, and a sustain pulse of voltage Vs is applied to the Y1 electrode while a ground potential is applied to X2, Y2 and the address electrode. As a result, a voltage of 2 Vs is applied between the X1 electrode and the Y1 electrode, and the wall charge voltages in the vicinity of the X1 electrode and the Y1 electrode are added to reach the discharge start voltage. Sustain discharge occurs. At this time, a voltage of Vs is applied between the Y1 electrode and the X2 electrode and between the Y2 electrode and the X1 electrode constituting the even display line, and the voltage due to the wall charge is also added, but the discharge start voltage is not reached, so the discharge Does not occur. Due to the sustain discharge between the X1 electrode and the Y1 electrode in the lighting cell, a positive wall charge is formed in the vicinity of the X1 electrode and a negative wall charge is formed in the vicinity of the Y1 electrode. Since the X2 electrode and the Y2 electrode are not discharged, the wall charge is maintained, and there is a negative wall charge near the X2 electrode and a positive wall charge near the Y2 electrode.

  Next, a sustain pulse of voltage Vs is applied to the X1 and Y2 electrodes, and a sustain pulse of voltage -Vs is applied to the Y1 and X2 electrodes. That is, reverse-phase sustain pulses are applied between the X1-Y1 electrodes and between the X2-Y2 electrodes. As described above, the voltage due to the wall charges in the vicinity of the X1, Y1, X2, and Y2 electrodes increases the voltage between the X1-Y1 electrodes and between the X2-Y2 electrodes, and thus reaches the discharge start voltage, and between the X1-Y1 electrodes. And a sustain discharge is generated between the X2-Y2 electrodes. This discharge inverts the polarity of the wall charges near the X1, Y1, X2, and Y2 electrodes. Note that no sustain discharge occurs because no voltage is applied between the Y1-X2 electrodes and between the Y2-X1 electrodes.

  Hereinafter, when the sustain pulse is applied while reversing the polarity of the sustain pulse applied between the X1-Y1 electrodes and between the X2-Y2 electrodes, a sustain discharge is repeatedly generated.

  Since the first sustain discharge occurred only between the X1-Y1 electrodes and did not occur between the X2-Y2 electrodes, the sustain discharge between the X2-Y2 electrodes is reduced by one time. Therefore, at the end of the sustain period, with the ground potential applied to X1, Y1, and the address electrode, a sustain pulse of voltage Vs is applied to the X2 electrode, and a sustain pulse of voltage -Vs is applied to the Y2 electrode. Sustain discharge is generated only between the Y2 electrodes. Due to the sustain discharge between the X2 and Y2 electrodes, the wall charges near the X2 and Y2 electrodes are inverted to have the same polarity as the wall charges near the X1 and Y1 electrodes. As a result, during the reset period, a common on-cell reset voltage is applied to all the X electrodes and an on-cell reset blunt wave is applied to all the Y electrodes, so that the wall charges of the lighted cells in the previous subfield can be erased. Here, two sustain discharges occur in each odd display line.

  SF3 is a waveform obtained by removing the drive waveform of the sustain period S from SF4. In the address period A, an address discharge is generated between the X electrode and the Y electrode to form a wall charge for the sustain discharge. Does not occur. Therefore, the luminance of SF3 is lower than the luminance of SF4 by the luminance due to the sustain discharge.

  SF2 differs from SF3 in that the potentials of the X1 and X2 electrodes in the address period A are changed from Vx to the ground potential. As a result, the address discharge between the X electrode and the Y electrode in the address period A does not occur, and the wall charge for the sustain discharge is not formed. Therefore, the luminance of SF2 is lower than the luminance of SF3 by the luminance due to the address discharge between the X electrode and the Y electrode.

  SF1 is different from SF2 in that the voltage of the address pulse is a voltage VA1 lower than the voltage VA. As a result, the intensity of the address discharge between the Y electrode and the address electrode is lowered, and the luminance of SF1 is lower than the luminance of SF2 by the amount of the intensity reduction of the address discharge.

  The operation of SF4 in the odd field has been described above. In the even field, the driving waveform of the X1 electrode is applied to the X2 electrode, and the driving waveform of the X2 electrode is applied to the X1 electrode.

  Also in the second embodiment, a modification in which the potential of the X electrode during the address period described in the first embodiment is changed, or a modification in which the voltage of the scan pulse is changed instead of changing the voltage of the address pulse to VA1 is applied. Is possible.

  As described above, in the subfield configuration of the PDP apparatus of the second embodiment, the subfield having a lower luminance than the minimum luminance subfield having the sustain period is provided in three stages. Improves the ability to express

  FIG. 14 is an exploded perspective view of a PDP used in the PDP apparatus according to the third embodiment of the present invention. The third embodiment is an embodiment in which the present invention is applied to a two-electrode type PDP apparatus. In the two-electrode type plasma display panel (PDP), there are a form in which intersecting electrodes are formed on one substrate and a form in which the intersecting electrodes are formed on opposite substrates. Here, a form in which intersecting electrodes are formed on one substrate. An example to which the present invention is applied will be described. However, the present invention is not limited to this, and can be applied to a form in which intersecting electrodes are formed on opposing substrates.

  As shown in FIG. 14, in the two-electrode type PDP, a horizontal electrode (first electrode) group composed of a transparent electrode 51 and a bus electrode 52 is arranged in parallel on a transparent substrate 1, and a dielectric layer 53 is placed thereon. And a vertical electrode (second electrode) group composed of a transparent electrode 54 and a bus electrode 55 is arranged in parallel, and a dielectric layer 56 is further formed thereon. Then, a protective layer 57 such as MgO is provided thereon. The back substrate 42 is provided with a two-dimensional partition wall composed of partition walls 58 extending in the vertical direction and partition walls 59 extending in the horizontal direction, and phosphors 60, 61, 62 are applied to the back substrate 42 and the side surfaces of the partition walls.

  FIG. 15 is a diagram showing the electrode shape of the PDP of FIG. As shown in the drawing, the edges of the horizontal transparent electrode 51 protruding from the horizontal bus electrode 52 and the vertical transparent electrode 54 protruding from the vertical bus electrode 55 are formed at a predetermined interval. Discharge is possible between the transparent electrodes 54. Since the partition wall is provided so as to overlap the horizontal bus electrode 52 and the vertical bus electrode 55, no discharge occurs between the horizontal bus electrode 52 and the vertical bus electrode 55.

  FIG. 16 is a diagram showing the overall configuration of the PDP apparatus in the third embodiment. The vertical electrode driver 61 applies address pulses to the vertical electrodes of the PDP 60 and applies a predetermined voltage supplied from the vertical sustain circuit 63 to the vertical electrodes. The horizontal electrode driver 62 applies scan pulses to the horizontal electrodes of the PDP 60 and applies a predetermined voltage supplied from the horizontal sustain circuit 64 to the horizontal electrodes. The control circuit 65 controls each part.

  FIG. 17 is a diagram showing drive waveforms of the third embodiment, where H1 shows a waveform applied to the horizontal electrode, and V shows a waveform applied to the vertical electrode. This waveform diagram corresponds to FIG. 7 showing the drive waveform of the first embodiment, and the drive waveform of the subfield with high luminance of SF4 or higher is not shown, but the waveform is the same as that of SF3 and the sustain waveform. Only the number of pulses is different. As illustrated, the sustain period S is not provided in SF1 and SF2.

  First, the driving waveform of SF3 will be described. As shown, the waveforms applied to the horizontal and vertical electrodes in the reset period R are similar to the waveforms applied to the X and Y electrodes in FIGS. Therefore, in the reset period, the wall charges of the lighted cells in the previous subfield are erased and the same wall charges are formed in all the cells.

  In the address period A, with the bias voltage −Vy applied to the horizontal electrode and the ground potential applied to the vertical electrode, a scan pulse of voltage −Vs is applied to the horizontal electrode while sequentially changing the application position, and is synchronized with the scan pulse. Then, an address pulse of voltage VA is applied to the vertical electrode of the lighting cell. As a result, an address discharge is generated in the lighted cell, and a wall charge for selectively generating a sustain discharge is formed. In this case, a positive wall charge is formed near the horizontal electrode of the lighting cell, and a negative wall charge is formed near the vertical electrode.

  In the sustain period S, a sustain pulse of voltage Vs is applied to the horizontal electrode, and a sustain pulse of voltage -Vs is applied to the vertical electrode. The voltage due to the wall charges is added to this, exceeding the discharge start voltage, and sustain discharge occurs. Since the sustain discharge reverses the polarity of the wall charges, the sustain discharge is generated again when the sustain pulse having the reversed polarity is applied next. Thereafter, when the sustain pulse is repeatedly applied while inverting the polarity, the sustain discharge is repeated.

  SF2 is different in that the sustain period S is not provided in SF3. Thereby, wall charges for the sustain discharge are formed in the address period A, but since the sustain discharge is not performed, the brightness of SF2 is lower than that of SF3 by the brightness due to the sustain discharge.

  SF1 is different from SF2 in that the scan pulse voltage is changed from -Vs to -Vs1 (Vs1 is smaller than Vs) and the address pulse voltage is changed from VA to VA1 (VA1 is smaller than VA). As a result, the voltage applied between the horizontal electrode and the vertical electrode at the time of address discharge in the lighted cell is reduced, the intensity of address discharge is reduced, and the brightness of SF1 is lower than the brightness of SF2 by the amount of intensity reduction of address discharge. Lower.

  As described above, in the subfield configuration of the PDP apparatus of the third embodiment, the subfield having a lower luminance than the minimum luminance subfield having the sustain period is provided in two stages. Improves the ability to express

  According to the present invention, the display quality of the plasma display device can be improved, and the ability to express low luminance gradation, which is considered to be inferior to that of the CRT, is improved. Useful.

DESCRIPTION OF SYMBOLS 1 ... Front substrate 2 ... Back substrate 11 ... 1st (X) electrode 12 ... 2nd (Y) electrode 15 ... 3rd (address) electrode 30 ... Plasma display panel 31 ... Address driver 32 ... Y scan driver 33 ... Y sustain Circuit 34 ... X sustain circuit

Claims (3)

The first and second electrode groups arranged in parallel on the first substrate and the second substrate facing the first substrate intersect with the first and second electrode groups. And a third electrode group disposed on
One frame is composed of a plurality of subfields, and the plurality of subfields are:
An address period in which a scan pulse is applied to the second electrode group to select a cell to be lit and an address pulse is applied to the third electrode group, and the lighting display is applied to the first and second electrode groups A first subfield group comprising a plurality of subfields including a sustain period for applying a sustain pulse for
A second subfield group comprising a plurality of subfields having a luminance weight smaller than a subfield of the first subfield group, including the address period without the sustain period,
In the subfield of the second subfield side luminance weights is less included in the group, the first when applying the scan pulse and the address pulse to the second and third electrode groups of the address period A plasma display device characterized in that a voltage value applied to the electrode is set to a voltage lower than that of other subfields included in the second subfield group. The second sub-field the address period to the first you applied to the electrode group voltage values in the other sub-fields included in the group, the said address period in the first subfield group first The voltage value is the same as the voltage value applied to one electrode group,
Claim 1, characterized in that the second of said first electrode to that voltage values applied to groups in the address period in the subfield of luminance weight smaller side included in the subfield group, and a ground potential 2. The plasma display device according to 1. The second sub-field the address period to the first you applied to the electrode group voltage values in the other sub-fields included in the group, the said address period in the first subfield group first The voltage value is the same as the voltage value applied to one electrode group,
Wherein the second of said first electrode to that voltage values applied to groups in the address period in the subfield of luminance weight smaller side included in the sub-field group, non of the address period in the second electrode group The plasma display device according to claim 1, wherein the plasma display device has a selection potential.

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