JP5199941B2 - Voltage amplification circuit - Google Patents

Description

  The present invention relates to a voltage amplifier circuit, and more particularly to a voltage amplifier circuit that functions as a determination circuit that determines a transition of a voltage level of an input signal having a voltage amplitude level smaller than a CMOS level at high speed.

  As a determination circuit for determining the voltage level of an input signal having a voltage amplitude level smaller than the CMOS level, a determination circuit using a differential amplifier circuit as shown in FIG. 10 is generally used (see Patent Document 1 and Patent Document below). (See 2nd grade). In the circuit configuration shown in FIG. 10, the voltage level Vin of the input signal is compared with the reference voltage Vref, the differential voltage is amplified and output from the differential amplifier circuit, and the output voltage level is converted to the CMOS level voltage by the CMOS inverter circuit. Amplified further and output.

JP-A-9-186579 Japanese Patent Laid-Open No. 10-209844

  In the determination circuit shown in FIG. 10, when the voltage amplitude level of the input signal is very small, it is necessary to increase the amplification factor of the differential amplifier circuit. As a general method for increasing the amplification factor of the differential amplifier circuit, there are a first method for increasing the transconductance (gm) of the transistor in the input stage and a second method for increasing the output resistance of the amplifier stage. In the first method, it is necessary to increase the gate width of the transistor in the input stage. In the second method, it is necessary to increase the gate length in order to increase the output resistance of the transistor in the amplification stage. In any of the above methods, there is a problem that the transistor size of the input stage or the amplification stage becomes large and the transient response speed is lowered due to an increase in the parasitic capacitance of the transistor. In addition, an increase in the voltage amplitude of the output terminal (node X in FIG. 10) of the differential amplifier circuit also slows down the transient response of the output terminal, leading to a decrease in the transient response speed of the entire determination circuit. Become.

  As a method for suppressing the voltage amplitude of the output terminal (node X in FIG. 10) of the differential amplifier circuit, for example, using a MOSFET having a drain and a gate connected as a clamp element, the output terminal and ground voltage or the output terminal and power supply There is a method of interposing between the voltages. However, in the method of interposing the clamp element, if the clamp element is turned on before the voltage level of the output terminal reaches the input inversion level of the next stage CMOS inverter circuit, the transition time of the voltage level of the output terminal As a result, the reaction of the CMOS inverter circuit at the next stage is delayed. Also, if the threshold voltage for turning on the clamp element is increased to delay the turn-on timing, the input inversion level of the CMOS inverter circuit varies depending on the power supply voltage, so that the threshold voltage of the clamp element has a margin. As a result, the original voltage amplitude suppression effect is greatly impaired.

  The present invention has been made in view of a problem in a determination circuit for an input signal having a minute voltage amplitude using a differential amplifier circuit, and an object of the present invention is to detect a voltage level of an input signal having a voltage amplitude level smaller than a CMOS level. An object of the present invention is to provide a voltage amplifier circuit for determining a transition at high speed.

  In order to achieve the above object, a voltage amplifier circuit according to the present invention is a pre-stage configured using a MOSFET that amplifies a voltage change of an input signal with respect to a predetermined reference voltage and outputs a first output voltage from a first output terminal. A circuit unit and a rear circuit unit configured using a MOSFET that amplifies a voltage change of the first output voltage and outputs a second output voltage from a second output terminal, and the rear circuit unit includes a gate The first output terminal, the drain is the second output terminal, the source is a first transistor made of a MOSFET connected to the first power supply voltage, the gate and drain are the first output terminal, and the source is the second output. A second transistor made of a MOSFET of the same conductivity type as the first transistor connected to the output terminal, one end connected to the second power supply voltage, and the other end connected to the second output terminal, respectively. 1 and the current source circuit, that is configured with a the first feature.

  In addition to the first feature, the voltage amplifier circuit according to the present invention is configured such that, when the first transistor and the second transistor are N-channel MOSFETs, the second power supply voltage is based on the first power supply voltage. The second characteristic is that when the first transistor and the second transistor are P-channel MOSFETs, the second power supply voltage is a negative voltage with reference to the first power supply voltage. .

  Further, in the voltage amplifier circuit according to the present invention, in addition to the first or second feature, the front-stage circuit unit includes a differential amplifier circuit that amplifies a voltage difference between the predetermined reference voltage and the input signal. This is the third feature.

  Furthermore, in the voltage amplifier circuit according to the present invention, in addition to the first or second feature, the pre-stage circuit unit inputs the predetermined reference voltage to one of a source and a gate, and the input signal to the other. Is input, and the drain is connected to the first output terminal. The input transistor is formed of a MOSFET of the same conductivity type as the first transistor, one end is connected to the second power supply voltage, and the other end is connected to the first output terminal. The second feature is that the second current source circuit is configured.

  Furthermore, in the voltage amplifier circuit according to the present invention, in addition to any one of the features described above, the first current source circuit includes a drain connected to the second output terminal and a source connected to the second power supply voltage. A first output transistor comprising a transistor and a reverse conductivity type MOSFET, and a MOSFET of the same conductivity type as the first output transistor, the gate and drain of which are connected to the gate of the first output transistor and the source of which is connected to the second output terminal, respectively. A second output transistor comprising: a second bias circuit; a drain connected to a gate of the first output transistor; and a source connected to the first output terminal. A bypass transistor comprising a MOSFET of the same conductivity type as the first transistor, one end of the second power supply voltage and the other end of the first transistor; Further comprising a third current source circuit to the gate and respectively connected output transistors and fifth characteristic.

  According to the voltage amplifier circuit of the first feature, in the subsequent circuit section, the absolute value of the gate-source voltage of the first transistor is the absolute value of the gate-source voltage of the second transistor and the drain of the first transistor. • Sum of absolute values of source-to-source voltage. Therefore, when the first transistor transitions from the off-state to the on-state due to the transition of the first output voltage input from the front-stage circuit section to the subsequent-stage circuit section, the first transistor is always turned on. After the absolute value of the drain-source voltage is sufficiently lower than the absolute value of the gate-source voltage, the absolute value of the gate-source voltage of the second transistor exceeds the absolute value of the threshold voltage of the second transistor. Two transistors are turned on. That is, since the first transistor sufficiently transitions from the off state to the on state while the second transistor is in the off state, the first output voltage can transition at high speed without being affected by the second transistor. Further, when the second transistor is turned on, further transition of the first output voltage is suppressed, so that the first output voltage transitions in the reverse direction, causing the first transistor to transition from the on state to the off state. In this case, since the voltage amplitude of the first output voltage is suppressed, the first output voltage can transition at high speed in the reverse direction. Further, in the subsequent stage circuit portion of the present invention, since the first transistor transitions from the off state to the on state, voltage amplitude suppression for the first output voltage by the second transistor is automatically started. It is not necessary to adjust the voltage amplitude suppression start point of the first transistor, and a delay in transition time between on and off of the first transistor is avoided due to power supply voltage fluctuation. Therefore, even if the capacitive load parasitic on the first output terminal is large, the signal delay from the input of the input signal of the preceding circuit section to the second output terminal of the succeeding circuit section can be significantly suppressed. As a result, it is possible to provide a voltage amplifier circuit that functions as a determination circuit that determines a transition of the voltage level of an input signal having a voltage amplitude level smaller than the CMOS level at high speed.

  In addition, according to the voltage amplification circuit of the second feature, the voltage amplification circuit that exhibits the effects of the voltage amplification circuit of the first feature according to the conductivity type of the MOSFETs constituting the first transistor and the second transistor. Is specifically realized.

  Further, according to the voltage amplification circuit of the third feature, the voltage difference between the two input voltages of the predetermined reference voltage and the input signal voltage can be amplified at high speed by configuring the pre-stage circuit unit with a differential amplification circuit. A voltage amplification circuit is realized.

  Further, according to the voltage amplification circuit of the fourth feature, the input transistor is switched between the on state and the off state in a state where the voltage difference between the predetermined reference voltage and the input signal becomes the threshold voltage of the input transistor. When an input signal whose voltage changes slightly across the state is received, the pre-stage circuit section in which the first output voltage of the first output terminal changes greatly according to the on / off state change of the input transistor has a simple circuit configuration. A voltage amplifying circuit that can be realized and has the effect of the voltage amplifying circuit of the first feature is specifically realized.

  Further, according to the voltage amplifier circuit of the fifth feature, the first output transistor and the second output transistor in which the conductivity types of the first transistor and the second transistor are reversed are used as the first current source circuit of the subsequent circuit section. Since it is provided between the second output terminal and the second power supply voltage, a complementary push-pull circuit for driving the second output terminal is configured. Here, when the first transistor transitions from the off-state to the on-state due to the transition of the first output voltage input from the front-stage circuit section to the subsequent-stage circuit section, the bypass transistor transitions from the on-state to the off-state, Since the gate voltage of the output transistor makes a transition toward the second power supply voltage by the third current source circuit, the absolute value of the gate-source voltage of the first output transistor decreases and the first output transistor changes from the on state to the off state. Therefore, the voltage at the second output terminal can be sharply changed toward the first power supply voltage. Further, when the first transistor transitions from the on state to the off state, the first output voltage transitions toward the first power supply voltage. Therefore, the bypass transistor transitions from the off state to the on state, and the first output Since the gate voltage of the transistor transits toward the first output voltage via the bypass transistor, the absolute value of the gate-source voltage of the first output transistor decreases and the first output transistor changes from the off state to the on state. Therefore, the voltage at the second output terminal can be sharply changed toward the second power supply voltage. Accordingly, it is possible to prevent the voltage change at the second output terminal from slowing down when the capacitive load at the second output terminal is large, and the transient response characteristics of the entire circuit can be improved.

The circuit diagram which shows the circuit structure in 1st Embodiment of the voltage amplifier circuit which concerns on this invention. The circuit diagram which shows the circuit structure in 2nd Embodiment of the voltage amplifier circuit which concerns on this invention. The circuit diagram which shows the circuit structure in 3rd Embodiment of the voltage amplifier circuit which concerns on this invention. The circuit diagram which shows the circuit structure in 4th Embodiment of the voltage amplifier circuit which concerns on this invention. The circuit diagram which shows the circuit structure in another embodiment of 2nd Embodiment of the voltage amplifier circuit which concerns on this invention. The circuit diagram which shows the circuit structure in another embodiment of 1st Embodiment of the voltage amplifier circuit which concerns on this invention. The circuit diagram which shows the circuit structure in other another embodiment of 2nd Embodiment of the voltage amplifier circuit which concerns on this invention. The circuit diagram which shows the circuit structure in another embodiment of 3rd Embodiment of the voltage amplifier circuit which concerns on this invention. The circuit diagram which shows the circuit structure in another embodiment of 4th Embodiment of the voltage amplifier circuit which concerns on this invention. Circuit diagram showing a typical circuit configuration example of a determination circuit using a differential amplifier circuit of a conventional determination circuit

  An embodiment of a voltage amplifier circuit according to the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 shows a circuit configuration of the voltage amplifier circuit 1 in the first embodiment. The voltage amplifier circuit 1 includes two stages before and after the front circuit unit 10 and the rear circuit unit 20. The pre-stage circuit unit 10 is configured by a general differential amplifier circuit.

  The post-stage circuit unit 20 includes a first transistor M1 and a second transistor M2 made of an N-channel MOSFET, and a first current source circuit S1. The first transistor M1 has a gate that is the output node N1 (corresponding to the first output terminal) of the pre-stage circuit unit 10, a drain that is output node N2 (corresponds to the second output terminal) of the post-stage circuit unit 20, and a source that is the ground voltage. Each is connected to GND (corresponding to the first power supply voltage). The second transistor M2 has a gate and a drain connected to the output node N1, and a source connected to the output node N2. The first current source circuit S1 has one end connected to the positive power supply voltage Vcc (corresponding to the second power supply voltage) and the other end connected to the output node N2. The description that the transistor and the circuit are connected to the ground voltage GND and the power supply voltage Vcc specifically includes the ground voltage line provided in the circuit of the present invention and the ground voltage line for supplying the power supply voltage Vcc, It means that it is electrically connected to the power supply voltage line.

  The pre-stage circuit unit 10 includes a third transistor M3 and a fourth transistor M4 made of a pair of P-channel MOSFETs, a fifth transistor M5 and a sixth transistor M4 made of a pair of N-channel MOSFETs, and a second current source. A circuit S2 is provided. The third transistor M3 has an inverted input signal INB (corresponding to a predetermined reference voltage) input to the gate, a drain connected to the internal node N3, and a source connected to the internal node N4. The fourth transistor M4 has a gate receiving a non-inverted input signal IN (corresponding to an input signal), a drain connected to the output node N1, and a source connected to the internal node N4. The fifth transistor M5 has a gate and a drain connected to the internal node N3 and a source connected to the ground voltage GND. The sixth transistor M6 has a gate connected to the internal node N3, a drain connected to the output node N1, and a source connected to the ground voltage GND. The second current source circuit S2 has one end connected to the positive power supply voltage Vcc and the other end connected to the internal node N4.

  In the present embodiment, the first current source circuit S1 and the second current source circuit S2 are configured by, for example, a P-channel MOSFET in which the gate voltage is fixed at a predetermined voltage level. Configured to act as a source.

  In the pre-stage circuit unit 10, a current mirror circuit is configured by the fifth transistor M5 and the sixth transistor M6, and the current supplied from the second current source circuit S2 is input to the gates of the third transistor M3 and the fourth transistor M4. Since the voltage is distributed to the third transistor M3 and the fourth transistor M4 according to the voltage difference, the drain current of the fourth transistor M4 that increases the voltage V1 of the output node N1 and the sixth voltage that decreases the voltage V1 of the output node N1. The voltage V1 at the output node N1 changes due to the current difference in the drain current of the transistor M6. For example, the non-inverting input signal IN rises to a voltage level (V4−Vtp) lower than the voltage level V4 of the internal node N4 by the threshold voltage Vtp of the fourth transistor M4, and the inverting input signal INB has a lower voltage than that. If there is, the third transistor M3 is in an on state and the fourth transistor M4 is in a state close to an off state, so that the current supplied from the second current source circuit S2 flows through the third transistor M3, and the same amount of current flows. Since the current flows through the sixth transistor M6, the output node N1 is substantially reduced to the ground voltage GND. Conversely, when the non-inverted input signal IN becomes lower than the inverted input signal INB, the third transistor is used to distribute the current supplied from the second current source circuit S2 from the third transistor M3 to the fourth transistor M4. The bias condition of the third transistor M3 changes, the amount of current of the fourth transistor M4 increases, and the current of the sixth transistor M6 decreases so that the drain current of M3 decreases. If ignored, voltage V1 at output node N1 rises to near voltage level V4 at internal node N4.

  The post-stage circuit unit 20 operates as follows with respect to the voltage change of the output node N1. When the non-inverting input signal IN changes from the high voltage state to the low voltage state with respect to the inverting input signal INB and the voltage V1 of the output node N1 rises from the vicinity of the ground voltage GND, the first circuit section 20 Both the transistor M1 and the second transistor M2 are initially in the off state, and the voltage level V2 of the output node N2 rises to the power supply voltage Vcc via the first current source circuit S1. When the voltage level V1 of the output node N1 increases beyond the threshold voltage Vt1 of the first transistor M1, the first transistor M1 is turned on, and the voltage level V2 of the output node N2 decreases. Since the voltage level V1 of the output node N1 further increases and the voltage level V2 of the output node N2 decreases, the voltage V1 of the output node N1 is the sum of the voltage V2 of the output node N2 and the threshold voltage Vt2 of the second transistor M2 ( When V2 + Vt2) is exceeded, the second transistor M2 is turned on. When the voltage level V1 of the output node N1 further increases, the current supplied from the fourth transistor M4 of the pre-stage circuit unit 10 to the output node N1 flows to the second transistor M2, so that the voltage V1 of the output node N1 is the pre-stage circuit. The voltage increase stops in a state (upper limit value) where the drain currents of the fourth transistor M4 and the second transistor M2 are balanced without increasing to near the voltage level V4 of the internal node N4 of the unit 10. That is, the voltage amplitude of the voltage V1 at the output node N1 is suppressed by turning on the second transistor M2. By the way, if the back gate of the second transistor M2 is not connected to the source but is connected to the ground voltage GND, the potential of the back gate becomes a negative potential from the source, and the threshold voltage Vt2 is equal to the threshold voltage Vt1 of the first transistor M1. Since the voltage is slightly higher, the second transistor M2 is less likely to be turned on until the first transistor M1 is turned on and the voltage V1 of the output node N1 is sufficiently lowered.

  Next, when the non-inverting input signal IN changes from the low voltage state to the high voltage state with respect to the inverting input signal INB, and the voltage V1 of the output node N1 falls from the above-described upper limit value, the post-stage circuit unit 20 Both the first transistor M1 and the second transistor M2 are initially in the on state, and the voltage level V2 of the output node N2 is lowered to the vicinity of the ground voltage GND through the first transistor M1. Initially, the voltage level V1 of the output node N1 rapidly decreases from the upper limit value via both the fourth transistor M4 of the pre-stage circuit unit 10 and the second transistor M2 in the on state. As the voltage level V1 of the output node N1 decreases, the voltage between the gate and the source of the first transistor M1 decreases. Therefore, the voltage level V2 of the output node N2 starts to increase, and the voltage V1 of the output node N1 becomes equal to the output node N2. When the voltage V2 falls below the sum of the threshold voltage Vt2 of the second transistor M2 (V2 + Vt2), the second transistor M2 is turned off. Further, when the voltage level V1 of the output node N1 falls below the threshold voltage Vt1 of the first transistor M1, the first transistor M1 is turned off, and the voltage level V2 of the output node N2 further rises to the power supply voltage Vcc.

  As described above, since the voltage amplitude of the output node N1 is appropriately suppressed, the transition of the gate voltage of the first transistor M1 is slow in the subsequent circuit unit 20 without being greatly affected by the parasitic capacitance of the output node N1. In other words, the delay time from the change of the non-inverting input signal IN to the start of the switching operation between the on state and the off state of the first transistor M1 is shortened.

  In order to increase the speed without suppressing the voltage amplitude of the output node N1, in order to increase the voltage change of the output node N1, it is necessary to increase the transistor size of the pre-stage circuit unit 10. Since the capacity increases, the desired speedup cannot be easily realized. However, according to the circuit configuration of the present embodiment, the voltage change of the output node N1 is accelerated without increasing the transistor size of the differential amplifier circuit. Accordingly, the size of the transistors constituting the circuit of the present invention can be reduced, and the circuit area can be greatly reduced.

Second Embodiment
FIG. 2 shows a circuit configuration of the voltage amplifier circuit 2 in the second embodiment. The voltage amplification circuit 2 includes two stages before and after the front circuit unit 11 and the rear circuit unit 20. Unlike the first embodiment, the pre-stage circuit unit 11 is not composed of a differential amplifier circuit. Since the post-stage circuit unit 20 has the same circuit configuration as that of the first embodiment, a duplicate description is omitted.

  In the second embodiment, the pre-stage circuit unit 11 includes a seventh transistor M7 (corresponding to an input transistor) made of an N-channel MOSFET and a second current source circuit S2. In the seventh transistor M7, a predetermined reference voltage Vref is input to the gate, the input signal IN is input to the source, and the drain is connected to the output node N1 (corresponding to the first output terminal) of the pre-stage circuit unit 11. The second current source circuit S2 has one end connected to the positive power supply voltage Vcc (corresponding to the second power supply voltage) and the other end connected to the output node N1. As in the first embodiment, the second current source circuit S2 may be configured by, for example, a P-channel MOSFET whose gate voltage is fixed at a predetermined voltage level, but is not necessarily the same circuit configuration as the first embodiment. Not necessarily. The input signal IN may be input directly to the source of the seventh transistor M7, or may be input via a current limiting resistor or the like.

  In the first embodiment, the voltage of the non-inverted input signal IN and the voltage V1 of the output node N1 change in opposite phases in the pre-stage circuit section 10, but in the second embodiment, as described later, the pre-stage circuit section. 11, since the voltage VIN of the input signal IN and the voltage V1 of the output node N1 change in phase, the phase relationship between the input signal IN and the output node N2 is reversed between the second embodiment and the first embodiment. .

  The operation of the pre-stage circuit unit 11 will be briefly described. When the voltage level VIN of the input signal IN reaches the lower limit value of the voltage lower than the reference voltage Vref by the threshold voltage Vt7 of the seventh transistor M7 (Vref−Vt7), the seventh transistor M7 is turned on. Therefore, the voltage V1 at the output node N1 is directed toward the voltage level VIN of the input signal IN until the current supplied from the second current source circuit S2 and the drain current of the seventh transistor M7 are in equilibrium (lower limit value). Is falling. In the second embodiment, the current amount of the second current source circuit S2 and the seventh transistor M7 are set so that the lower limit value of the voltage V1 of the output node N1 is equal to or lower than the threshold voltage Vt1 of the first transistor M1 of the post-stage circuit unit 20. Transistor size and voltage amplitude of the input signal IN are set. From this state, when the voltage level VIN of the input signal IN rises, the voltage V1 of the output node N1 starts to rise similarly, and further, when the voltage level VIN of the input signal IN rises exceeding the voltage (Vref−Vt7). If the seventh transistor M7 is turned off and the operation of the post-stage circuit unit 20 is ignored, the voltage V1 at the output node N1 rises to the power supply voltage Vcc via the second current source circuit S2.

  However, as described above, in the post-stage circuit unit 20, when the voltage V1 of the output node N1 exceeds the sum (V2 + Vt2) of the voltage V2 of the output node N2 and the threshold voltage Vt2 of the second transistor M2, the second transistor M2 Turns on. When the voltage level V1 of the output node N1 further rises, the current supplied from the second current source circuit S2 of the pre-stage circuit unit 11 to the output node N1 flows to the second transistor M2, so that the voltage V1 of the output node N1 is The voltage increase stops in a state (upper limit value) where the current of the second current source circuit S2 and the drain current of the second transistor M2 are balanced without increasing to the power supply voltage Vcc. That is, the voltage amplitude of the voltage V1 at the output node N1 is suppressed by turning on the second transistor M2 as in the first embodiment. However, until the second transistor M2 is turned on, the voltage V1 of the output node N1 rises rapidly, so that the first transistor M1 is quickly turned on.

  Next, when the input signal IN decreases from the upper limit value of the voltage higher than the voltage (Vref−Vt7) toward the lower limit value, when the input signal IN falls below the voltage (Vref−Vt7), the seventh transistor M7 is turned on. The voltage V1 at the output node N1 decreases from the upper limit value toward the lower limit value. Here, since the upper limit value of the voltage V1 of the output node N1 is suppressed to be low, the voltage V1 of the output node N1 quickly decreases toward the lower limit value without being greatly affected by the parasitic capacitance of the output node N1. be able to.

<Third Embodiment>
FIG. 3 shows a circuit configuration of the voltage amplifier circuit 3 in the third embodiment. The voltage amplifying circuit 3 is composed of two stages of a front-stage circuit unit 10 and a rear-stage circuit unit 21. Since the pre-stage circuit unit 10 has the same circuit configuration as that of the first embodiment, a redundant description is omitted.

  In the first embodiment, the voltage increase at the output node N2 is governed by the first current source circuit S1. For this reason, when the capacitive load of the output node N2 of the post-stage circuit unit 20 is large, the rising speed of the voltage V2 of the output node N2 may be slow. As a result, the transient response delay from the change of the non-inverting input signal IN to the voltage change of the output node N2 becomes large. Conversely, if the amount of current in the first current source circuit S1 is increased in order to increase the rising speed of the voltage V2 at the output node N2, the falling speed of the voltage V2 at the output node N2 is decreased and the signal amplitude is narrowed. .

  In the third embodiment, the post-stage circuit unit 21 in which the drive of the output node N2 is a push-pull type is adopted, and the circuit configuration is configured to suppress the transient response delay even when the load capacity of the output node N2 is large.

  Specifically, the post-stage circuit unit 21 is a P-channel type in which the drain is connected to the output node N2 and the source is connected to the power supply voltage Vcc instead of the first current source circuit S1 in the post-stage circuit unit 20 of the first embodiment. An eighth transistor M8 (corresponding to the first output transistor) made of a MOSFET, and a ninth transistor M9 (the ninth transistor M9) made of a P-channel MOSFET having a gate and a drain connected to the gate of the eighth transistor M8 and a source connected to the output node N2. A tenth transistor M10 (corresponding to two output transistors), further comprising an N-channel MOSFET having a gate connected to a predetermined bias voltage Vb, a drain connected to the gate of the eighth transistor M8, and a source connected to the output node N1. Equivalent to a bypass transistor), one end is a positive power supply voltage Vcc, and the other end is an eighth. Configured to include a third current source circuit S3 for gate and respectively connected to transistor M8. The gate of the eighth transistor M8, the gate and drain of the ninth transistor M9, the drain of the tenth transistor M10, and the other end of the third current source circuit S3 are connected to each other to form an internal node N5. The third current source circuit S3 may be composed of, for example, a P-channel MOSFET in which the gate voltage is fixed at a predetermined voltage level, like the first current source circuit S1 and the second current source circuit S2. The circuit configuration is not necessarily the same as that of the first current source circuit S1 and the second current source circuit S2.

  In the post-stage circuit unit 21, a complementary push-pull type driving circuit is configured by the first transistor M1 made of an N-channel MOSFET and the eighth transistor M8 made of a P-channel MOSFET with respect to the output node N2. The second transistor M2 and the ninth transistor M9 also have a complementary symmetrical circuit configuration, and the ninth transistor M9 has a voltage amplitude suppression effect of the second transistor M2 with respect to the output node N1 with respect to the internal node N5. Has the same effect as. The tenth transistor M10 and the third current source circuit S3 constitute a level shift circuit, and the voltage level V1 of the output node N1 in which the voltage amplitude is suppressed is shifted to the positive power supply voltage Vcc side at the internal node N5. Further, the voltage amplitude is suppressed by the ninth transistor M9 and supplied to the gate of the eighth transistor M8. Therefore, the change in the voltage V1 at the output node N1 is transmitted to the internal node N5 at high speed, and the on / off state of the eighth transistor M8 is controlled.

  With the circuit configuration as shown in FIG. 3, the post-stage circuit unit 21 can quickly raise or lower the voltage V2 of the output node N2 while maintaining the effect of suppressing the voltage amplitude of the output node N1. .

  Specifically, when the voltage V1 of the output node N1 increases, the drain current of the tenth transistor M10 decreases and the current supplied from the third current source circuit S3 relatively increases, so that the voltage of the internal node N5 increases. V5 rises and the eighth transistor M8 is turned off. On the other hand, the first transistor M1 is turned on, draws current from the output node N2, and lowers the voltage V2 of the output node N2 to the level of the ground voltage GND. When the voltage V2 of the output node N2 becomes the ground voltage GND, the second transistor M2 is turned on, the output node N1 is in a state where the drain currents of the second transistor M2 and the fourth transistor M4 are balanced, and the voltage V1 at that time is Due to the effect of the diode-connected second transistor M2, the voltage stays higher than the ground voltage GND by about the threshold voltage Vt2 of the second transistor M2.

  Conversely, when the voltage V1 at the output node N1 falls, the first transistor M1 turns off, and at the same time, the drain current of the tenth transistor M10 increases, the voltage V5 at the internal node N5 is lowered, and the eighth transistor M8 turns on. It becomes a state. When the first transistor M1 is turned off and the eighth transistor M8 is turned on, the voltage V2 of the output node N2 rises to the power supply voltage Vcc level. As a result, the ninth transistor M9 is also turned on, and the internal node N5 is in a state where the drain currents of the ninth transistor M9 and the tenth transistor M10 and the current of the third current source circuit S3 are balanced, and the voltage V5 at that time is Due to the effect of the diode-connected ninth transistor M9, it stops at a voltage that has dropped from the power supply voltage Vcc by the threshold voltage of the ninth transistor M9.

<Fourth embodiment>
FIG. 4 shows a circuit configuration of the voltage amplifier circuit 4 in the fourth embodiment. The voltage amplifying circuit 4 is composed of two stages, a front-stage circuit unit 11 and a rear-stage circuit unit 21. The voltage amplification circuit 4 in the fourth embodiment is a circuit configuration in which the front-stage circuit unit 11 of the second embodiment and the rear-stage circuit unit 21 of the third embodiment are combined. The front-stage circuit unit 11 is the same as that of the second embodiment. Since the post-stage circuit unit 21 has the same circuit configuration as that of the third embodiment, a duplicate description is omitted.

  Next, another embodiment of the device of the present invention will be described.

  <1> In the second embodiment, the input signal IN is input to the source of the seventh transistor M7 in the pre-stage circuit unit 11. However, as shown in FIG. 5, the input signal IN is input to the gate of the seventh transistor M7. It is good also as composition to do. In this case, a predetermined reference voltage Vref is input to the source of the seventh transistor M7, but it may be the ground voltage GND.

  In the second embodiment, when the voltage level VIN of the input signal IN rises to a higher voltage side with a voltage (Vref−Vt7) lower than the reference voltage Vref by the threshold voltage Vt7 of the seventh transistor M7 as a boundary, the seventh transistor When M7 is turned off and then falls to a lower voltage side, the seventh transistor M7 is turned on. However, in another embodiment shown in FIG. 5, the voltage level VIN of the input signal IN is changed from the reference voltage Vref to the seventh transistor. When the voltage (Vref + Vt7) that is higher by the threshold voltage Vt7 of M7 becomes a boundary and rises to a higher voltage side, the seventh transistor M7 is turned on, and when the voltage is lowered to a lower voltage side, the seventh transistor M7 is turned off. That is, the basic operation is the same as that of the second embodiment, except that the relationship between the voltage level VIN of the input signal IN and the on / off state of the seventh transistor M7 is different between the second embodiment and this separate embodiment. , I will omit the duplicate explanation. A similar embodiment can be applied to the pre-stage circuit unit 11 of the fourth embodiment.

  In the second embodiment, the voltage VIN of the input signal IN and the voltage V1 of the output node N1 change in the same phase in the pre-stage circuit unit 11, but in the second embodiment, the voltage VIN of the input signal IN and the output node N1 Therefore, the phase relationship between the input signal IN and the output node N2 is reversed between the second embodiment and the second embodiment.

  <2> Further, in the first and second embodiments, the first transistor M1 and the second transistor M2 of the post-stage circuit unit 20 are configured by N-channel MOSFETs. As shown in FIG. 2, it may be composed of a P-channel MOSFET. In this case, the N-channel type is replaced with the P-channel type and the P-channel type is replaced with the N-channel type, and the power supply voltage Vcc and the ground voltage GND are exchanged with each other. . Thus, the power supply voltage Vcc corresponds to the first power supply voltage, and the ground voltage GND corresponds to the second power supply voltage that is a negative voltage with respect to the first power supply voltage. 6 and 7 show circuit configurations when the first transistor M1 and the second transistor M2 of the post-stage circuit unit 20 are configured by P-channel MOSFETs in the first and second embodiments, respectively. The same circuit elements and nodes as those in FIGS. 1 and 2 in the case where the first transistor M1 and the second transistor M2 are configured by N-channel MOSFETs are denoted by the same reference numerals.

  The operation of each embodiment is the same as that of each of the embodiments described above except that the direction of voltage change at each node is reversed.

  <3> Further, in the third and fourth embodiments, the first transistor M1, the second transistor M2, and the tenth transistor M10 of the post-stage circuit unit 20 are configured by N-channel MOSFETs, and the eighth transistor M8 and the 9 The case where the transistor M9 is composed of a P-channel MOSFET has been described. However, as shown in FIGS. 8 and 9, the conductivity type of each transistor is reversed and the power supply voltage Vcc and the ground voltage GND are exchanged with each other. However, the current direction of the third current source circuit S3 may be reversed. In this case, the N-channel type is replaced with the P-channel type and the P-channel type is replaced with the N-channel type, and the power supply voltage Vcc and the ground voltage GND are exchanged with each other. . Thus, the power supply voltage Vcc corresponds to the first power supply voltage, and the ground voltage GND corresponds to the second power supply voltage that is a negative voltage with respect to the first power supply voltage. FIGS. 8 and 9 show circuit configurations in the case where the conductivity types of the transistors M1, M2, M8, M9, and M10 of the post-stage circuit unit 20 are reversed in the third and fourth embodiments, respectively. 3 and 4 in the case where the first transistor M1, the second transistor M2, and the tenth transistor M10 are configured by N-channel MOSFETs, and the eighth transistor M8 and the ninth transistor M9 are configured by P-channel MOSFETs. The same circuit elements and nodes are denoted by the same reference numerals.

  The operation of each embodiment is the same as that of each of the embodiments described above except that the direction of voltage change at each node is reversed.

  The voltage amplifier circuit according to the present invention can be used for a determination circuit that determines a transition of a voltage level of an input signal whose voltage amplitude level is smaller than that of a CMOS level at high speed.

1-4: Voltage amplification circuit 10, 11: Pre-stage circuit unit 20, 11: Subsequent circuit unit GND: Ground voltage IN: Input signal, non-inverted input signal INB: Inverted input signal M1: First transistor M2: Second transistor M3 : Third transistor M4: Fourth transistor M5: Fifth transistor M6: Sixth transistor M7: Seventh transistor (input transistor)
M8: Eighth transistor (first output transistor)
M9: Ninth transistor (second output transistor)
M10: 10th transistor (bypass transistor)
N1: Output node (first output terminal) of the previous circuit section
N2: Output node (second output terminal) of the subsequent circuit section
N3, N4: Internal node of the previous circuit unit N5: Internal node of the subsequent circuit unit S1: First power supply circuit S2: Second power supply circuit S3: Third power supply circuit Vb: Bias voltage Vcc: Power supply voltage Vref: Reference voltage

Claims (5)

A pre-stage circuit unit configured by using a MOSFET that amplifies a voltage change of an input signal with respect to a predetermined reference voltage and outputs a first output voltage from a first output terminal, and amplifies the voltage change of the first output voltage. A post-stage circuit unit configured using a MOSFET that outputs the second output voltage from the second output terminal,
The latter stage circuit section is
A first transistor comprising a MOSFET having a gate connected to the first output terminal, a drain connected to the second output terminal, a source connected to a first power supply voltage, a gate and a drain connected to the first output terminal, and a source connected to the first output terminal; A second transistor comprising a MOSFET of the same conductivity type as the first transistor connected to the second output terminal; a first current source circuit having one end connected to the second power supply voltage and the other end connected to the second output terminal; And a voltage amplifying circuit comprising: When the first transistor and the second transistor are N-channel MOSFETs, the second power supply voltage is a positive voltage with reference to the first power supply voltage.
2. The voltage amplifier circuit according to claim 1, wherein when the first transistor and the second transistor are P-channel MOSFETs, the second power supply voltage is a negative voltage with respect to the first power supply voltage. .   The voltage amplifier circuit according to claim 1, wherein the pre-stage circuit unit includes a differential amplifier circuit that amplifies a voltage difference between the predetermined reference voltage and the input signal.   The pre-stage circuit unit has the same conductivity type as the first transistor in which the predetermined reference voltage is input to one of the source and the gate, the input signal is input to the other, and the drain is connected to the first output terminal. 2. An input transistor comprising a MOSFET, and a second current source circuit having one end connected to the second power supply voltage and the other end connected to the first output terminal, respectively. Or the voltage amplifier circuit of 2. The first current source circuit includes a first output transistor composed of a MOSFET having a conductivity opposite to that of the first transistor, the drain of which is connected to the second output terminal, and the source of which is connected to the second power supply voltage. A gate and a source of the first output transistor are configured to include a second output transistor made of a MOSFET of the same conductivity type as the first output transistor, each of which is connected to the second output terminal;
The post-stage circuit unit further includes a MOSFET having the same conductivity type as that of the first transistor whose gate is connected to a predetermined bias voltage, whose drain is connected to the gate of the first output transistor, and whose source is connected to the first output terminal. 5. The bypass transistor, and a third current source circuit having one end connected to the second power supply voltage and the other end connected to the gate of the first output transistor, respectively. The voltage amplification circuit described.

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