JP5198265B2 - 薄型可撓性基板の平坦な表面を形成する装置及び方法 - Google Patents
薄型可撓性基板の平坦な表面を形成する装置及び方法 Download PDFInfo
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- JP5198265B2 JP5198265B2 JP2008518412A JP2008518412A JP5198265B2 JP 5198265 B2 JP5198265 B2 JP 5198265B2 JP 2008518412 A JP2008518412 A JP 2008518412A JP 2008518412 A JP2008518412 A JP 2008518412A JP 5198265 B2 JP5198265 B2 JP 5198265B2
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
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- 241000018646 Pinus brutia Species 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
本明細書の全体に使用される用語及び/又は語句を、以下で簡単に定義する。「接続される」又は「結合される」という用語、及び関連する用語は、実用上の意味で使用するのであって、必ずしも直接的な接続又は結合に限られるわけではない。したがって、たとえば、2つのデバイスを、直接、あるいは1つ又は複数のデバイスを介して結合することができる。本明細書に記載する開示事項により、当業者は、上記の定義に基づいて接続又は結合が行われる多くの方法を理解するであろう。
Claims (20)
- 平坦な基板の表面を形成する装置であって、前記装置が、
複数のアパーチャを有する上部プレートと、
間に隆起部分を形成するチャネルネットワークを有する下部プレートであって、各々の隆起部分が、前記上部プレートのアパーチャと対向するように配置される下部プレートと、
前記上部プレートと前記下部プレートとの間の中間構造であって、前記下部プレート上に位置する前記チャネルネットワークと嵌合する隆起部分を備える中間構造と、
前記中間構造と前記下部プレートとの間に配置された可撓性基板とを備え、
前記上部プレートが、前記中間構造上に前記下部プレート方向に下方に圧迫されて、前記可撓性基板の部分が、前記下部プレートの前記隆起部分上で伸張する装置。 - 前記上部プレートが、主にアルミニウムから構成される請求項1に記載の装置。
- 間に隆起部分を形成する前記チャネルネットワークが、前記下部プレート上に垂直方向及び水平方向に配置される請求項1に記載の装置。
- 前記可撓性基板が、ポリイミド、液晶ポリマー(LCP)、又はポリテトラフルオロエチレン(EPTFE)から成る群から選択される材料から構成される請求項1に記載の装置。
- 前記可撓性基板の厚さが.5mm〜1mmの範囲である請求項1に記載の装置。
- 前記可撓性基板が複数の層を含む請求項1に記載の装置。
- 前記可撓性基板が、前記可撓性基板に接合される構成要素の集合に基づくカスタムデザインを有する請求項1に記載の装置。
- 前記上部プレート、中間構造、及び下部プレートの各々が、前記上部プレート、中間構造、及び下部プレートを整列させるための複数のねじ孔を有する請求項1に記載の装置。
- 前記下部プレートの前記隆起部分が、垂直方向及び水平方向の少なくともいずれか一方の方向において整列していない請求項1に記載の装置。
- 前記上部プレート、中間構造、下部プレート、及び可撓性基板からなる組み立てられた固定具の厚さが、1.27〜25.4mm(0.05〜1インチ)の範囲である請求項1に記載の装置。
- 前記中間構造が前記可撓性基板と一体化して、前記可撓性基板用のキャリアを形成する請求項1に記載の装置。
- 前記可撓性基板用のキャリアの厚さが0.381〜3.18mm(0.015〜0.125インチ)である請求項11に記載の装置。
- 前記キャリアが、主に強化ガラス積層板から構成される請求項11に記載の装置。
- 平坦な基板の表面を形成する方法であって、
可撓性基板をフレームと下部プレートとの間に整列させるステップであって、前記下部プレートが、間にチャネルを有する1つ又は複数の隆起部分を備え、前記フレームが、前記下部プレートの前記隆起部分に面する開口部を含むステップと、
前記可撓性基板を前記フレームと前記下部プレートとの間に圧迫するステップであって、圧迫の結果、前記フレームの開口部が、前記下部プレートの前記隆起部分と嵌合することによって、前記下部プレートの前記隆起部分全体に前記可撓性基板の1つ又は複数の部分が伸張するステップとを含む方法。 - 前記圧迫するステップが、
上部プレートをフレーム上に整列させるステップであって、前記上部プレートが、前記フレームの前記開口部と整列する1つ又は複数の開口部を有するステップと、
前記上部プレートを基板組立体を形成するフレーム上に下方に圧迫するステップとを含む請求項14に記載の方法。 - 前記上部プレートの1つ又は複数の開口部を通して、フラックス又は導電性媒体を可撓性基板上に蒸着するステップと、
前記上部プレートの1つ又は複数の関連する開口部を通して、1つ又は複数のデバイスを前記基板組立体の前記可撓性基板上に配置するステップと、
はんだを使用して、構成要素のデバイスの端子を前記可撓性基板の伸張部分に取り付けるステップと、
取り付けられた構成要素を含む基板組立体を加熱して、1つ又は複数の組み立てられた構成要素を形成するステップとをさらに含む請求項15に記載の方法。 - 前記1つ又は複数の組み立てられた構成要素を分離するステップをさらに含む請求項16に記載の方法。
- 前記導電性媒体がはんだペーストである請求項16に記載の方法。
- 前記デバイスの端子がはんだバンプである請求項16に記載の方法。
- 基板組立体を加熱するステップの後にアンダーフィル又はオーバーモールドの化合物を蒸着するステップと、
前記アンダーフィル又はオーバーモールドの化合物を硬化させるステップとをさらに含む請求項16に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/166,461 | 2005-06-24 | ||
US11/166,461 US7226821B2 (en) | 2005-06-24 | 2005-06-24 | Flip chip die assembly using thin flexible substrates |
PCT/US2006/024399 WO2007002346A1 (en) | 2005-06-24 | 2006-06-21 | Flip chip die assembly using thin flexible substrates |
Publications (3)
Publication Number | Publication Date |
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JP2008544554A JP2008544554A (ja) | 2008-12-04 |
JP2008544554A5 JP2008544554A5 (ja) | 2009-07-09 |
JP5198265B2 true JP5198265B2 (ja) | 2013-05-15 |
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Application Number | Title | Priority Date | Filing Date |
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JP2008518412A Expired - Fee Related JP5198265B2 (ja) | 2005-06-24 | 2006-06-21 | 薄型可撓性基板の平坦な表面を形成する装置及び方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7226821B2 (ja) |
EP (1) | EP1894239B1 (ja) |
JP (1) | JP5198265B2 (ja) |
WO (1) | WO2007002346A1 (ja) |
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US9899330B2 (en) * | 2014-10-03 | 2018-02-20 | Mc10, Inc. | Flexible electronic circuits with embedded integrated circuit die |
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2005
- 2005-06-24 US US11/166,461 patent/US7226821B2/en not_active Expired - Fee Related
-
2006
- 2006-06-21 WO PCT/US2006/024399 patent/WO2007002346A1/en active Application Filing
- 2006-06-21 JP JP2008518412A patent/JP5198265B2/ja not_active Expired - Fee Related
- 2006-06-21 EP EP06773810A patent/EP1894239B1/en not_active Not-in-force
- 2006-08-15 US US11/464,779 patent/US7497911B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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WO2007002346A1 (en) | 2007-01-04 |
JP2008544554A (ja) | 2008-12-04 |
US20060290007A1 (en) | 2006-12-28 |
US7497911B2 (en) | 2009-03-03 |
US7226821B2 (en) | 2007-06-05 |
EP1894239A1 (en) | 2008-03-05 |
EP1894239B1 (en) | 2012-08-01 |
US20060292756A1 (en) | 2006-12-28 |
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