JP5197873B2 - Liquid crystal display - Google Patents

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  Liquid crystal display devices are utilized in various fields as display devices for OA equipment such as personal computers and televisions, taking advantage of features such as light weight, thinness, and low power consumption. In recent years, liquid crystal display devices are also used as mobile terminal devices such as mobile phones, display devices such as car navigation devices and game machines.

  In such a liquid crystal display device, there are increasing demands such as an improvement in image definition accompanying an increase in the amount of information, an improvement in display speed for moving images, and a wide viewing angle. Along with miniaturization of a TFT (Thin Film Transistor) array structure, as liquid crystal modes satisfying these requirements, an OCB (Optically Compensated Bend) method using a nematic liquid crystal, a VAN (Vertical Aligned Nematic) method, and a HAN (Hybrid Aid) method are used. Π arrangement method, IPS (In-Plane Switching) method, FFS (Fringe Field Switching) method and the like have been proposed.

  In particular, the FFS method has already been adopted in a wide field as a liquid crystal display mode that realizes a high contrast, a wide viewing angle, and a high transmittance. A characteristic configuration in the FFS system is that two types of transparent electrodes facing each other with an insulating layer interposed therebetween are provided on the same substrate, and a slit pattern is provided on the upper layer electrode. The orientation of the liquid crystal molecules is controlled by controlling the electric field formed between the two types of transparent electrodes.

JP 2000-10110 A

  An object of the present embodiment is to provide a liquid crystal display device with good display quality.

According to this embodiment,
A first non-linear first line formed between the first gate line and the second gate line, and between the first gate line and the second gate line and at a first distance from the first gate line. A common line including a second edge formed at a second distance shorter than the first distance from one edge and the second gate line, and disposed between the first gate line and the second gate line. And a first electrode in contact with the common wiring; an insulating film disposed on the first electrode; and a first electrode of the common wiring disposed on the insulating film and facing the first electrode. A first substrate including a second electrode extending directly above the edge and having a slit; a second substrate facing the first substrate; and between the first substrate and the second substrate And a liquid crystal layer held in the The liquid crystal display device is provided, characterized in that.

According to this embodiment,
An insulating substrate; first and second gate wirings disposed on the insulating substrate; and the first and second gate wirings disposed on the insulating substrate between the first gate wiring and the second gate wiring. A first end face formed at a first distance from the first gate wiring and inclined at a first angle with respect to the insulating substrate and a second distance shorter than the first distance from the second gate wiring are formed. A common line including a second end face inclined at a second angle larger than the first angle with respect to the insulating substrate, and the first wiring line and the second gate wiring line disposed on the insulating substrate. And a first electrode in contact with the common wiring; an insulating film disposed on the first electrode; and a first end of the common wiring disposed on the insulating film and facing the first electrode. A second substrate extending directly above and having a slit formed thereon, a second substrate facing the first substrate, and between the first substrate and the second substrate There is provided a liquid crystal display device comprising a held liquid crystal layer.

According to this embodiment,
A gate wiring formed along the first direction, a source wiring formed along a second direction orthogonal to the first direction, and a third direction intersecting the first direction and the second direction. A common wire formed in contact with the common wire, an insulating film disposed on the first electrode, a common electrode disposed on the insulating film and facing the first electrode and the common electrode. A first substrate including a second electrode extending directly above the wiring and having a slit formed thereon; a second substrate facing the first substrate; and between the first substrate and the second substrate And a liquid crystal layer held on the liquid crystal display device.

According to this embodiment,
A gate wiring formed along the first direction, a source wiring formed along a second direction orthogonal to the first direction, and a first wiring formed from the gate wiring along the first direction. A common wiring including a first wiring portion formed at a distance and a second wiring portion connected to the first wiring portion and formed at a second distance longer than the first distance from the gate wiring; A first electrode in contact with a common wiring; an insulating film disposed on the first electrode; a first wiring portion disposed on the insulating film and facing the first electrode; A first substrate including a second electrode extending directly above the second wiring portion and having a slit; a second substrate facing the first substrate; the first substrate and the second substrate; A liquid crystal layer held between The liquid crystal display device is provided, characterized and.

FIG. 1 is a plan view schematically showing the configuration of the liquid crystal display device according to the present embodiment. FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel shown in FIG. FIG. 3 is a schematic plan view of a first configuration example of the pixel structure of the array substrate shown in FIG. 2 as viewed from the counter substrate side. FIG. 4 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel in which the pixels shown in FIG. 3 are cut. FIG. 5 is a schematic plan view of a second configuration example of the pixel structure of the array substrate shown in FIG. 2 as viewed from the counter substrate side. FIG. 6 is a schematic plan view of a third configuration example of the pixel structure in the array substrate shown in FIG. 2 as viewed from the counter substrate side. FIG. 7 is a schematic cross-sectional view of the common wiring shown in FIG. FIG. 8 is a schematic plan view of a fourth configuration example of the pixel structure of the array substrate shown in FIG. 2 as viewed from the counter substrate side. FIG. 9 is a schematic plan view of a fifth configuration example of the pixel structure of the array substrate shown in FIG. 2 as viewed from the counter substrate side.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a plan view schematically showing a configuration of a liquid crystal display device 1 in the present embodiment.

  That is, the liquid crystal display device 1 includes an active matrix type liquid crystal display panel LPN, a drive IC chip 2 connected to the liquid crystal display panel LPN, a flexible wiring board 3, and the like.

  The liquid crystal display panel LPN is held between an array substrate AR as a first substrate, a counter substrate CT as a second substrate disposed to face the array substrate AR, and the array substrate AR and the counter substrate CT. And a liquid crystal layer (not shown). The array substrate AR and the counter substrate CT are bonded together by a seal material SE. A liquid crystal layer (not shown) is held inside the cell gap formed between the array substrate AR and the counter substrate CT and surrounded by the sealing material SE. For example, the seal material SE is formed in a substantially rectangular frame shape between the array substrate AR and the counter substrate CT. Such a sealing material SE is formed of, for example, a resin material.

  Such a liquid crystal display panel LPN includes a substantially rectangular active area ACT for displaying an image on the inner side surrounded by the seal material SE. This active area ACT is composed of a plurality of pixels PX arranged in an m × n matrix (where m and n are positive integers). The driving IC chip 2 and the flexible wiring board 3 are mounted on the array substrate AR in the peripheral area PRP outside the active area ACT.

  FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel LPN shown in FIG. Here, the array substrate AR of the liquid crystal display panel LPN includes a first electrode (or may be referred to as a lower electrode or a common electrode) E1 and a second electrode (or may be referred to as an upper electrode or a pixel electrode) E2. Liquid crystal molecules constituting the liquid crystal layer LQ mainly using a lateral electric field (that is, an electric field substantially parallel to the main surface of the substrate) formed between the first electrode E1 and the second electrode E2. A configuration to which a switching FFS mode liquid crystal mode is applied will be described.

  The array substrate AR includes n gate wirings G (G1 to Gn) and n common wirings C (C1 to Cn) formed along the first direction X in the active area ACT, respectively. M source lines S (S1 to Sm) formed along a substantially orthogonal second direction Y, switching elements SW arranged in each pixel PX and electrically connected to the gate lines G and the source lines S, A first electrode E1 disposed in each pixel PX and electrically connected to the common wiring C, a second electrode E2 disposed in each pixel PX and facing the first electrode and electrically connected to the switching element SW, etc. I have. For example, the storage capacitor Cs is formed between the first electrode E1 and the second electrode E2. The liquid crystal layer LQ is interposed between the first electrode E1 and the second electrode E2.

  Each gate line G is drawn outside the active area ACT and is connected to the first drive circuit GD. Each source line S is drawn outside the active area ACT and connected to the second drive circuit SD. Each common line C is drawn outside the active area ACT and connected to the third drive circuit CD. The first drive circuit GD, the second drive circuit SD, and the third drive circuit CD are formed on the array substrate AR and connected to the drive IC chip 2.

  In the illustrated example, the drive IC chip 2 is mounted on the array substrate AR outside the active area ACT of the liquid crystal display panel LPN. In addition, illustration of a flexible wiring board is abbreviate | omitted and the terminal T for connecting a flexible wiring board is formed in array board | substrate AR. These terminals T are connected to the driving IC chip 2 through various wirings.

  FIG. 3 is a schematic plan view of a first configuration example of the structure of the pixel PX in the array substrate AR shown in FIG. 2 as viewed from the counter substrate CT side.

  The first gate line GA and the second gate line GB are formed in a substantially linear shape along the first direction X. The source line S is formed in a substantially linear shape along the second direction Y. Note that a switching element electrically connected to the first gate line GA and the source line S is disposed in the vicinity of the intersection between the first gate line GA and the source line S. The illustration is omitted.

  The common line C is disposed between the first gate line GA and the second gate line GB, and is separated from the first gate line GA and the second gate line GB. Moreover, the common wiring C is unevenly distributed on the second gate wiring GB side between the first gate wiring GA and the second gate wiring GB (that is, the common wiring C is close to the second gate wiring GB). )

  Such a common line C includes a first edge ED1 that faces the first gate line GA and a second edge ED2 that faces the second gate line GB. The first edge ED1 is formed at a first distance D1 from the first gate line GA. The second edge ED2 is formed at a second distance D2 that is shorter than the first distance D1 from the second gate line GB.

  The planar shape of the first edge ED1 and the second edge ED2 is asymmetric. That is, the first edge ED1 is non-linear, and the second edge ED2 is substantially straight. In the illustrated example, the first edge ED1 is formed in a comb shape. For this reason, the length of the first edge ED1 is longer than the length of the second edge ED2.

  The first electrode E1 is formed corresponding to each pixel PX. In the illustrated example, the first electrode E1 is formed in a substantially rectangular shape. The first electrode E1 is disposed between the first gate line GA and the second gate line GB, and is separated from the first gate line GA and the second gate line GB. The first electrode E1 is in contact with the common wiring C.

  The second electrode E2 is formed corresponding to each pixel PX. In the illustrated example, the second electrode E2 is formed in a substantially rectangular shape. The second electrode E2 is disposed above the first electrode E1 and faces the first electrode. Further, the second electrode E2 extends immediately above the first edge ED1 of the common wiring C. In the illustrated example, the second electrode E2 passes immediately above the common wiring C, extends directly above the first edge ED1 and the second edge ED2, and further extends directly above the second gate wiring GB. ing.

  A plurality of slits SL are formed in the second electrode E2. In the illustrated example, the slits SL are parallel to each other and extend substantially linearly in a direction intersecting the first direction X and the second direction Y. That is, the extending direction of the slit SL is a direction intersecting the common wiring C and the source wiring S. These slits SL are formed above the first electrode E1. Many slits SL are located immediately between the first gate line GA and the common line C. Further, a part of the slit SL is formed in the vicinity immediately above the first edge ED1 of the common wiring C. Note that no slit SL is formed near the second edge ED2.

  Such a second electrode E2 is electrically connected to a switching element (not shown).

  FIG. 4 is a diagram schematically showing a cross-sectional structure of the liquid crystal display panel LPN in which the pixel PX shown in FIG. 3 is cut.

  That is, the array substrate AR is formed by using a first insulating substrate 20 having a light transmission property such as a glass plate. The array substrate AR includes a switching element SW on the inner surface of the first insulating substrate 20 (that is, the surface facing the counter substrate CT). The switching element SW shown here is a bottom-gate thin film transistor (TFT). The switching element SW shown here is a bottom-gate thin film transistor and includes a semiconductor layer SC formed of amorphous silicon. However, the configuration of the switching element SW is not limited to this example. For example, the switching element SW may be a top gate type thin film transistor or may include a semiconductor layer SC formed of polysilicon.

  The gate electrode WG of the switching element SW is disposed on the first insulating substrate 20. The gate electrode WG is electrically connected to the first gate line GA. In the illustrated example, the gate electrode WG is formed integrally with the first gate line GA. Further, the common wiring C and the second gate wiring GB are also disposed on the first insulating substrate 20. The gate electrode WG, the first gate line GA, the second gate line GB, and the common line C are formed of the same conductive material and can be formed in the same process.

  The first electrode E1 is disposed on the first insulating substrate 20. The first electrode E1 is located between the first gate line GA (or gate electrode WG) and the second gate line GB, and is in contact with the common line C. The first electrode E1 is formed of a light-transmitting conductive material, for example, a transparent oxide conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

  The gate electrode WG, the first gate line GA, the second gate line GB, the common line C, and the first electrode E1 are covered with a first interlayer insulating film 21. The first interlayer insulating film 21 is also disposed on the first insulating substrate 20.

  The semiconductor layer SC of the switching element SW is disposed on the first interlayer insulating film 21. The semiconductor layer SC is located immediately above the gate electrode WG. The source electrode WS and the drain electrode WD of the switching element SW are disposed on the first interlayer insulating film 21. A part of each of the source electrode WS and the drain electrode WD is in contact with the semiconductor layer SC. The source electrode WS is electrically connected to the source line S. In the illustrated example, the source electrode WS is formed integrally with the source line S.

  The gate electrode WG, the source electrode WS, the drain electrode WD, the first gate wiring GA, the second gate wiring GB, the common wiring C, the source wiring S, etc. of the switching element SW are, for example, molybdenum, aluminum, tungsten, titanium. Formed of a conductive material.

  The source electrode WS and the drain electrode WD are covered with the second interlayer insulating film 22. The second interlayer insulating film 22 is also disposed on the first interlayer insulating film 21. The first interlayer insulating film 21 and the second interlayer insulating film 22 are made of an inorganic material such as silicon nitride (SiN).

  The second electrode E <b> 2 is disposed on the second interlayer insulating film 22. The second electrode E2 is in contact with the drain electrode WD through a contact hole that penetrates the second interlayer insulating film 22. The second electrode E2 is also formed of a transparent oxide conductive material such as ITO or IZO, like the first electrode E1.

  Such a second electrode E2 faces the first electrode E1 via the first interlayer insulating film 21 and the second interlayer insulating film 22. That is, the second electrode E2 extends immediately above the common wiring C including the first edge ED1 and the second edge ED2. Further, the second electrode E2 also extends directly above the second gate line GB. The second electrode E2 has a slit SL that faces the first electrode E1, but the illustration of the slit SL is omitted here. The second electrode E2 and the second interlayer insulating film 22 are covered with the first alignment film 23.

  On the other hand, the counter substrate CT is formed using a second insulating substrate 30 having optical transparency such as a glass plate. The counter substrate CT includes, on the inner surface of the second insulating substrate 30 (that is, the surface facing the array substrate AR), a black matrix 31 for partitioning each pixel PX, and a color filter 32 disposed in each pixel PX. ing.

  The black matrix 31 is disposed on the second insulating substrate 30 and is located immediately above the wiring portions such as the gate wiring G and the source wiring S provided on the array substrate AR and the switching element SW. Such a black matrix 31 is formed in a lattice shape or a stripe shape. The black matrix 31 is made of, for example, a black-colored resin material or a light shielding metal material such as chromium (Cr).

  The color filter 32 is disposed on the second insulating substrate 30. A part of the color filter 32 is stacked on the black matrix 31. Although not described in detail, such a color filter 32 is arranged corresponding to a red color filter arranged corresponding to a red pixel, a blue color filter arranged corresponding to a blue pixel, and a green pixel. A green color filter is included. These red color filter, blue color filter, and green color filter are formed of, for example, resin materials colored in respective colors.

  The color filter 32 is covered with a second alignment film 33. The first alignment film 23 and the second alignment film 33 are formed of, for example, polyimide that exhibits horizontal alignment. The first alignment film 23 and the second alignment film 33 are rubbed in a direction substantially parallel to the direction in which the slit SL extends. Note that the rubbing direction of the first alignment film 23 and the rubbing direction of the second alignment film 33 are opposite to each other (directions different by 180 ° in the plane).

  In the liquid crystal mode using the lateral electric field as described above, it is desirable that the surface of the counter substrate CT in contact with the liquid crystal layer LQ is flat, and the counter substrate CT further includes the black matrix 31 and the color filter 32, An overcoat layer may be provided between the second alignment film 33 and the second alignment film 33. Such an overcoat layer is formed of, for example, a transparent resin material.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film 23 and the second alignment film 33 face each other. At this time, a spacer (not shown) (for example, a columnar spacer formed integrally with the array substrate AR or the counter substrate CT by a resin material) is disposed between the array substrate AR and the counter substrate CT, and thereby a predetermined number Cell gaps are formed. The array substrate AR and the counter substrate CT are bonded together with a sealing material (not shown) in a state where a predetermined cell gap is formed.

  The liquid crystal layer LQ is composed of a liquid crystal material having a positive dielectric anisotropy enclosed in a cell gap formed between the first alignment film 23 of the array substrate AR and the second alignment film 33 of the counter substrate CT. Has been.

  A first polarizing plate (not shown) is disposed on one outer surface of the liquid crystal display panel LPN, that is, the outer surface of the first insulating substrate 20 constituting the array substrate AR. Further, on the other outer surface of the liquid crystal display panel LPN, that is, the outer surface of the second insulating substrate 30 constituting the counter substrate CT, a second polarizing plate, a retardation plate, and the like (not shown) are arranged. The polarization axis of the first polarizing plate is orthogonal to the polarization axis of the second polarizing plate.

  In the FFS method, in the second electrode E2 in which the slit SL is formed, the area of the remaining portion other than the slit SL cannot be sufficiently secured, and particularly in the portion overlapping the lower layer wiring, the second electrode E2 is caused by the step. May be interrupted. When such a problem occurs, a potential cannot be supplied to a part of the second electrode E2, so that the pixel region is not only low in luminance but also affected by the gate wiring potential and a pixel region that is difficult to receive. Will be connected with a high resistance, causing burn-in.

  In the present embodiment, since the second electrode E2 having the slit SL extends immediately above the common wiring C, the second electrode E2 is disposed over the step formed due to the common wiring C. In the example shown in FIG. 4, for example, when the second electrode E <b> 2 is interrupted near the first edge ED <b> 1 of the common wiring C, the first edge from the first gate wiring GA to the first edge of the second electrode E <b> 2. While it is electrically connected to the switching element SW up to the vicinity of ED1, the common wiring C to the vicinity of the second gate wiring GB are in a floating state.

  Therefore, in the above example, the common line C has the substantially straight second edge ED2 on the second gate line GB side, while the non-linear first edge ED1 on the first gate line GA side. have. A first electrode E1, a first interlayer insulating film 21, and a second interlayer insulating film 22 are stacked on the common wiring C including the first edge ED1 and the second edge ED2, respectively.

  The surface 22A of the second interlayer insulating film 22 serving as the base of the second electrode E2 includes slopes SS1 and SS2 corresponding to the shapes of the first edge ED1 and the second edge ED2. Since the length of the first edge ED1 is longer than the length of the second edge ED2, the slope SS1 formed above the first edge ED1 is in a gentler order than the slope SS2 formed above the second edge ED2. Tapered shape. That is, the slope SS1 is gentler than the slope SS2.

  For this reason, the second electrode E2 disposed on the surface 22A of the second interlayer insulating film 22 tends to be interrupted on a steep slope, but the slope SS1 formed near the top of the first edge ED1 is a gentle slope. Therefore, it is formed over the slope SS1. Therefore, in the second electrode E2, even when the slit SL is formed near the upper portion of the first edge ED and the remaining area other than the slit SL is relatively small, the discontinuity of the second electrode E2 is suppressed. Is possible.

  Thus, by suppressing the discontinuity of the second electrode E2, by applying an electric field between the first electrode E1 and the second electrode E2, it is possible to suppress the occurrence of display unevenness and image sticking, It is possible to achieve a good display quality with high transmittance, brightness, and wide viewing angle.

  In the vicinity of the upper portion of the second edge ED2, no slit SL is formed in the second electrode E2, so that even if the slope SS2 is steep, the second electrode E2 is less likely to be interrupted. However, when the slit SL is also formed near the upper portion of the second edge ED2, the second edge ED2 is non-linear like the first edge ED1 in order to suppress the interruption of the second electrode E2. It is desirable to be formed.

  As described above, in order to suppress the discontinuity of the second electrode E2, it is effective to set the edge length of the lower layer wiring that overlaps the second electrode E2 to be sufficiently long. However, the aperture ratio may be reduced. There is a possibility that the variation in the aperture ratio may be enlarged. According to the inventor's study, it has been confirmed that it is desirable to form a non-linear shape so that the wiring length is about 1.1 to 2.0 times the wiring length of the straight edge.

  FIG. 5 is a schematic plan view of a second configuration example of the structure of the pixel PX in the array substrate AR shown in FIG. 2 as viewed from the counter substrate CT side.

  The second configuration example is the same as the first configuration example shown in FIG. 3 in that the first edge ED1 of the common wiring C is non-linear, but the shape is different. That is, in the second configuration example, the common wiring C has the first protruding portion CV1 and the second protruding portion CV2 protruding to the first gate wiring GA side, and forms a non-linear first edge ED1. Yes.

  Also in the second configuration example to which the common wiring C having such a shape is applied, the edge length of the first edge ED1 can be increased. In particular, the edges of the first protrusion CV1 and the second protrusion CV2 do not overlap the slit SL in most parts. For this reason, it is possible to secure a sufficiently large area of the remaining portion other than the slit SL, and it is possible to suppress the discontinuity of the second electrode E2 as in the first configuration example.

  FIG. 6 is a schematic plan view of a third configuration example of the structure of the pixel PX in the array substrate AR shown in FIG. 2 as viewed from the counter substrate CT side.

  Compared with the first configuration example shown in FIG. 3, the third configuration example has a first end surface ES1 where the common wiring C faces the first gate wiring GA and a second end surface ES2 which faces the second gate wiring GB. The first end face ES1 and the second end face ES2 are different in that they are asymmetrical. The first end surface ES1 is formed at a first distance D1 from the first gate line GA. The second end surface ES2 is formed at a second distance D2 that is shorter than the first distance D1 from the second gate line GB.

  FIG. 7 is a schematic cross-sectional view of the array substrate AR including the common wiring C shown in FIG. FIG. 7 shows only the configuration necessary for the description.

  In the third configuration example, the first end surface ES1 and the second end surface ES2 are asymmetric in cross-sectional shape. That is, the first end surface ES1 is a gentle slope that is inclined with respect to the first insulating substrate 20 at the first angle θ1. The second end surface ES2 is a steep slope that is inclined with respect to the first insulating substrate 20 at a second angle θ2 that is larger than the first angle θ1.

  Between the common wiring C including the first end surface ES1 and the second end surface ES2 and the second electrode E2, the first electrode E1, the first interlayer insulating film 21, and the second interlayer insulating film 22 are stacked. Has been. Regarding the surface 22A of the second interlayer insulating film 22, a slope SS1 is formed above the first end face ES1, and a slope SS2 is formed above the second end face ES2. The slope SS1 formed above the first end face ES1 has a gentler forward tapered shape than the slope SS2 formed above the second end face ES2. That is, the slope SS1 is gentler than the slope SS2.

  For this reason, the area where the second electrode E2 overlaps above the first end face ES1 is larger than the area where the second electrode E2 overlaps above the second end face ES2. Therefore, as in the first configuration example, it is possible to suppress the disconnection of the second electrode E2.

  In addition, when the slit SL is also formed near the upper end of the second end surface ES2, the second end surface ES2 is the first end surface in order to suppress the discontinuity of the second electrode E2 above the second end surface ES2. It is desirable to form a gentle slope like ES1.

  As described above, in order to suppress the discontinuity of the second electrode E2, it is effective to take a sufficiently large area of the end surface of the lower layer wiring that overlaps the second electrode E2, but this leads to a decrease in the aperture ratio, There is a risk that the variation in the aperture ratio will increase. According to the inventor's study, the angle formed by the first insulating substrate 20 at the end surface forming the gentle slope (for example, the angle θ1 formed by the first end surface ES1 and the first insulating substrate 20) is 20 ° to 60 °. It was confirmed that it was desirable to do.

  FIG. 8 is a schematic plan view of a fourth configuration example of the structure of the pixel PX in the array substrate AR shown in FIG. 2 as viewed from the counter substrate CT side.

  In the fourth configuration example, the first gate wiring GA and the second gate wiring GB are formed along the first direction X, and the source wiring S is formed in the second direction, as compared with the first configuration example shown in FIG. On the other hand, the difference is that the common wiring C is formed along the third direction DR3 intersecting the first direction X and the second direction Y while being formed along Y.

  The third direction DR3 in which the common wiring C extends is different from the fourth direction DR4 in which the slit SL extends. That is, the third direction DR3 intersects with the fourth direction DR4. In the illustrated example, the angle θ3 formed by the first direction X and the third direction DR3 is an acute angle smaller than the angle θ4 formed by the first direction X and the fourth direction DR4.

  In the fourth configuration example, the common wiring C has a first edge ED1 and a second edge ED2 that are both substantially straight. The first distance D1 between the first gate line GA and the first edge ED1 is gradually shortened from the left side to the right side in the drawing. Conversely, the second distance D2 between the second gate line GB and the second edge ED2 becomes gradually longer from the left side to the right side in the drawing. As described above, in the fourth configuration example, the distance between the common wiring C overlapping the second electrode E2, the first gate wiring GA, and the second gate wiring GB is not constant.

  In the illustrated example, the second edge ED2 does not overlap the slit SL. The first edge ED1 slightly overlaps the slit SL, but does not overlap the slit SL in most parts. Thus, by applying a layout in which the first edge ED1 and the second edge ED2 of the common wiring C do not overlap with the slit SL, it is possible to ensure a sufficiently large area of the remaining portion other than the slit SL. It becomes possible to suppress the discontinuity of the second electrode E2. In such a fourth configuration example, the same effect as the above configuration example can be obtained.

  FIG. 9 is a schematic plan view of a fifth configuration example of the structure of the pixel PX in the array substrate AR illustrated in FIG. 2 as viewed from the counter substrate CT side.

  In the fifth configuration example, as compared with the first configuration example shown in FIG. 3, the first gate wiring GA and the second gate wiring GB are formed along the first direction X, and the source wiring S is formed in the second direction. On the other hand, the common wiring C is connected to the first wiring part CA and the first wiring part CA formed at a first distance D1 from the first gate wiring GA, and is formed from the first gate wiring GA. The difference is that the second wiring portion CB is formed with a second distance D2 longer than the first distance D1. In other words, the first wiring portion CA is disposed closer to the second gate wiring GB than the second wiring portion CB. Both the first wiring part CA and the second wiring part CB are formed linearly along the first direction X. As described above, also in the fifth configuration example, as in the fourth configuration example, the intervals between the common wiring C overlapping the second electrode E2, the first gate wiring GA, and the second gate wiring GB are not constant.

  In the illustrated example, the edge on the first gate line GA side of the first wiring part CA intersects with the slit SL. The edge of the second wiring portion CB on the first gate wiring GA side does not overlap the slit SL in most parts. Thus, by applying a layout in which the edges of some of the wiring portions constituting the common wiring C do not overlap with the slit SL, a sufficiently large area of the remaining portion other than the slit SL can be secured. It becomes possible to suppress the discontinuity of the second electrode E2. Also in the fifth configuration example, the same effect as the above configuration example can be obtained.

  As described above, according to this embodiment, it is possible to provide a liquid crystal display device with good display quality.

  In addition, this invention is not limited to the said embodiment itself, In the stage of implementation, it can change and implement a component within the range which does not deviate from the summary. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device LPN ... Liquid crystal display panel AR ... Array substrate CT ... Opposite substrate ACT ... Active area PX ... Pixel E1 ... 1st electrode E2 ... 2nd electrode SL ... Slit LQ ... Liquid crystal layer G ... Gate wiring S ... Source wiring C ... Common wiring ED1 ... 1st edge ED2 ... 2nd edge CV1 ... 1st protrusion part CV2 ... 2nd protrusion part ES1 ... 1st end surface ES2 ... 2nd end surface CA ... 1st wiring part CB ... 2nd wiring part

Claims (5)

An insulating substrate; a first gate wiring and a second gate wiring disposed on the insulating substrate along a first direction; the first gate wiring and the second gate wiring on the insulating substrate; And a first end face formed at a first distance from the first gate line and inclined at a first angle with respect to the insulating substrate and shorter than the first distance from the second gate line. A common wiring including a second end face formed at a second distance and inclined at a second angle greater than the first angle with respect to the insulating substrate; and the first gate wiring and the second wiring on the insulating substrate. A first electrode disposed between the gate wiring and in contact with the common wiring; an insulating film disposed on the first electrode; and an insulating film disposed on the insulating film and facing the first electrode Previous A first substrate having a second electrode including a slit extending directly above the first end surface of the common wiring, and
A second substrate facing the first substrate;
A liquid crystal layer held between the first substrate and the second substrate;
A liquid crystal display device comprising:   The surface of the insulating film includes a first inclined surface formed above the first end surface and a second inclined surface formed above the second end surface, and the first inclined surface is more than the second inclined surface. The liquid crystal display device according to claim 1, wherein the liquid crystal display device has a gentle gentle slope.   3. The liquid crystal display device according to claim 1, wherein an area where the second electrode overlaps above the first end face is larger than an area where the second electrode overlaps above the second end face.   The liquid crystal display device according to claim 1, wherein the first angle is 20 ° to 60 °. The first substrate further includes a source wiring formed along a second direction orthogonal to the first direction,
5. The liquid crystal display device according to claim 1, wherein the slit of the second electrode is formed in a direction intersecting with the common line and the source line. 6.

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