JP5191193B2 - Image display drive device - Google Patents

Description

  According to the present invention, when there is a data transfer request for a part of image data stored in a storage device, the image data relating to the data transfer request is read from the storage device and output to a display device for display. The present invention relates to an image display driving device and an image display system.

  In a radar display device mounted on a ship, an image showing a chart of a predetermined range of sea area around the ship is displayed. This image is displayed by storing image data of a wide range of sea area images (hereinafter referred to as “image data area”) in a storage device such as an SDRAM, and a part of the image data, that is, , Specify and read only the image of the predetermined range centered on the ship in the image (hereinafter, the range of the image is referred to as “display area”), temporarily store it in the line buffer, liquid crystal display, etc. Is displayed on the display device. In this case, since the ship is moving on the sea, the display area of which range in the image data area is changed every moment.

  FIG. 6 is a block diagram illustrating a configuration example of the display system 101 mounted on the radar display device. The display system 101 controls a liquid crystal display (LCD) 2 that displays an image, a liquid crystal drive (LCDC) 3 that controls the LCD 2, an SDRAM 4 that is a storage device that stores image data to be displayed on the LCD 2, and the SDRAM 4. A memory controller 5, an internal bus 6 for connecting the LCDC 3 and the SDRAM 4, and a CPU 7 for centrally controlling each unit. The SDRAM 4 stores image data of an image of a wide range of sea areas. The CPU 7 designates a display area within the range of the image data area of the image data, reads the image data, and displays it on the LCD 2.

  That is, when there is a data transfer request from the CPU 7 by designating the first pixel, the LCDC 3 generates an address designating the read range of the SDRAM 4 image data by the address generation circuit 11 from the data transfer request. Necessary image data is read from the SDRAM 4 via the controller 5. The image data is burst transferred to the line buffer 12 via the internal bus 6 and output from the line buffer 12 to the LCD 2.

  By the way, in the display system 101, when image data of a necessary display area is read from the SDRAM 4 to the line buffer by burst transfer, the data is read for each predetermined burst length. For example, when the burst length is 8 and the data address read from the SDRAM 4 is 0, 1, 2, 3, 4, 5, 6, 7,..., The start address of the SDRAM burst length and the read data address The start address matches. That is, the start address of the burst length is 0, 8, 16,. In this case, data is read for each burst length such as data addresses 0 to 7, data addresses 8 to 15, and so on.

  However, for example, when the head pixel setting by the data transfer request from the CPU 7 is 3 to 10 of the data address of the SDRAM 4, the address of the transfer request output from the address generation circuit 11 to the internal bus 6 is 3 to 3. Thus, the burst length start address does not match the read data address start address. In this case, the data addresses read from the SDRAM 4 output from the memory controller 5 in the data read for the first burst length are initially 3, 4, 5, 6, 7, 0, 1, 2, and the data addresses 0, 1 and 2 are circulated, resulting in an unnecessary access cycle. Data addresses 8, 9, 10, 11, 12, 13, 14, and 15 are also accessed, and 11 to 15 are unnecessary access cycles. The next data transfer request from the address generation circuit 11 also becomes the data address 11 to 18 of the SDRAM 4. Similarly, the data address read from the SDRAM 4 output from the memory controller 5 is first 11, 12, 13, 14, 15. , 8, 9, 10 and the data addresses 8, 9, 10 are circulated, resulting in an unnecessary access cycle. Data addresses 16, 17, 18, 19, 20, 21, 22, 23 are also accessed, and 19 to 23 are unnecessary accesses.

  FIG. 7 is an explanatory diagram for explaining the operation of the internal bus 6 and the access to the SDRAM 4 over time in this case. “3-10” of the code (111) means a data transfer request generated by the address generation circuit 11 and outputted to the internal bus 6 to the addresses 3 to 10 of the SDRAM 4, and “3-10” of the code (112). “3-7-0” means 3, 4, 5, 6, 7, 0, 1 and 2 of the data address of the SDRAM 4 generated by the memory controller 5 (the data addresses 0, 1 and 2 are circulated) The code (113) “8-15” indicates the data address 8, 9, 10, 11, 12, 13, 14, 15 of the SDRAM 4 generated by the memory controller 5. Means "3-10" of the code (114), the data of the data addresses 3 to 10 of the SDRAM 4 is transferred from the memory controller 5 to the LCDC 3 via the internal bus 6 Which means the door.

  Similarly, “11-18” in the code (115) means a data transfer request to the addresses 11 to 18 of the SDRAM 4 generated by the address generation circuit 11 and output to the internal bus 6. "11-15-8" of the data address 11, 12, 13, 14, 15, 8, 9, 10 (data addresses 8, 9, 10) of the SDRAM 4 generated by the memory controller 5 , “16-23” of the reference numeral (117) is the data address 16, 17, 18, 19, 20, 21, 22 of the SDRAM 4 generated by the memory controller 5. , 23, and “11-18” of reference numeral (118) indicates that the data at the data addresses 11 to 18 of the SDRAM 4 is received from the memory controller 5. It is meant to be transferred to LCDC3 through the section bus 6.

  As described above, when the start address of the SDRAM burst length does not match the start address of the read data address, an unnecessary data access cycle occurs. When reading large data such as image data, the data reading speed is reduced by such an unnecessary data cycle, and the internal bus 6 is occupied by the data reading, which may adversely affect other processes. Therefore, it is necessary to increase the speed of the internal bus 6, and there is a problem that the current consumption of the internal bus 6 increases and the circuit scale increases. In order to prevent such a problem, the head address of the burst length and the head address of the read data address must be matched, and the display area can be moved only for each head address of the burst length. There is a problem that the display area cannot be moved finely.

  Next, another problem will be described. First, in FIG. 6, when the bus width of the internal bus 6 is 32 bits and the data amount of one pixel of the image data is 8 bits, the image data is transferred every 4 pixels on the internal bus 6.

  In this case, if the start address of the display area generated by the address generation circuit 11 matches the start address of the bus width of the internal bus 6 due to the setting of the start pixel by the data transfer request from the CPU 7, for example, data transfer is performed. When the head address of the display area requested by the CPU 7 is 0, data at addresses 0 to 3 is transferred in one data transfer of the internal bus 6. That is, the data of address 0 is transferred by bits 0 to 7, the data of address 1 is transferred by bits 8 to 15, the data of address 2 is transferred by bits 16 to 23, and the data of address 3 is transferred by bits 24 to 31.

  On the other hand, if the start address of the display area generated by the address generation circuit 11 does not match the start address of the bus width of the internal bus 6 due to the setting of the start pixel by the data transfer request from the CPU 7, for example, data When the start address of the display area requested by the CPU 7 is 2, the data read from the SDRAM 4 has a different start position. That is, in this case, the data of address 0 is transferred by bits 16 to 23 and the data of address 1 is transferred by bits 24 to 31, and both bits 0 to 7 and bits 8 to 15 become invalid data.

  In this case, invalid data cannot be output to the LCD 2, and in order to prevent deterioration in bus transfer efficiency due to transfer of invalid data, the start address of the display area requested for data transfer from the CPU 7 and the internal bus 6 The number of processes that match the start address of the bus width increases, and the start address of the bus width must match the start address of the read data address. There is a problem that the display area cannot be finely moved because it can only be performed every time (in the above example, every 4 pixels).

  Further, another problem will be described. FIG. 8 is a block diagram illustrating a configuration example of the image display system 121 mounted on the radar display device. In this display system 101, circuit elements and the like having the same reference numerals as those in FIG. 6 are the same as those in FIG.

  The image display system 121 is a device that displays image data having a plurality of layers on the LCD 2. In this example, the image data has two layers, layer 0 and layer 1, and as shown in FIG. 9, the image data of layer 0 is below address 0000 of SDRAM4, and the image data of layer 1 is below address 1000. Each is remembered. Each address of the SDRAM 4 stores 16-bit image data of bits 0 to 15.

  If there is a correlation at the same pixel position in layer 0 and layer 1, the addresses in the SDRAM 4 of the data at the same pixel position in layer 0 and layer 1 are different, so the CPU 7 has the same pixel in the layer 0 area and the layer 1 area. Data is accessed (the same number of times as the number of layers), the correlation of each layer of the same pixel is obtained, and stored in the layer 0 area and the layer 1 area of the SDRAM 4 (again, the number of layers) The SDRAM 4 is accessed the same number of times).

  When reading out the image data, the data below the address 0000 are read out sequentially, and the break between the layer 0 and layer 1 data is at the break between the addresses (between the addresses 999 and 1000). The layer 0 image data is stored in the layer 0 line buffer 12, and the layer 1 image data is stored in the layer 1 line buffer 13. Then, the screen synthesis circuit 14 synthesizes the data stored in the layer 0 line buffer 12 and the data stored in the layer 1 line buffer 13 and outputs them to the LCD 2.

  However, in the case where a plurality of layers are correlated as described above, the CPU 7 accesses the same pixel data in the layer 0 area and the layer 1 area as described above. Will be accessing. In addition, even after the correlation between the layers of the same pixel is obtained, the data is stored in the layer 0 area and the layer 1 area of the SDRAM 4, so that the SDRAM 4 is accessed as many times as the number of layers. As described above, since the display system 121 accesses the different address positions of the SDRAM 4 many times in order to correlate different layers, the data cannot be read from the SDRAM 4 at a high speed, and the image processing capability is reduced. There is a problem that it ends up.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problems, speed up the reading of image data, and make it possible to finely move the display area.

  (1) According to the present invention, when there is a data transfer request for a part of image data stored in the SDRAM, the image data related to the data transfer request is read from the SDRAM and output to the display device. In the display driving device, when there is a buffer for temporarily storing the image data read from the SDRAM, output means for outputting the image data temporarily stored in the buffer to the display device, and the data transfer request, First address determination means for determining whether or not the start address of the image data relating to the data transfer request matches the start address of the SDRAM burst length, and if both the start addresses do not match by the start address determination means When it is determined, the start address of the image data related to the data transfer request is First address conversion means for converting the first address of the DRAM burst length, and the image data for each burst length of the bus connecting the SDRAM and the buffer from the first address converted by the first address conversion means. Image data reading means for making a read request from the memory, memory control means for controlling the SDRAM based on a request from the image data reading means and reading image data from the SDRAM in accordance with the SDRAM read procedure, and both heads by the address determination means. When it is determined that the addresses do not match, the image data read by the memory control means is included in the address after conversion by the head address conversion means but is not yet converted by the head address conversion means Not included in Unnecessary image data determining means for determining and the image data read by the image data reading means are determined not to be included in the data transfer request before conversion by the data transfer request converting means by the unnecessary image data determining means. An image display driving device comprising: storage means for storing in the buffer except for the portion that has been corrected.

  According to the invention of (1), even when the head address of the burst length does not match the head address of the read data address, the image data is read from the SDRAM for each burst length, and the image data after the read Since unnecessary items are removed from the memory, unnecessary access cycles due to circulation can be prevented and image data can be read faster, resulting in a reduction in bus speed and current consumption. And circuit scale can be reduced. In addition, the display area can be moved finely.

  Hereinafter, a plurality of embodiments of the invention will be described.

[Embodiment 1]
FIG. 1 is a block diagram showing an electrical connection of the image display system 1 according to the present embodiment. The image display system 1 is a storage device that stores a liquid crystal display (LCD) 2 that displays an image, a liquid crystal driving device (LCDC) 3 that is an image display driving device that controls the LCD 2, and image data to be displayed on the LCD 2. An SDRAM 4, a memory controller 5 that controls the SDRAM 4 and reads out image data in accordance with the SDRAM reading procedure, an internal bus 6 that connects the LCDC 3 and the SDRAM 4, and a CPU 7 that centrally controls each unit are provided. The SDRAM 4 stores image data of an image of a wide range of sea areas. The CPU 7 designates a display area within the range of the image data area of the image data, reads the image data, and displays it on the LCD 2.

  That is, when there is a data transfer request from the CPU 7 by designating the first pixel, the LCDC 3 generates an address designating the read range of the SDRAM 4 image data by the address generation circuit 11 from the data transfer request. Necessary image data is read from the SDRAM 4 via the controller 5. The image data is burst transferred to the line buffer 12 via the internal bus 6 and output from the line buffer 12 to the LCD 2.

  The data transfer request from the CPU 7 is made by designating the position of the first pixel in the display area from which data is read. In response to this data transfer request, first, the head address correction circuit 21 determines whether or not the head address of the image data in the display area related to the data transfer request matches the head address of the SDRAM burst length. . In this example, the burst length is 8. Thus, for example, if the leading address for the data transfer request is 0, the leading address of the image data in the display area for the data transfer request matches the leading address of the SDRAM burst length. In this case, the data transfer request is output to the address generation circuit 11 while keeping the leading address for the data transfer request as 0. Based on this, the address generation circuit 11 generates an address that matches the burst length, reads data from the SDRAM 4, and stores it in the line buffer 12. Therefore, data is read from the SDRAM 4 for each burst length, such as data addresses 0 to 7, data addresses 8 to 15, and so on.

  Next, when the head address correction circuit 21 determines that the head address of the image data in the display area for the data transfer request does not match the head address of the SDRAM burst length, the head address correction circuit 21 The start address of the SDRAM burst length including the start pixel position designated by the data transfer request is corrected and output to the address address generation circuit 11. For example, when the head pixel in the data transfer request from the CPU 7 is the data address 3 of the SDRAM 4, the data address 0 is corrected.

  Based on this, the address generation circuit 11 outputs a data transfer request of the data addresses 0 to 7 to the internal bus 6, and the memory controller 5 accesses the data addresses 0 to 7 of the SDRAM 4 to read the data. Thereafter, the same data is read out.

  FIG. 2 is an explanatory diagram for explaining the operation of the internal bus 6 and the access to the SDRAM 4 over time in this case. When the head pixel in the data transfer request from the CPU 7 is the data address 3 of the SDRAM 4, the head address correction circuit 21 converts the head pixel position of the data transfer request into the address 0, and the address correction circuit 21 A data transfer request to addresses 0 to 7 is output to the bus 6, and the memory controller 5 accesses addresses 0 to 7 of the SDRAM 4 (accessed to “0-7” of the code (2), The addresses 0 to 7 of the SDRAM 4 are read (“0-7” in the code (3)).

  Thereafter, a data transfer request ("8-15" of the code (4)) to the addresses 8 to 15 of the SDRAM 4 by the address generation circuit 11 is directly sent to the addresses 8 to 15 (code (5) of the SDRAM 4) by the memory controller. “8-15”) is accessed, and addresses 8 to 15 of the SDRAM 4 (“8-15” in symbol (6)) are read out to the internal bus 6.

  The read-out top image data includes unnecessary pixel data. For example, since the addresses 0 to 7 are read for the first pixel setting at the address 3, the data at the addresses 0 to 2 is not necessary.

  Returning to FIG. 1, the head address correction circuit 21 converts the head pixel as described above, so it is not included in the data transfer request before the conversion, but what is included in the data transfer request after the conversion. Whether or not there is (addresses 0 to 2 in this example) is specified, and this data is output to the line buffer writing circuit 22.

  Based on this data, the line buffer writing circuit 22 deletes unnecessary image data at addresses 0 to 2 from the read image data at addresses 0 to 7 and writes them to the line buffer 12.

  According to the image display system 1 described above, even when the head address of the burst length does not match the head address of the read data address, the image data is read from the SDRAM 4 for each burst length. Since unnecessary items are removed from the image data, unnecessary access cycles due to rounds can be prevented, and the image data can be read faster, resulting in a reduction in bus speed. It is possible to reduce current consumption and circuit scale. In addition, the display area can be moved finely.

[Embodiment 2]
FIG. 3 is a block diagram showing electrical connections of the image display system 31 according to the present embodiment. The image display system 31 is a storage device that stores a liquid crystal display (LCD) 2 that displays an image, a liquid crystal drive device (LCDC) 3 that is an image display drive device that controls the LCD 2, and image data to be displayed on the LCD 2. An SDRAM 4, a memory controller 5 that controls the SDRAM 4, an internal bus 6 that connects the LCDC 3 and the SDRAM 4, and a CPU 7 that centrally controls each unit are provided. The SDRAM 4 stores image data of an image of a wide range of sea areas. The CPU 7 designates a display area within the range of the image data area of the image data, reads the image data, and displays it on the LCD 2.

  That is, when there is a data transfer request from the CPU 7 by designating the first pixel, the LCDC 3 generates an address designating the read range of the SDRAM 4 image data by the address generation circuit 11 from the data transfer request. Necessary image data is read from the SDRAM 4 via the controller 5. The image data is burst transferred to the line buffer 12 via the internal bus 6 and output from the line buffer 12 to the LCD 2.

  The data transfer request from the CPU 7 is made by designating the position of the first pixel in the display area from which data is read. In response to this data transfer request, first, in the unnecessary data determination circuit 32, whether or not the leading address of the image data in the display area related to the data transfer request matches the leading address of the bus width of the internal bus 6. Determine. That is, in the image display system 31, the bus width of the internal bus 6 is 32 bits, and one pixel of image data is 8 bits. Therefore, the image data is read by 4 pixels via the internal bus 6. Thus, for example, if the leading address for the data transfer request is 0, the leading address of the image data in the display area for the data transfer request matches the leading address of the bus width. In this case, the data transfer request is output to the address generation circuit 11 while keeping the leading address for the data transfer request as 0. Based on this, the address generation circuit 11 generates an address that matches the head address of the bus width of the internal bus 6, reads data from the SDRAM 4, and stores it in the line buffer 12. Therefore, data is transferred from the SDRAM 4 in units of 4 pixels such as data addresses 0 to 3, data addresses 4 to 7,... According to the bus width. That is, if the data address is 0 to 3, 1-pixel data is transferred using bits 0 to 7, bits 8 to 15, bits 16 to 23, and bits 24 to 31, respectively.

  Next, when the unnecessary data determination circuit 32 determines that the start address of the image data in the display area for the data transfer request does not match the start address of the bus width, the start address is stored in the address generation circuit 11. Outputs 0. At this time, the transfer data of the bus width of the internal bus 6 read from the SDRAM 4 includes invalid data. For example, when the leading address of the image data in the display area for the data transfer request is 2, it does not match the leading address of the bus width. In this case, the unnecessary data determination circuit 32 sets the leading address to 0. In order to be converted, data corresponding to 1 pixel and 2 pixels in total are transferred in bits 16 to 23 and bits 24 to 31, respectively. Bits 0 to 7 and bits 8 to 15 are invalid data. Thereafter, the address generation circuit 11 outputs a data transfer request that matches the leading address of the bus width of the internal bus 6 to the internal bus 6, thereby performing data transfer that does not include invalid data.

  The head image data read out in this way includes invalid data. In this case, the unnecessary data determination circuit 32 outputs the position data of the invalid data that includes invalid data to the line buffer write circuit 33. In the above example, position data is output when bits 0 to 7 and bits 8 to 15 are invalid data.

  Based on this data, the line buffer writing circuit 33 prevents invalid data of bits 0 to 7 and bits 8 to 15 from being written to the line buffer 12 out of the data for one read bus width.

  According to the image display system 31 described above, even when the leading address of the bus width and the leading address of the read data address do not match, the image data is transferred from the SDRAM 4 for each bus width. Since invalid data is removed from the image data, the reading of the image data can be speeded up, and the display area can be moved finely.

[Embodiment 3]
FIG. 4 is a block diagram showing an electrical connection of the image display system 41 according to the present embodiment. The image display system 41 is a storage device that stores a liquid crystal display (LCD) 2 that displays an image, a liquid crystal drive device (LCDC) 3 that is an image display drive device that controls the LCD 2, and image data to be displayed on the LCD 2. An SDRAM 4, a memory controller 5 that controls the SDRAM 4, an internal bus 6 that connects the LCDC 3 and the SDRAM 4, and a CPU 7 that centrally controls each unit are provided. The SDRAM 4 stores image data of an image of a wide range of sea areas. The CPU 7 designates a display area within the range of the image data area of the image data, reads the image data, and displays it on the LCD 2.

  In the present embodiment, the image data includes a plurality of layers, in this example, two layers, layer 0 and layer 1. Layer 0 and layer 1 have a correlation with respect to the same pixel. The CPU 7 reads the layer 0 and layer 1 image data from the SDRAM 4, performs correlation processing with the same pixel data, and again stores the layer 0 and layer 1 image data in the layer 4 storage area and the layer 1 storage area of the SDRAM 4. Store each one.

  FIG. 5 is an explanatory diagram for explaining the storage of the layer 0 and layer 1 image data in the SDRAM 4. In the SDRAM 4, the image data of the same pixel of layer 0 and layer 1 is stored in the data area of the same address. For example, if the data amount is 8 bits for one pixel of layer 0 and one pixel of layer 1, the data for one pixel of layer 0 is stored in bits 0 to 7 of the data area of one address of SDRAM4, Data for one pixel of layer 1 is stored in bits 8 to 15.

  Thus, when the CPU 7 reads the layer 0 and layer 1 data from the SDRAM 4 in order to obtain the correlation between the same pixels, the layer 0 and layer 1 data of the same pixel is included if the data is read from the same address. Thus, it is possible to prevent the trouble of reading layer 0 data from a certain address of the SDRAM 4 and reading layer 1 data from a different address twice. In addition, when the data of the same pixel of layer 0 and layer 1 is correlated and then the data of the same pixel of layer 0 and layer 1 is stored again in the SDRAM 4, layer 0 and layer of the same pixel at the same address are stored. 1 data is stored. That is, data for one pixel of layer 0 is stored in bits 0 to 7 of the data area of the same address of the SDRAM 4, and data for one pixel of layer 1 is stored in bits 8 to 15. Therefore, it is possible to prevent the trouble of storing layer 0 data at a certain address of the SDRAM 4 and storing layer 1 data at a different address.

  Returning to FIG. 4, in the case of the data structure of the image data in the SDRAM 4 as described above, when the data transfer request is made by designating the first pixel from the CPU 7, the LCDC 3 receives the address generation circuit from the data transfer request. 11, an address for designating a reading range of image data of the SDRAM 4 is generated, and necessary image data is sequentially read from the SDRAM 4 for each address via the memory controller 5. This image data is burst transferred via the internal bus 6.

  As described above, since the read image data includes the same pixel data of layer 0 and layer 1 at the same address, the separation circuit 42 causes the layer 0 and layer of the same pixel stored at the same address to be stored. The layer 0 data and the layer 1 data after separation are stored in the layer 0 line buffer 43 and the layer 1 line buffer 44, respectively. As described above, the layer 0 data and the layer 1 data respectively stored in the layer 0 line buffer 43 and the layer 1 line buffer 44 are combined by the screen combining circuit 45 and output to the LCD 2.

  According to the image display system 41 described above, the layer 0 data is read twice from a certain address of the SDRAM 4 and the layer 1 data is read from a different address, or the layer 0 data is stored at a certain address of the SDRAM 4. In addition, since it is possible to prevent the trouble of storing layer 1 data at different addresses twice, the data can be read from the SDRAM 4 at high speed, and the image processing capability can be improved.

  Note that the image display system 41 may handle image data having no correlation between layers unlike the above. In that case, according to the configuration of the image display system 41 described with reference to FIGS. 4 and 5, the reading speed of the image data from the SDRAM 4 may be decreased.

  Therefore, the configuration of the image display system 41 described with reference to FIGS. 4 and 5 and the configuration of the image display system 121 described with reference to FIGS. You may make it switch.

  That is, when handling image data having a correlation between layers, as described with reference to FIG. 5, the data of the same pixel in each of a plurality of layers is stored in the same address of the SDRAM 4, and the image read from the SDRAM 4 is read. With respect to the data, the separation circuit 42 separates the layer 0 and layer 1 data of the same pixel for each layer in the data of the same address of the SDRAM 4, and the layer 0 line buffer 43 and the layer 1 line buffer 44 respectively. Store.

  On the other hand, when handling image data having no correlation between layers, as described with reference to FIG. 9, the image data of each layer is stored in different addresses of the SDRAM 4, and the image data read from the SDRAM 4 is The separation circuit 42 separates the data of layer 0 and layer 1 due to the difference in the SDRAM 4 and stores them in the layer 0 line buffer 43 and the layer 1 line buffer 44, respectively.

It is a block diagram which shows the electrical connection of the image display system concerning Embodiment 1 of this invention. It is explanatory drawing of operation | movement of the image display system of FIG. It is a block diagram which shows the electrical connection of the image display system concerning Embodiment 2 of this invention. It is a block diagram which shows the electrical connection of the image display system concerning Embodiment 3 of this invention. FIG. 5 is an explanatory diagram of a data configuration of image data in the SDRAM in FIG. It is a block diagram which shows the electrical connection of the image display system explaining the subject of this invention. It is explanatory drawing of operation | movement of the image display system of FIG. It is a block diagram which shows the electrical connection of the image display system explaining the subject of this invention. It is a block diagram which shows the electrical connection of the image display system explaining the subject of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image display system 2 Liquid crystal display 3 Liquid crystal drive device 4 SDRAM
6 Internal bus 11 Address generation circuit 12 Line buffer 21 Start address correction circuit 22 Line buffer write circuit

Claims (1)

In an image display driving device that reads out the image data related to the data transfer request from the SDRAM and outputs the data to a display device when there is a data transfer request for a part of the image data stored in the SDRAM.
A buffer for temporarily storing the image data read from the SDRAM;
Output means for outputting image data temporarily stored in the buffer to a display device;
When there is a data transfer request, start address determination means for determining whether or not the start address of the image data related to the data transfer request matches the start address of the SDRAM burst length;
A head address converting means for converting the head address of the image data relating to the data transfer request into a head address of the SDRAM burst length when the head address determining means determines that the two head addresses do not match;
Image data reading means for making a request for reading the image data from the SDRAM for each burst length of a bus connecting the SDRAM and the buffer from the head address converted by the head address converting means;
Memory control means for controlling the SDRAM based on a request from the image data reading means and reading image data from the SDRAM according to a SDRAM reading procedure;
When the address determination means determines that the two head addresses do not match, the image data read by the memory control means is included in the address after conversion by the head address conversion means but is included in the head Unnecessary image data determination means for determining what is not included in the address before conversion by the address conversion means;
The image data read by the image data reading unit is stored in the buffer except for a portion determined by the unnecessary image data determination unit as not included in the data transfer request before conversion by the data transfer request conversion unit. Storage means for
An image display driving device comprising:

Images