JP5187150B2 - Integrated circuit device, electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an integrated circuit device, an electro-optical device, an electronic apparatus, and the like.

  In recent years, high-definition video technology such as high-definition video has become widespread, and along with this, display devices (electronic devices) such as liquid crystal projectors have become higher definition and multi-gradation. With higher definition, it is required to drive data lines such as a liquid crystal panel (electro-optical panel) at a higher speed. In addition, driving with higher voltage accuracy is required due to multi-gradation.

  However, since data lines such as liquid crystal panels (electro-optical panels) have parasitic capacitance, inductance, and resistance, signal quality deteriorates due to ringing or the like when driven at high speed. As a result, the data lines There is a problem that cannot be set to a desired gradation voltage.

  For example, Patent Document 1 discloses a method for driving a data line with a DAC output after driving the data line with an operational amplifier. For example, Patent Document 2 discloses a technique for preventing oscillation by switching the output resistance of a drive circuit. According to these methods, the ringing or the like can be reduced by changing the output impedance of the drive circuit.

However, in these methods, since the electrostatic protection resistance appears as one node, there is a problem that electrostatic charges are concentrated on the portion of the drive circuit having the lowest electrostatic resistance. Further, in the method of Patent Document 2, it is necessary to provide a special resistance element for switching output impedance, and there is a problem that the area occupied by the circuit increases.
JP 2001-188615 A JP 2005-175812 A

  According to some aspects of the present invention, it is possible to provide an integrated circuit device, an electro-optical device, an electronic apparatus, and the like that can drive a drive target at high speed and stably and that have high electrostatic resistance.

  One embodiment of the present invention is a driving circuit that drives a driving target connected to an output terminal of an integrated circuit device, and a first electrostatic circuit provided between a first output node of the driving circuit and the output terminal. A second resistance for electrostatic protection provided between the resistance element for protection, the second output node of the drive circuit, and the output terminal, the resistance value of which is greater than the first resistance element for electrostatic protection. The drive circuit drives the drive object via the first electrostatic protection resistance element and the second electrostatic protection resistance element in the first half of the drive period, and drives the drive The second half of the period relates to an integrated circuit device that drives the drive target via the second electrostatic protection resistance element without passing through the first electrostatic protection resistance element.

  According to one embodiment of the present invention, output impedance control can be realized in which the output impedance in the second half of the drive period is greater than the output impedance in the first half of the drive period. By this output impedance control, it is possible to suppress deterioration in signal quality such as overshoot, undershoot, and ringing that occurs when the signal voltage rises and falls. Further, by diverting the electrostatic protection resistance element, it is not necessary to provide a special resistance element for output impedance control, and the area occupied by the circuit can be reduced. Furthermore, since the impedance to the power source viewed from the output terminal of the integrated circuit device can be set to a value similar to the output impedance, the electrostatic resistance can be increased.

  In one embodiment of the present invention, the drive circuit includes a drive amplifier, a first switch element provided between an output node of the drive amplifier and the first output node, and an output node of the drive amplifier. And a second switch element provided between the second output node, the first switch element is in an on state during the first half of the drive period, and the second half of the drive period The second switch element may be in an on state throughout the first half period and the second half period of the driving period.

  In this way, the above-described output impedance control can be realized by the on / off control of the first and second switch elements, and deterioration of signal quality and the like can be prevented. Further, when driving the data line of the electro-optical panel, the drive amplifier can be electrically separated from the data line, for example, in the equalization period and the precharge period.

  In one embodiment of the present invention, the driving circuit includes a differential unit, a first output unit in which an output of the differential unit is connected to an input thereof, and an output thereof is output to the first output node. An output of the differential section is connected to an input of the differential section, and a second output section of which the output is output to the second output node. In the first half period of the driving period, the first output And the second output unit are both set to an output enable state, and in the second half of the driving period, the first output unit is set to an output disable state, and the second output unit is output enabled. The state may be set.

  This eliminates the need for a switch element for switching the output impedance, thereby reducing the area occupied by the circuit.

  In the aspect of the invention, the first output unit may have a drain connected to the first output node and a gate connected to the first differential output node of the differential unit. A second N-type transistor whose drain is connected to the source of the first N-type transistor, whose output enable signal is input to its gate, and whose source is connected to the low-potential-side power supply; A first P-type transistor having a drain connected to the first output node and a gate connected to a second differential output node of the differential section; and a drain connected to the first P-type A second P-type transistor connected to a source of a transistor, having an inverted signal of the output enable signal input to a gate thereof, and having a source connected to a high-potential side power supply, A third N-type transistor whose drain is connected to the second output node, whose gate is connected to the first differential output node of the differential section, and whose source is connected to the low-potential side power supply The drain is connected to the second output node, the gate is connected to the second differential output node of the differential section, and the source is connected to the high potential side power supply. The output enable signal may be set to a high potential level in the first half period of the driving period, and the output enable signal may be set to a low potential level in the second half period of the driving period. .

  In this case, a transistor with a small gate width (channel width) can be used as a transistor used for switching output impedance, so that the area occupied by the circuit can be reduced.

  In the aspect of the invention, the first electrostatic resistance element may be i (i is 1 ≦ i) of the first to Nth (N is an integer of 2 or more) electrostatic protection resistance units. <An integer that is N) of electrostatic protection resistance units, and the second electrostatic protection resistance element is the i of the first to Nth electrostatic protection resistance units. The resistance unit for electrostatic protection except for the electrostatic protection resistor unit of FIG. 1 is formed, and a direction parallel to one side of the integrated circuit device is defined as a first direction and orthogonal to the first direction. When the direction is the second direction, the first to Nth electrostatic protection resistance units are arranged in the first direction of the drive circuit, and the first to Nth electrostatic resistances are arranged. Among the protective resistor units, the electrostatic protective resistor unit of the j + 1th (j is an integer satisfying 1 ≦ j <N) First to the second may be positioned in the direction of the static electricity protection resistor units of the j-th of the electrostatic protection resistor units of the first N.

  If it does in this way, two resistance elements for electrostatic protection with a desired resistance value can be easily formed by combining a resistance unit arbitrarily from a plurality of resistance units for electrostatic protection.

  In the aspect of the invention, as the first to Nth electrostatic protection resistance units, first, second, and third resistance units are provided, and the second resistance unit is the first resistance unit. The first electrostatic resistance element is disposed between a resistance unit and the third resistance unit, and the first electrostatic protection resistance element includes the first and third resistance units, and the second electrostatic protection resistance. The element may be constituted by the second resistance unit.

  In this way, it is possible to easily form two electrostatic protection resistance elements having different resistance values. Further, since the resistance units that are sources of more heat can be arranged apart from each other, an increase in temperature can be suppressed and the electrostatic resistance of the integrated circuit device can be increased.

  In the aspect of the invention, the first, second, and third resistance units may be formed of impurity regions, and may include a first metal line connected to the output terminal of the integrated circuit device, and the first resistance. Of the contacts connecting the impurity regions of the unit, the contact formed closest to the drive circuit is the first contact, and the first metal line and the impurity region of the second resistor unit are connected. Of the contacts to be contacted, the contact formed closest to the drive circuit is the second contact, and of the contacts connecting the first metal line and the impurity region of the third resistance unit, the drive When the contact formed closest to the circuit is the third contact, the first contact and the third contact are the second contact. The contact formed between the second metal line connected to the first output node of the drive circuit and the impurity region of the first resistance unit is formed at a position closer to the drive circuit. A contact formed farthest from the drive circuit is a fourth contact, and a third metal line connected to the second output node of the drive circuit is connected to the impurity region of the second resistance unit. Of the contacts to be connected, the contact formed farthest from the drive circuit is a fifth contact, and among the contacts connecting the second metal line and the impurity region of the third resistance unit, the drive The contact formed farthest from the circuit is the sixth contact, the distance between the first contact and the fourth contact is L1, and the second contact is The distance between the tact fifth contact and L2, the distance between the sixth contact and the third contact when the L3, may be L1 <L2 and L3 <L2.

  In this way, it is possible to easily form two electrostatic protection resistance elements having greatly different resistance values only by changing the arrangement of the contacts. Furthermore, by widening the contact region between the impurity region and the metal line, the current flowing through the resistance element region can be reduced, so that the electrostatic resistance of the integrated circuit device can be increased.

  In one embodiment of the present invention, the drive target may be an electro-optical panel.

  In this way, image data or the like can be stably supplied to the electro-optical panel at high speed, and the electrostatic resistance of the data line driving circuit or the like can be increased.

  Another aspect of the present invention relates to an electro-optical device and an electronic apparatus including the integrated circuit device described above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Basic Configuration Example FIG. 1 shows a basic configuration example of the integrated circuit device of this embodiment. The integrated circuit device according to the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications may be made such as omitting some of the components, replacing them with other components, and adding other components. Is possible.

  The integrated circuit device of this configuration example includes a drive circuit 10 and first and second electrostatic protection resistance elements 30 and 31 for electrostatic protection. The drive circuit 10 receives the input signal IA, outputs output signals to the first and second output nodes N1 and N2, and drives a drive target connected to the output terminal 20 of the integrated circuit device. The first electrostatic protection resistance element 30 is provided between the first output node N1 of the drive circuit 10 and the output terminal 20, and the second electrostatic protection resistance element 31 is the second resistance node 31 of the drive circuit 10. Provided between output node N2 and output terminal 20. When the resistance value of the first electrostatic protection resistance element 30 is R1, and the resistance value of the second electrostatic protection resistance element 31 is R2, R1 <R2.

  The drive circuit 10 drives the drive target via the first electrostatic protection resistance element 30 and the second electrostatic protection resistance element 31 in the first half period T1 of the drive period, and in the second half period T2 of the drive period, The drive target is driven via the second electrostatic protection resistance element 31 without passing through the first electrostatic protection resistance element 30. That is, when the output impedance of the drive circuit 10 itself is RD, the first and second electrostatic protection resistance elements 30 and 31 are connected in parallel in the first half period T1 of the drive period. The output impedance of the entire circuit is RD + (R1 × R2) / (R1 + R2). Here, when R2 is sufficiently larger than R1 (for example, R1 = 50Ω, R2 = 1 kΩ), the output impedance of the entire circuit is approximately RD + R1. On the other hand, in the second half period T2 of the driving period, for example, only the second electrostatic protection resistance element 31 is connected, so that the output impedance of the entire circuit is RD + R2.

  Here, the drive period is a period for setting a voltage to be driven to a desired voltage (for example, a data voltage corresponding to image data) by driving a drive target (for example, a data line). Is an electro-optical panel (data line), for example, one horizontal scanning period (1H period). Further, when one drive circuit (operational amplifier) drives R, G, and B data lines (pixels) in a time-sharing manner in one horizontal scanning period, for example, R, G, and B Each driving period can be a driving period of the present embodiment.

  Thus, in the integrated circuit device of this embodiment, when the output impedance in the first half period T1 of the driving period is ROUT1, and the output impedance in the second half period T2 of the driving period is ROUT2, the output impedance satisfying ROUT1 <ROUT2 Control can be performed.

  FIG. 2 shows an example of the signal waveform of the drive signal when the output impedance control is performed using the integrated circuit device of the present embodiment and when the output impedance control is not performed.

  In FIG. 2, V1 shows an example of a signal waveform when output impedance control is not performed. In this case, since the output impedance is a low value throughout both the first half period T1 and the second half period T2, the rise of the signal voltage becomes steep as shown by A1 in FIG. A drive target (for example, an electro-optical panel) connected to the output terminal 20 includes parasitic capacitance, inductance, and resistance. In general, it is known that when a drive target including such a parasitic element is driven by a signal having a steep rise or fall, overshoot, undershoot, ringing, and the like occur, leading to deterioration of signal quality. . For example, A2 in FIG. 2 indicates overshoot, and A3 to A6 indicate ringing. When the output impedance control is not performed in this way, it takes time for the signal voltage to stabilize, and there is a possibility of causing a malfunction of the circuit such as a noise generation source.

  In FIG. 2, V2 shows an example of a signal waveform when the output impedance control is performed using the integrated circuit device of the present embodiment. As described above, the output impedance has a low value in the first half period T1 of the driving period, and the output impedance has a high value in the second half period T2. For this reason, it rises steeply in the first half period T1, but since the output impedance becomes high in the second half period T2, the rise becomes slow as shown by B1. As a result, overshoot is reduced as indicated by B2, and ringing is also suppressed as indicated by B3 to B6.

  The signal waveform example in FIG. 2 shows the rise of the signal voltage. However, it is possible to suppress degradation of signal quality such as undershoot and ringing by performing the output impedance control also at the fall.

  As described above, by using the integrated circuit device of the present embodiment shown in FIG. 1, it is possible to drive the drive target without degrading the signal quality, and to obtain a stable operation of the circuit.

  Further, in the integrated circuit device of this embodiment, the first and second electrostatic protection resistance elements 30 and 31 are used for the above-described output impedance control. In general, in an integrated circuit device, a resistance element for electrostatic protection is provided adjacent to an input / output terminal in order to prevent electrostatic breakdown due to charging / discharging of external static electricity through the input / output terminal. Has been done. By diverting the electrostatic protection resistance element to the output impedance control, it is not necessary to provide a special resistance element for output impedance control, and the area occupied by the circuit can be reduced.

  Furthermore, in the integrated circuit device of the present embodiment, since the impedance to the power source viewed from the output terminal 20 can be set to a value similar to the output impedance, the electrostatic resistance can be increased.

2. First Configuration Example FIG. 3 shows a first configuration example of the integrated circuit device of this embodiment. In this configuration example, the drive circuit 10 includes a drive amplifier 40, a first switch element SW1, and a second switch element SW2. The first switch element SW1 is provided between the output node N3 and the first output node N1 of the drive amplifier 40, and the second switch element SW2 is connected to the output node N3 and the second output node N2 of the drive amplifier 40. Between. SW1 is in an on state in the first half period T1 of the driving period, and is in an off state in the second half period T2 of the driving period. SW2 is in an on state throughout the first half period T2 and the second half period T2 of the driving period.

  The first and second switch elements SW1 and SW2 can be constituted by, for example, a transfer gate (transmission gate) in which one N-type transistor and one P-type transistor are connected in parallel.

  Also in the first configuration example of FIG. 3, signal quality degradation such as overshoot, undershoot, and ringing can be suppressed by performing output impedance control similar to that of the configuration example of FIG. 1. That is, the drive amplifier 40 drives the drive target via the first electrostatic protection resistance element 30 and the second electrostatic protection resistance element 31 in the first half period T1 of the drive period, and in the second half period T2 of the drive period. The drive target is driven only through the second electrostatic protection resistance element 31. Accordingly, as described above, when the output impedance in the first half period T1 of the driving period is ROUT1, and the output impedance in the second half period T2 of the driving period is ROUT2, output impedance control is performed so that ROUT1 <ROUT2. it can.

  In the first configuration example as well, by diverting the electrostatic protection resistance element to the output impedance control, it is not necessary to provide a special resistance element for output impedance control, and the area occupied by the circuit is reduced. be able to.

  Furthermore, in the first configuration example, both the first and second switch elements SW1 and SW2 can be turned off. For example, when driving a data line such as a liquid crystal panel, the data line and the counter electrode are electrically short-circuited at the beginning of each horizontal scanning period (equalization) and the data lines are set to a certain level. Control (precharge) is set to the intermediate potential. In the period in which these controls are performed, the drive amplifier 40 needs to be electrically disconnected from the data line. In the first configuration example, this can be realized by turning off both SW1 and SW2.

  As described above, by using the first configuration example, it is possible to drive the drive target without degrading the signal quality, and to obtain a stable operation of the circuit. Further, by diverting the electrostatic protection resistance element to output impedance control, it is not necessary to provide a special resistance element for output impedance control, and the area occupied by the circuit can be reduced. Furthermore, when driving a data line such as a liquid crystal panel, the drive amplifier can be electrically disconnected from the data line during the equalization period and the precharge period.

3. Second Configuration Example FIG. 4 shows a second configuration example. In this configuration example, the drive circuit 10 includes a differential unit 50, a first output unit 51, and a second output unit 52. In the first output unit 51, the output of the differential unit 50 is connected to the input, and the output is output to the first output node N1. The output of the differential unit 50 is connected to the input of the second output unit 52, and the output is output to the second output node N2. In the first half period T1 of the drive period, both the first output unit 51 and the second output part 52 are set to the output enable state, and in the second half period T2 of the drive period, the first output unit 51 is set to the output disable state. As a result, the second output unit 52 is set to the output enable state.

  Also in the second configuration example of FIG. 4, signal quality deterioration such as overshoot, undershoot and ringing can be suppressed by performing output impedance control similar to that of the configuration example of FIG. 1. That is, the drive circuit 10 drives the drive target via the first electrostatic protection resistance element 30 and the second electrostatic protection resistance element 31 in the first half period T1 of the drive period, and in the second half period T2 of the drive period. The drive target is driven only through the second electrostatic protection resistance element 31. Accordingly, as described above, when the output impedance in the first half period T1 of the driving period is ROUT1, and the output impedance in the second half period T2 of the driving period is ROUT2, output impedance control is performed so that ROUT1 <ROUT2. it can.

  Also in the second configuration example, by using the electrostatic protection resistance element for the output impedance control described above, it is not necessary to provide a special resistance element for output impedance control, and the area occupied by the circuit is reduced. be able to.

  Further, the second configuration example has an advantage that a switch element for switching the output impedance is not necessary. In the first configuration example of FIG. 3 described above, two switch elements SW1 and SW2 are provided to switch the output impedance. The transistor constituting this switch element must have a low on-resistance (resistance in the on state). If the on-resistance is large, the output impedance is almost determined by the on-resistance of the switch element. In this case, the output impedance hardly changes even when the switch element is switched.

  In order to reduce the on-resistance of the transistor constituting the switch element, the gate width (channel width) of the transistor must be increased. Therefore, the above-described first configuration example of FIG. 3 has a drawback that the area occupied by the circuit becomes large. On the other hand, in the second configuration example shown in FIG. 4, since the switch element for switching the output impedance is not necessary, the area occupied by the circuit can be reduced.

  FIG. 5 shows a more detailed configuration example of the second configuration example. In this configuration example, the differential unit 50 is configured by a class AB push-pull differential amplifier.

  The first output unit 51 has a drain connected to the first output node N1, a gate connected to the first differential output node ND1 of the differential unit 50, and a first N-type transistor TN6 connected to the first output node N1. The second N-type transistor TN7 whose drain is connected to the source of the first N-type transistor TN6, the output enable signal ENB is input to its gate, and whose source is connected to the low-potential-side power source VSS, and whose drain is A first P-type transistor TP6 connected to the first output node N1 and having the gate connected to the second differential output node ND2 of the differential section 50, and the drain of the first P-type transistor TP6. The second P-type transistor is connected to the source, the inverted signal XENB of the output enable signal ENB is input to the gate, and the source is connected to the high potential side power supply VDD. And a register TP7.

  The second output unit 52 has a drain connected to the second output node N2, a gate connected to the first differential output node ND1 of the differential unit 50, and a source connected to the low potential power source VSS. The third N-type transistor TN8, the drain thereof is connected to the second output node N2, the gate thereof is connected to the second differential output node ND2 of the differential section 50, and the source thereof is connected to the high potential side. And a third P-type transistor TP8 connected to the power supply VDD.

  In the first half period T1 of the driving period, the output enable signal ENB is set to the high potential level (high potential side power supply VDD), and in the second half period T2 of the driving period, the output enable signal ENB is set to the low potential level (low potential side power supply VSS). Set to

  In the configuration example of FIG. 5, it is possible to suppress deterioration of signal quality such as overshoot, undershoot and ringing by performing output impedance control as follows.

  In the first half period T1 of the driving period, the output enable signal ENB is set to a high potential level, so that the N-type transistor TN7 is turned on. Further, since the inverted signal XENB of ENB is set to a low potential level, the P-type transistor TP7 is also turned on. On the other hand, the second output unit 52 is always in an outputable state. Therefore, in the first half period T1, the first output unit 51 drives the drive target via the first electrostatic protection resistance element 30, and at the same time, the second output unit 52 outputs the second electrostatic protection resistance element 31. The drive target is driven via

  In the second half period T2 of the driving period, the output enable signal ENB is set to a low potential level, so that the N-type transistor TN7 is turned off. Since the inverted signal XENB of ENB is set to a high potential level, the P-type transistor TP7 is also turned off. Therefore, in the second half period T2, the first output unit 51 does not operate, and only the second output unit 52 drives the drive target via the second electrostatic protection resistance element 31.

  As described above, the configuration example of FIG. 5 can suppress signal quality degradation such as overshoot, undershoot, and ringing by performing output impedance control similar to that of the configuration example of FIG.

  Further, in the configuration example of FIG. 5, since the sources of the transistors TN7 and TP7 used for switching the output impedance are both connected to the power supply (VDD or VSS), the output enable signal ENB is set to a high potential level. The absolute value of the gate bias voltage is always set to VDD. On the other hand, in the case of the transistor constituting the switch element of the first configuration example of FIG. 3 described above, the absolute value of the gate bias voltage is the case of the configuration example of FIG. Smaller.

  Generally, in a field effect transistor, when the gate length and the gate width are constant, the drain current increases as the absolute value of the gate bias voltage increases. Therefore, TN7 and TP7 in the configuration example of FIG. 5 have an advantage that a transistor having a gate width (channel width) smaller than that of the transistor configuring the switch element of the first configuration example in FIG. 3 can be used.

4). Layout of Integrated Circuit Device The layout of the integrated circuit device of this embodiment is as described below, for example.

  The first electrostatic protection resistance element 30 includes i (i is an integer satisfying 1 ≦ i <N) of the first to Nth (N is an integer of 2 or more) electrostatic protection resistance units. Consists of a resistance unit for electrostatic protection. The second electrostatic protection resistance element 31 is constituted by Ni resistance protection units excluding i electrostatic protection resistance units among the first to Nth electrostatic protection resistance units. Composed.

  When the direction parallel to one side of the integrated circuit device is the first direction D1, and the direction orthogonal to D1 is the second direction D2, the first to Nth electrostatic protection resistance units are drive circuits. Among the first to Nth electrostatic protection resistance units, the j + 1th (j is an integer satisfying 1 ≦ j <N) electrostatic protection resistance units Among the 1st to Nth electrostatic protection resistance units, the jth electrostatic protection resistance unit is disposed in the second direction D2.

  If it does in this way, two resistance elements for electrostatic protection with a desired resistance value can be easily formed by combining a resistance unit arbitrarily from a plurality of resistance units for electrostatic protection.

  FIG. 6 shows an example of the layout of the integrated circuit device of this embodiment. In this layout example, the first, second, and third resistance units 61, 62, and 63 (first to Nth electrostatic protection resistors in a broad sense) are used as the first to Nth electrostatic protection resistance units. Unit). The second resistor unit 62 (j + 1th electrostatic protection resistor unit in a broad sense) is arranged in the D2 direction of the first resistor unit 61 (jth electrostatic protection resistor unit in a broad sense), and the third The resistor unit 63 is arranged in the direction D2 of the second resistor unit 62. That is, the second resistance unit 62 is disposed between the first resistance unit 61 and the third resistance unit 63.

  The first electrostatic protection resistance element 30 is composed of two first and third resistance units 61 and 63 (i electrostatic protection resistance units in a broad sense). The protective resistance element 31 is composed of one second resistance unit 62 (Ni electrostatic resistance resistance units in a broad sense).

  As described above, according to the layout example of FIG. 6, two electrostatic protection resistance elements having different resistance values can be easily formed.

  Furthermore, according to this layout example, the electrostatic resistance of the integrated circuit device can be increased. The heat generated in the resistance element is proportional to the power consumed by the resistance element, and the power is inversely proportional to the resistance value if the voltage applied to the resistance element is constant. Accordingly, the first and third resistance units 61 and 63 having a low resistance value generate more heat than the second resistance unit 62 having a high resistance value. In addition, according to this layout example, the first and third resistance units 61 and 63 that are sources of more heat can be arranged apart from each other, so that an increase in temperature can be suppressed. In this way, the electrostatic resistance of the integrated circuit device can be increased.

5. Resistor Unit Layout FIG. 7 shows an example of the layout of the resistor unit of this embodiment. According to this layout example, the first, second and third resistance units 61, 62 and 63 are formed by the impurity regions DA1 to DA3.

  Of the contacts connecting the first metal line ML1 connected to the output terminal 20 and the impurity region DA1 of the first resistor unit 61, the contact formed closest to the drive circuit 10 is the first contact. Let it be CH1. Of the contacts connecting the first metal line ML1 and the impurity region DA2 of the second resistor unit 62, a contact formed at a position closest to the drive circuit 10 is referred to as a second contact CH2. Of the contacts connecting the first metal line ML1 and the impurity region DA3 of the third resistor unit 63, a contact formed at a position closest to the drive circuit 10 is referred to as a third contact CH3. In the above case, the first contact CH1 and the third contact CH3 are formed closer to the drive circuit 10 than the second contact CH2.

  Of the contacts connecting the second metal line ML2 connected to the first output node N1 of the drive circuit 10 and the impurity region DA1 of the first resistance unit 61, the contact is formed at a position farthest from the drive circuit 10. The contact is a fourth contact CH4. Of the contacts connecting the third metal line ML3 connected to the second output node N2 of the drive circuit 10 and the impurity region DA2 of the second resistance unit 62, the contact is formed at a position farthest from the drive circuit 10. The contact is a fifth contact CH5. Of the contacts connecting the second metal line ML2 and the impurity region DA3 of the third resistor unit 63, the contact formed farthest from the drive circuit 10 is a sixth contact CH6. When the distance between CH1 and CH4 is L1, the distance between CH2 and CH5 is L2, and the distance between CH3 and CH6 is L3, L1 <L2 and L3 <L2.

  According to the layout example of the resistance unit of FIG. 7 described above, the resistance value of the second resistance unit 62 can be made higher than the resistance values of the first and third resistance units 61 and 63. This is because the resistance value of each resistance unit is proportional to the distances L1, L2, and L3 between the respective contacts. Further, since the first and third resistance units 61 and 63 are connected in parallel, the resistance value is a combined resistance value in parallel connection.

  For example, by setting L1 = L3 and L2 = 10 × L1, and setting the widths of the impurity regions DA1 to DA3 and sheet resistance values (resistance values per unit area) to appropriate values, the first and third resistance units 61 , 63 can be set to 100Ω, and the resistance value of the second resistor unit 62 can be set to 1 kΩ. In this way, when the resistance values of the first and second electrostatic protection resistance elements 30 and 31 are R1 and R2, respectively, R1 = 50Ω and R2 = 1 kΩ can be obtained.

  As described above, according to this layout example of FIG. 7, two resistance elements for electrostatic protection having greatly different resistance values can be easily formed simply by changing the arrangement of the contacts.

  Furthermore, according to this layout example, the electrostatic resistance of the integrated circuit device can be increased. For example, the first resistance unit 61 will be described. Although not shown in FIG. 7, when the impurity region DA1 is P-type, an electrostatic protection diode can be provided between the impurity region DA1 and the high potential side power supply VDD. Further, when the impurity region DA1 is N-type, an electrostatic protection diode can be provided between the impurity region DA1 and the low potential side power source VSS.

  A case where impurity region DA1 is P-type will be described. A current generated by electrostatic discharge flows into the first resistance unit 61 from the output terminal 20 through the metal line ML1. At this time, until the discharge current reaches the resistance element region (region sandwiched between CH1 and CH4), a part of the current flows from the metal line ML1 to the impurity region DA1 through the contact, and further, the electrostatic protection diode Pass through to the high potential side power supply VDD. In this way, the current that actually flows through the resistance element region decreases.

  Next, the case where the impurity region DA1 is N-type will be described. In this case, the discharge current flows out from the integrated circuit device. A part of the current flows from the low-potential-side power supply VSS through the electrostatic protection diode to the impurity region DA1, and further to the output terminal 20 through the metal line ML1 through the contact without passing through the resistance element region. In this way, the current that actually flows through the resistance element region decreases.

  As described above, the current flowing through the resistance element region can be reduced regardless of whether the impurity region DA1 is P-type or N-type. The same applies to the third resistance unit 63.

  In the layout example of FIG. 7, the contact regions between the impurity region DA1 and the metal line ML1 and the contact regions between the impurity region DA3 and the metal line ML3 are provided for the first and third resistance units 61 and 63 having particularly low resistance values. Can be wide. Therefore, since the current flowing through the resistance element region can be further reduced, the electrostatic resistance of the integrated circuit device can be increased.

6). Data Line Driver Circuit FIG. 8 shows an example of a data line driver circuit including the integrated circuit device of this embodiment.

  The data line driver circuit 520 (drive circuit in a broad sense) includes a shift register 522, a data latch 524, a line latch 526, a DAC 528 (digital / analog converter circuit; a data voltage generation circuit in a broad sense), and an output buffer 529 (operational amplification). Circuit).

  The shift register 522 includes a plurality of flip-flops provided corresponding to the data lines and sequentially connected. When the shift register 522 holds the enable input / output signal EIO in synchronization with the clock signal CLK, the shift register 522 sequentially shifts the enable input / output signal EIO to the adjacent flip-flops in synchronization with the clock signal CLK.

  Image data DIO is input to the data latch 524 from the controller 540 in units of, for example, 18 bits (6 bits (gradation data) × 3 (each RGB color)). The data latch 524 latches the image data DIO in synchronization with the enable input / output signal EIO sequentially shifted by each flip-flop of the shift register 522.

  The line latch 526 latches the image data of one horizontal scanning unit latched by the data latch 524 in synchronization with the horizontal synchronization signal LP supplied from the controller 540.

  The DAC 528 generates an analog data voltage to be supplied to each data line. Specifically, the DAC 528 selects a gradation voltage based on digital image data from the line latch 526, and outputs an analog data voltage corresponding to the digital image data.

  The output buffer 529 buffers the data voltage from the DAC 528 and outputs it to the data line to drive the electro-optical panel. Specifically, the output buffer 529 includes the integrated circuit devices OPC1 to OPCn of this embodiment provided for each data line, and these integrated circuit devices OPC1 to OPCn convert the data voltage from the DAC 528 into an impedance. Then, the electro-optical panel is driven through the data lines S1 to Sn.

  In FIG. 8, the digital image data is converted from digital to analog and output to the data line via the output buffer 529. However, the analog video signal is sampled and held, and the output buffer 529 is Via the data line.

7). FIG. 9 shows an example of an electro-optical device including the integrated circuit device of this embodiment.

  The electro-optical device 510 includes an electro-optical panel 512 (LCD (Liquid Crystal Display) panel in a narrow sense), a data line driving circuit 520 (a source driver in a narrow sense), a scanning line driving circuit 530 (a gate driver in a narrow sense), A controller 540 and a power supply circuit 542 are included. Note that it is not necessary to include all these circuit blocks in the electro-optical device 510, and a part of the circuit blocks may be omitted.

  Here, the electro-optical panel 512 includes a plurality of scanning lines (gate lines in a narrow sense), a plurality of data lines (source lines in a narrow sense), and pixel electrodes specified by the scanning lines and the data lines. In this case, an active matrix liquid crystal device can be formed by connecting a thin film transistor TFT (Thin Film Transistor, switching element in a broad sense) to a data line and connecting a pixel electrode to the TFT.

  The gate electrode of TFTij is connected to the scanning line Gi, the source electrode of TFTij is connected to the data line Sj, and the drain electrode of TFTij is connected to the pixel electrode PEij. Between the pixel electrode PEij and the counter electrode VCOM (common electrode) facing the pixel electrode PEij with a liquid crystal element (electro-optical material in a broad sense), a liquid crystal capacitor CLij (liquid crystal element) and an auxiliary capacitor CSij are provided. Is formed. Then, liquid crystal is sealed between the active matrix substrate on which the TFTij, the pixel electrode PEij and the like are formed, and the counter substrate on which the counter electrode VCOM is formed, and according to the applied voltage between the pixel electrode PEij and the counter electrode VCOM. The transmittance of the pixel is changed.

  Note that the voltage applied to the counter electrode VCOM is generated by the power supply circuit 542. Further, the counter electrode VCOM may be formed in a strip shape so as to correspond to each scanning line, without being formed on one surface on the counter substrate.

  The data line driving circuit 520 uses the driving circuit 10 in FIG. 1 as a circuit for driving the data lines. The data line driving circuit 520 drives the data lines S1 to Sn of the electro-optical panel 512 based on the image data. On the other hand, the scanning line driving circuit 530 sequentially scans and drives the scanning lines G1 to Gm of the electro-optical panel 512.

  The controller 540 controls the data line driving circuit 520, the scanning line driving circuit 530, and the power supply circuit 542 according to the contents set by a host such as a central processing unit (CPU) (not shown).

  More specifically, the controller 540 sets, for example, an operation mode and supplies an internally generated vertical synchronizing signal and horizontal synchronizing signal to the data line driving circuit 520 and the scanning line driving circuit 530, and a power supply circuit. For 542, the polarity inversion timing of the voltage of the counter electrode VCOM is controlled.

  The power supply circuit 542 generates various voltages (grayscale voltages) necessary for driving the electro-optical panel 512 and the voltage of the counter electrode VCOM based on a reference voltage supplied from the outside.

  In FIG. 9, the electro-optical device 510 includes the controller 540, but the controller 540 may be provided outside the electro-optical device 510. Alternatively, the host may be included in the electro-optical device 510 together with the controller 540. Further, part or all of the data line driver circuit 520, the scan line driver circuit 530, the controller 540, and the power supply circuit 542 may be formed on the electro-optical panel 512.

  The electro-optical panel 512 is not limited to a liquid crystal panel, and may be a panel using a light emitting element such as an organic EL (Electro Luminescence) or an inorganic EL.

8). Electronic Device FIG. 10 shows an example of an electronic device (cellular phone) including the electro-optical device of this embodiment. Note that the electronic device of the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, or a portable information terminal.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the controller 540 in the YUV format.

  The mobile phone 900 includes an electro-optical panel 512. The electro-optical panel 512 is driven by a source driver 520 (data line driving circuit in a broad sense) and a gate driver 530 (scanning line driving circuit in a broad sense). The electro-optical panel 512 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels.

  The controller 540 is connected to the source driver 520 and the gate driver 530 and supplies gradation data in RGB format to the source driver 520.

  The power supply circuit 542 is connected to the source driver 520 and the gate driver 530, and supplies a driving power supply voltage to each driver. Further, the counter electrode voltage VCOM is supplied to the counter electrode of the electro-optical panel 512.

  Host 940 is connected to controller 540. The host 940 controls the display controller 540. The host 940 can supply the gradation data received via the antenna 960 to the controller 540 after demodulating the modulation / demodulation unit 950. The controller 540 displays an image on the electro-optical panel 512 by the source driver 520 and the gate driver 530 based on the gradation data.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the electro-optical panel 512 based on operation information from the operation input unit 970.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. In addition, the configurations and operations of the integrated circuit device, the electro-optical device, and the electronic apparatus are not limited to those described in this embodiment, and various modifications can be made.

The basic structural example of this embodiment. The signal waveform example of a drive signal. The 1st example of composition of this embodiment. The 2nd structural example of this embodiment. Second more detailed configuration example. 6 is a layout example of an integrated circuit device. A layout example of a resistance unit. An example of a data line drive circuit. An example of an electro-optical device. An example of an electronic device.

Explanation of symbols

IA input signal, N1 first output node, N2 second output node,
R1, R2 resistance values of the first and second electrostatic protection resistance elements,
10 drive circuit, 20 output terminals, 30, 31 first and second resistance elements for electrostatic protection,
40 drive amplifiers, 50 differential units, 51, 52 first and second output units,
61, 62, 63 1st, 2nd, 3rd resistance unit,
510 electro-optical device, 512 electro-optical panel, 520 data line driving circuit,
522 shift register, 524 data latch, 526 line latch,
528 DAC, 529 output buffer, 530 scanning line driving circuit,
540 controller, 542 power supply circuit, 560 display driver,
900 mobile phone, 910 camera module, 940 host, 950 modem,
960 antenna, 970 operation input section

Claims (9)

A driving circuit for driving a driving target connected to an output terminal of the integrated circuit device;
A first resistance element for electrostatic protection provided between a first output node of the drive circuit and the output terminal;
A second electrostatic protection resistance element provided between the second output node of the drive circuit and the output terminal, the resistance value of which is larger than the first electrostatic protection resistance element;
The drive circuit is
In the first half of the drive period, the drive target is driven via the first electrostatic protection resistance element and the second electrostatic protection resistance element, and in the second half of the drive period, the first Driving the drive object via the second electrostatic protection resistance element without going through the electrostatic protection resistance element ;
The first electrostatic protection resistance element is:
Of the first to Nth (N is an integer of 2 or more) electrostatic protection resistance units, i (i is an integer satisfying 1 ≦ i <N) electrostatic protection resistance units,
The second electrostatic protection resistance element is:
Of the first to N-th electrostatic protection resistance units, N-i electrostatic protection resistance units excluding the i electrostatic protection resistance units are configured.
The first to Nth electrostatic protection resistance units are formed of impurity regions;
When a direction parallel to one side of the integrated circuit device is a first direction and a direction orthogonal to the first direction is a second direction,
The first to Nth electrostatic protection resistance units are:
Arranged in the first direction of the drive circuit;
Of the first to Nth electrostatic protection resistor units, the j + 1th electrostatic protection resistor unit (j is an integer satisfying 1 ≦ j <N) is
An integrated circuit device, wherein the integrated circuit device is arranged in the second direction of the jth electrostatic protection resistance unit among the first to Nth electrostatic protection resistance units . In claim 1 ,
As the first to Nth electrostatic protection resistance units, there are provided first, second and third resistance units,
The first electrostatic protection resistance element is constituted by the first and third resistance units,
The second electrostatic protection resistance element is constituted by the second resistance unit having a higher resistance value than the first and third resistance units ,
The first, second and third resistance units are arranged in the first direction of the drive circuit;
The second resistance unit is disposed in the second direction of the first resistance unit;
The integrated circuit device, wherein the third resistor unit is disposed in the second direction of the second resistor unit . In claim 2 ,
Of the contacts connecting the first metal line connected to the output terminal of the integrated circuit device and the impurity region of the first resistance unit, a contact formed closest to the drive circuit is the first. Contact
Of the contacts connecting the first metal line and the impurity region of the second resistor unit, a contact formed at a position closest to the drive circuit is a second contact.
Of the contacts connecting the first metal line and the impurity region of the third resistor unit, when the contact formed at the closest position from the drive circuit is the third contact,
The first contact and the third contact are formed closer to the drive circuit than the second contact,
Of the contacts connecting the second metal line connected to the first output node of the drive circuit and the impurity region of the first resistance unit, a contact formed at a position farthest from the drive circuit As the fourth contact,
Of the contacts connecting the third metal line connected to the second output node of the drive circuit and the impurity region of the second resistance unit, a contact formed at a position farthest from the drive circuit As the fifth contact,
Of the contacts connecting the second metal line and the impurity region of the third resistor unit, a contact formed at a position farthest from the drive circuit is a sixth contact,
The distance between the first contact and the fourth contact is L1, the distance between the second contact and the fifth contact is L2, and the distance between the third contact and the sixth contact. Is L3,
An integrated circuit device, wherein L1 <L2 and L3 <L2. In any one of Claims 1 thru | or 3 ,
The drive circuit is
A drive amplifier,
A first switch element provided between an output node of the drive amplifier and the first output node;
A second switch element provided between the output node and the second output node of the drive amplifier;
The first switch element is in an on state in the first half period of the driving period, and is in an off state in the second half period of the driving period,
The integrated circuit device, wherein the second switch element is in an ON state throughout the first half period and the second half period of the driving period. In any one of Claims 1 thru | or 3 ,
The drive circuit is
A differential section;
An output of the differential section connected to its input, and a first output section whose output is output to the first output node;
An output of the differential unit is connected to its input, and a second output unit whose output is output to the second output node;
In the first half period of the driving period, both the first output unit and the second output unit are set in an output enable state,
In the second half of the driving period, the integrated circuit device is characterized in that the first output unit is set in an output disabled state and the second output unit is set in an output enabled state. In claim 5 ,
The first output unit includes:
A first N-type transistor having a drain connected to the first output node and a gate connected to the first differential output node of the differential section;
A second N-type transistor whose drain is connected to the source of the first N-type transistor, whose output enable signal is input to its gate, and whose source is connected to the low-potential-side power supply;
A first P-type transistor having a drain connected to the first output node and a gate connected to a second differential output node of the differential section;
A second P-type transistor having a drain connected to the source of the first P-type transistor, an inverted signal of the output enable signal input to the gate, and a source connected to a high-potential side power supply. ,
The second output unit includes:
A third N-type transistor whose drain is connected to the second output node, whose gate is connected to the first differential output node of the differential section, and whose source is connected to the low-potential side power supply When,
A third P-type transistor whose drain is connected to the second output node, whose gate is connected to the second differential output node of the differential section, and whose source is connected to the high potential side power supply Including
In the first half period of the driving period, the output enable signal is set to a high potential level, and in the second half period of the driving period, the output enable signal is set to a low potential level. . In any one of Claims 1 thru | or 6 .
The integrated circuit device, wherein the drive target is an electro-optical panel. An electro-optical device comprising the integrated circuit device according to claim 7 . An electronic apparatus comprising the electro-optical device according to claim 8 .

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