JP5184132B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of preventing a chip crack in a wire bonding process to increase a manufacturing yield in a semiconductor apparatus in which a plurality of semiconductor chips are laminated in multiple stages. <P>SOLUTION: A dummy bump 16 is formed on a non-connected pad electrode 10N to which a bonding wire 11 of a lower stage chip 3D is not connected. Thereby, when the bonding wire 11 is connected to a pad electrode 10 of an upper stage chip 3U positioned on the non-connected pad electrode 10N of the lower stage chip 3D, the dummy bump 16 formed on the non-connected pad electrode 10N of the lower stage chip 3D supports the upper stage chip 3U to reduce the deflection of the upper stage chip 3U, and a crack generated in the pad electrode 10 of the upper stage chip 3U can be prevented. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device in which a plurality of semiconductor chips are stacked in multiple stages and a technique effective when applied to the manufacturing thereof.

  A semiconductor device having a laminated structure in which a plurality of semiconductor chips are stacked has been put into practical use, and various structures and manufacturing methods for having high reliability and functionality have been proposed.

  For example, Japanese Patent Laid-Open No. 2004-319892 (Patent Document 1) discloses that after a first semiconductor chip is mounted on a substrate, plasma treatment is performed, and after a second semiconductor chip is mounted on the first semiconductor chip, again. A technique for preventing peeling of a resin material by performing a plasma treatment is described.

Japanese Patent Laid-Open No. 2006-156909 (Patent Document 2) has a first semiconductor memory chip and a second semiconductor memory chip mounted on a surface of a mounting substrate via a spacer, and the surface of the mounting substrate. In addition, electrodes provided separately corresponding to bonding pads to which selection signals of the first semiconductor memory chip and the second semiconductor memory chip are supplied, and a plurality of bondings to which the same signal except for the selection signal is supplied respectively. A multi-chip module having a plurality of electrodes provided in common corresponding to pads is disclosed.
JP 2004-319892 A JP 2006-156909 A

  In recent years, large-capacity memory packages having a stacked structure in which a plurality of memory chips are stacked have been put into practical use. The present inventors have developed a memory package having a structure in which memory chips are stacked in multiple stages via spacers. In this memory package, a plurality of pad electrodes are provided on the side edge of each memory chip, and the plurality of pad electrodes are electrically connected to a plurality of lead electrodes provided on the main surface of the wiring board by bonding wires, respectively. Has been.

  However, according to studies by the present inventors, it has been found that there are various technical problems described below in the memory package.

  The inventors of the present invention manufacture a memory package having a stacked structure in which memory chips having a thickness of 50 μm or more are stacked in four stages (7 stages including a spacer). However, in order to cope with high integration (higher function or higher performance) of semiconductor devices, there is an increasing demand for a memory package having a stacked structure with an increased number of stages. Accordingly, the present inventors also considered a reduction in the thickness of the semiconductor device, and further reduced the thickness of the memory chip to 25 μm, and a memory having a stacked structure in which the memory chips are stacked in eight stages (15 stages including a spacer). Considered the package.

  However, it has been clarified that when the thickness of the memory chip is 25 μm, a crack occurs in the pad electrode to which the bonding wire is connected, resulting in a connection failure between the bonding wire and the pad electrode. In addition, when a crack occurs in the pad electrode, the crack further spreads in subsequent manufacturing processes and the wiring adjacent to the pad electrode is cut to cause a product defect. For example, in a molding process in which a plurality of semiconductor chips stacked in multiple stages are sealed with a resin sealing body, cracks spread due to pressure when a thermosetting insulating resin is injected into a molding die, and thermosetting in the molding process described above. The crack also spreads due to the warp of the semiconductor chip due to the heat treatment for curing the insulating insulating resin or the reflow treatment in the process of connecting the solder bumps to the back surface of the wiring board (the reliability of the semiconductor device is reduced).

  Although a spacer is provided between the upper chip and the lower chip, since a plurality of pad electrodes are provided on the side edge of the main surface of the lower chip, no spacer is provided in that portion. That is, there is a space (overhang) between the upper chip and the lower chip where no spacer is provided, in which the bonding wire is connected to the pad electrode of the lower chip, and a bonding wire loop is formed. doing. The crack is generated in the pad electrode of the upper chip located above the pad electrode to which the bonding wire is not connected (hereinafter simply referred to as an unconnected pad electrode) among the pad electrodes of the lower chip. It does not occur in the pad electrode of the upper chip located above the pad electrode to which the bonding wire is connected. From this, it is considered that when the thickness of the memory chip is reduced to 25 μm, the rigidity of the memory chip is lowered, the upper memory chip is bent by a load during wire bonding, and a crack is generated in the pad electrode.

  FIGS. 19A and 19B are schematic views illustrating how the upper chip bends. FIG. 19A is a cross-sectional view seen from the side surface in the case where all the pad electrodes provided on one side edge of the lower chip are unconnected pad electrodes, and FIG. 19B is one side of the lower chip. It is the schematic diagram seen from the side surface in case one of the pad electrodes provided at the edge is an unconnected pad electrode. A lower chip 52 is mounted on the main surface of the wiring substrate 51, a spacer 53 is stacked on the main surface of the lower chip 52, and an upper chip 54 is stacked on the main surface of the spacer 53.

  As shown in FIG. 19A, when all the pad electrodes provided on one side edge of the lower chip 52 are unconnected pad electrodes, the entire overhang portion of the upper chip 54 bends, so the upper chip A crack is generated in a part or all of the pad electrode provided on the side edge of one side of 54. Further, as shown in FIG. 19B, even if there is only one unconnected pad electrode on one side edge of the lower chip 52, the pad of the upper chip 54 directly above the unconnected pad electrode. When the bonding wire 55 is connected to the electrode, the upper chip 54 bends at that portion, so that a crack occurs in the pad electrode of the upper chip 54 directly above the unconnected pad electrode.

  When the thickness of the memory chip is 50 μm or more, the semiconductor chip itself is rigid and difficult to bend, so that it is considered that no cracks occur in the pad electrode of the upper chip. Even if the thickness of the memory chip is 25 μm, if a bonding wire connected to the pad electrode of the lower chip is formed below the pad electrode of the upper chip, the pad electrode of the lower chip is formed. It is considered that the upper chip is not easily bent due to the bonding wire to be connected, and no crack is generated in the pad electrode of the upper chip.

  At present, the memory chip is mounted on the wiring board or the spacer via an adhesive layer, for example, a DAF (Die Attach Film) having a thickness of about 10 μm. The thickness of the DAF is, for example, 30 μm or more. As a result, the bending strength of the memory chip can be improved. However, in a semiconductor device in which a plurality of memory chips are stacked in multiple stages, when the thickness of the DAF is increased, the entire thickness of the semiconductor device is also increased, making it difficult to cope with the reduction in thickness of the semiconductor device.

  An object of the present invention is to provide a technique capable of realizing high integration of a semiconductor device.

  Another object of the present invention is to provide a technique capable of realizing a thin semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  Another object of the present invention is to provide a technique capable of preventing a chip crack in a wire bonding process and improving a manufacturing yield in a semiconductor device in which a plurality of semiconductor chips are stacked in multiple stages.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, typical ones will be briefly described as follows.

  (1) A first semiconductor chip having a main surface on which a plurality of first pad electrodes are formed and mounted on the main surface of the wiring board; a spacer stacked on the main surface of the first semiconductor chip; A second semiconductor chip having a main surface on which a plurality of second pad electrodes are formed and stacked on the spacer; a first pad electrode formed on the main surface of the first semiconductor chip; and a main surface of the wiring substrate. A plurality of first wires for electrically connecting the formed electrodes, a second pad electrode formed on the main surface of the second semiconductor chip, and an electrode formed on the main surface of the wiring board are electrically connected And a sealing body that seals the first semiconductor chip, the spacer, the second semiconductor chip, the plurality of first wires, and the plurality of second wires. The plurality of first pad electrodes have unconnected pad electrodes to which the first wires are not electrically connected, and a dummy pattern that supports the second semiconductor chip is formed on the unconnected pad electrodes. Alternatively, the circuit element portion of the first semiconductor chip excluding the region where the plurality of first pad electrodes are formed is covered by the spacer.

  (2) A step of mounting a first semiconductor chip having a main surface on which a plurality of first pad electrodes having unconnected pad electrodes are formed on a wiring board; and a plurality of steps formed on the main surface of the first semiconductor chip. Electrically connecting the first pad electrode and the plurality of electrodes formed on the main surface of the wiring board with a plurality of first wires, forming a dummy pattern on the unconnected pad electrode, A step of laminating a spacer on one semiconductor chip, a step of laminating a second semiconductor chip having a main surface on which a plurality of second pad electrodes are formed, and a main surface of the second semiconductor chip. Electrically connecting a plurality of second pad electrodes and a plurality of electrodes formed on the main surface of the wiring board with a plurality of second wires, respectively, a first semiconductor chip, a spacer, a second semiconductor chip, a plurality of First wire And a plurality of second wire is a method of manufacturing a semiconductor device including the step of sealing with resin. The dummy pattern is formed of the same material as the plurality of first wires in a series of wire bonding in which the plurality of first wires are sequentially formed. The dummy pattern is formed by applying a resin on the unconnected pad electrode by a potting method and then performing a heat treatment. The dummy pattern is formed by applying a paste material on the unconnected pad electrode and then performing a heat treatment.

  (3) A step of mounting a first semiconductor chip having a main surface on which a plurality of first pad electrodes including unconnected pad electrodes are formed on a wiring board, and a plurality of formed on the main surface of the first semiconductor chip. A step of electrically connecting the first pad electrode and the plurality of electrodes formed on the main surface of the wiring board with a plurality of first wires, respectively, and laminating a spacer having a convex portion on the first semiconductor chip A step of stacking a second semiconductor chip having a main surface on which a plurality of second pad electrodes are formed on the spacer, and a plurality of second pad electrodes formed on the main surface of the second semiconductor chip; A step of electrically connecting a plurality of electrodes formed on the main surface of the wiring board with a plurality of second wires, respectively, a first semiconductor chip, a spacer, a second semiconductor chip, a plurality of first wires, and a plurality of first wires; 2 wires are sealed with resin A method of manufacturing a semiconductor device having a step. The spacer is stacked on the first semiconductor chip so that the convex portion of the spacer covers the unconnected pad electrode. The spacer covers the circuit element portion of the first semiconductor chip except for the region where the plurality of first pad electrodes are formed.

  Among the inventions disclosed in the present application, the effects obtained by one embodiment will be briefly described as follows.

  By preventing chip cracks in the wire bonding process, it is possible to improve the manufacturing yield of a semiconductor device in which a plurality of semiconductor chips are stacked in multiple stages.

  In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related.

  Further, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, the constituent elements (including element steps and the like) are not necessarily essential unless particularly specified and apparently essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In the drawings used in the present embodiment, hatching may be added even in a plan view for easy understanding of the drawings. In this embodiment, the term “wafer” mainly refers to a Si (Silicon) single crystal wafer, but not only to this, but also to form an SOI (Silicon On Insulator) wafer and an integrated circuit thereon. It refers to an insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A semiconductor device in which a plurality of semiconductor chips according to the first embodiment are stacked in multiple stages will be described with reference to FIGS. 1 is a cross-sectional view of a main part for explaining the configuration of the semiconductor device, FIG. 2 is a cross-sectional view of a main part in which the region A of FIG. 1 is enlarged, and FIGS. FIG. 2 is a plan view of the main part of FIG. 2 and a plan view of the main part of the line CC ′.

  As shown in FIGS. 1 to 3, the semiconductor device 1 </ b> A includes eight stages of memory chips 3 a, 3 b, 3 c on the main surface 2 x side of the main surface 2 x and the back surface 2 y located on the opposite sides of the wiring substrate 2. , 3d, 3e, 3f, 3g and 3h and the controller chip 4 are stacked and mounted, and a plurality of ball-like solder bumps 5 are arranged on the back surface 2y side of the wiring board 2 as external connection terminals. . Among the above eight-stage memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h, a memory chip located in the upper stage (hereinafter sometimes simply referred to as an upper stage chip) and a memory chip located in the lower stage Spacers 6 a, 6 b, 6 c, 6 d, 6 e, 6 f and 6 g are respectively arranged between them (hereinafter sometimes simply referred to as a lower chip). In the following description, when only the upper chip or the lower chip is described, one spacer is selected from the eight memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h. It refers to two memory chips that are positioned above and below.

  On the main surface 2x of the wiring board 2, a first-stage memory chip 3a is mounted via a DAF 7. The planar shape intersecting with the thickness direction is a quadrangle, and the thickness is, for example, 25 μm. The thickness of DAF 7 is, for example, 10 μm.

  On the main surface of the memory chip 3a, a circuit element portion and a plurality of pad electrodes (first pad electrodes) 10 respectively electrically connected to the circuit element portion are formed.

  On the main surface of the memory chip 3a, a first-stage spacer 6a is laminated via a DAF 8. The planar shape intersecting the thickness direction is a quadrangle, and the planar dimension is smaller than the planar dimension of the memory chip 3a. The thickness of the spacer 6a is such that the electrode (lead electrode) 9 disposed on the main surface of the wiring board 2 and the pad electrode (first pad electrode) 10 disposed on the main surface (first main surface) of the memory chip 3a. In the first embodiment, for example, the thickness is set to 40 μm. The thickness of DAF 8 is, for example, 10 μm. The spacer 6a is made of, for example, single crystal silicon.

  Furthermore, the second-stage memory chip 3b is stacked on the main surface of the spacer 6a via the DAF 7. The planar shape of the memory chip 3b, its thickness, the arrangement of pad electrodes, and the like are the same as those of the memory chip 3a. Further, on the main surface of the memory chip 3b, a circuit element portion and a plurality of pad electrodes (second pad electrodes) 10 respectively electrically connected to the circuit element portion are formed in the same manner as the memory chip 3a. ing.

  The planar dimension of the spacer 6a is made smaller than the planar dimension of the memory chip 3a, and the pad electrode 10 is disposed on the side edge of the main surface of the memory chip 3a. For this reason, the side edge portion of the second-stage memory chip 3b is overhanging. The distance from the end of the spacer 6a to the end of the memory chip 3b, that is, the dimension over which the memory chip 3b overhangs (the dimension indicated by the symbol L1 in FIG. 2) is 3 μm or more. The dimension up to the pad electrode (second pad electrode) 10 (the dimension indicated by the symbol L2 in FIG. 2) arranged on the main surface (second main surface) of 3b is 2 μm or more.

  The planar shape, thickness, and pad electrode arrangement of the third to eighth memory chips 3c, 3d, 3e, 3f, 3g and 3h are the same as those of the first memory chip 3a. The planar shapes and thicknesses of the second to seventh stage spacers 6b, 6c, 6d, 6e, 6f and 6g are the same as those of the first stage spacer 6a, and therefore, repeated description is omitted here. To do. The controller chip 4 is mounted on the main surface of the eighth-stage memory chip 3h via the DAF 7. The planar shape intersecting the thickness direction is a quadrangle, and the planar dimension is smaller than the planar dimension of the memory chip 3h. The thickness of the controller chip 4 is, for example, 25 μm.

  The memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h, and the controller chip 4 are not limited thereto, but are formed on a semiconductor substrate mainly made of single crystal silicon and a main surface of the semiconductor substrate. A plurality of semiconductor elements, a multilayer wiring layer in which a plurality of insulating layers and wiring layers are stacked on the main surface of the semiconductor substrate, and a surface protection film formed so as to cover the multilayer wiring layer It has become. The insulating layer is made of, for example, a silicon oxide film. The wiring layer is formed of a metal film whose main component is, for example, aluminum, tungsten, or copper. The surface protective film is formed of a multilayer film in which an inorganic insulating film such as a silicon oxide film or a silicon nitride film and an organic insulating film are stacked.

  A plurality of pad electrodes 10 are arranged along one direction (the X direction shown in FIG. 3) on the side edges of the main surfaces of the memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h. . These pad electrodes 10 are composed of the uppermost wiring of the multilayer wiring layers of the memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h, and the memory chips 3a, 3b, 3c, 3d, 3e, 3f. , 3g and 3h are exposed through openings formed corresponding to the respective pad electrodes 10. Spacers 6b, 6c, 6d, 6e, 6f and 6g are respectively mounted on the main surfaces of the memory chips 3a, 3b, 3c, 3d, 3e, 3f and 3g inside the region where the pad electrodes 10 are arranged. Yes. The pad electrode 10 is, for example, a quadrangle whose one side has a dimension of 0.07 to 0.1 μm.

  On the side edge of the main surface of the controller chip 4, another direction orthogonal to one direction along which the plurality of pad electrodes 10 of the memory chips 3 a, 3 b, 3 c, 3 d, 3 e, 3 f, 3 g and 3 h are along (shown in FIG. 3) A plurality of pad electrodes 13 are arranged along the (Y direction). These pad electrodes 13 are composed of the uppermost wiring of the multilayer wiring layers of the controller chip 4 and are exposed through openings formed in the surface protective film of the controller chip 4 corresponding to the respective pad electrodes 13. . The pad electrode 13 is, for example, a quadrangle whose one side has a dimension of 0.07 to 0.1 μm.

  The wiring board 2 has a quadrangular planar shape that intersects the thickness direction. The wiring board 2 is not limited to this, but mainly includes a core material, a protective film formed so as to cover the main surface of the core material, and a back surface located on the opposite side of the main surface of the core material. The core material has, for example, a multilayer wiring structure having wirings on the main surface, the back surface, and the inside of the core material. Each insulating layer of the core material is formed of, for example, a highly elastic resin substrate in which glass fiber is impregnated with epoxy or polyimide resin. Each wiring layer of the core material is formed of, for example, a metal film containing copper as a main component. The protective film on the main surface of the core material is formed mainly for the purpose of protecting the wiring formed on the uppermost layer of the core material.

  The main surface 2x of the wiring board 2 includes the memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h, and the wiring board in the region between the end of the controller chip 4 and the end of the wiring board 2. A plurality of lead electrodes 9 in one row are arranged along each of the two sides. These lead electrodes 9 are constituted by a part of each of a plurality of uppermost layer wirings formed on the core material of the wiring board 2 and are formed on the protective film on the main surface of the core material corresponding to each lead electrode 9. It is exposed through the opening.

  A plurality of back surface pad electrodes 14 are arranged on the back surface 2 y of the wiring board 2. These back surface pad electrodes 14 are constituted by a part of each of a plurality of lowermost layer wirings formed on the core material of the wiring board 2 and are formed on the protective film on the back surface of the core material corresponding to each back surface pad electrode 14. The exposed opening is exposed. The plurality of uppermost layer wirings and the plurality of lowermost layer wirings formed in the core material are electrically connected to each other by wirings formed in a plurality of through holes penetrating the core material.

  A plurality of pad electrodes 10 arranged on the main surface of the first-stage memory chip 3a and a plurality of lead electrodes 9 arranged on the main surface 2x of the wiring board 2 are electrically connected by a plurality of bonding wires 11, respectively. It is connected. Similarly, the plurality of pad electrodes 10 arranged on the main surfaces of the second to eighth memory chips 3b, 3c, 3d, 3e, 3f, 3g and 3h and the main surface 2x of the wiring board 2 are arranged. A plurality of lead electrodes 9 are electrically connected to each other by a plurality of bonding wires 11. Further, the plurality of pad electrodes 13 arranged on the main surface of the controller chip 4 and the plurality of lead electrodes 9 arranged on the main surface 2x of the wiring board 2 are electrically connected by a plurality of bonding wires 11 respectively. ing. For the bonding wire 11, for example, a gold wire of 15 to 20 μmφ is used. The bonding wires 11 are formed on the main surfaces of the memory chips 3a, 3b, 3c, 3d, 3e, 3g, 3g, and 3h, and the controller chip 4 by, for example, nail head bonding (ball bonding) using ultrasonic vibration in combination with thermocompression bonding. Are connected to the pad electrodes 10 and 13 arranged in the. Further, it is connected to the lead electrode 9 disposed on the main surface 2x of the wiring board 2.

  The memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h, the controller chip 4 and the bonding wires 11 are sealed by a resin sealing body 15 formed on the main surface 2x of the wiring board 2. Yes. For the purpose of reducing the stress, the resin sealing body 15 is formed of an epoxy thermosetting insulating resin to which, for example, a phenolic curing agent, silicone rubber, and a large number of fillers (for example, silica) are added. The resin sealing body 15 is formed by, for example, a transfer mold method. The thickness of the semiconductor device 1A sealed by the resin sealing body 15 (the dimension indicated by the symbol L3 in FIG. 1) is, for example, about 1.4 mm.

  A plurality of solder bumps 5 are electrically and mechanically connected to the plurality of back surface pad electrodes 14 formed on the back surface 2y of the wiring board 2, respectively. As the solder bump 5, a solder bump having a lead-free solder composition that does not substantially contain lead, for example, a solder bump having a Sn-1 [wt%] Ag-0.5 [wt%] Cu composition is used.

  By the way, as described with reference to FIGS. 1 to 3, in the semiconductor device 1A, the main surfaces of the first to eighth memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h, respectively. The plurality of pad electrodes 10 arranged on the substrate 10 and the plurality of lead electrodes 9 arranged on the main surface 2x of the wiring board 2 are electrically connected by a plurality of bonding wires 11, respectively. However, the bonding wires 11 are not connected to the plurality of pad electrodes 10 arranged on the main surfaces of the memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h, and the wiring board 2 is not connected. There are unconnected pad electrodes, such as chip select pins, which are not electrically connected to the lead electrodes 10 disposed on the main surface 2x. Each of the memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h has about 2 to 3 unconnected pad electrodes to which the bonding wires 11 are not connected. Therefore, as described above, if there is an unconnected pad electrode to which the bonding wire 11 is not connected to the lower chip, the upper chip is connected when the bonding wire 11 is connected to the pad electrode 10 of the upper chip positioned thereabove. This causes a problem that cracks occur in the pad electrode 10 of the upper chip and the wiring layer adjacent to the pad electrode 10. Therefore, in the present invention, means for supporting the upper chip is provided on the unconnected pad electrode to which the bonding wire 11 is not connected.

  Next, a dummy pattern for supporting the upper chip provided on the unconnected pad electrode arranged on the main surface of the lower chip according to the first embodiment will be described. 4A is an enlarged cross-sectional view of the main part of the upper and lower chip using the bonding wire as a supporting means, and FIG. 4B is an enlarged cross-sectional view of the main part of the upper and lower chip using the dummy bump as a supporting means. It is.

  As shown in FIG. 4A, when the bonding wire 11 is connected to the pad electrode 10 of the lower chip 3D, the bonding wire 11 is supported and the upper chip 3U located on the pad electrode 10 is supported. Since the upper chip 3U does not bend when the bonding wire 11 is connected to the pad electrode 10, the pad electrode 10 of the upper chip 3U is unlikely to crack.

  Further, as shown in FIG. 4B, dummy bumps 16 are arranged as dummy patterns for supporting the upper chip 3U on the unconnected pad electrodes 10N to which the bonding wires 11 of the lower chip 3D are not connected. Since the dummy bump 16 is supported, the upper chip 3U does not accumulate when the bonding wire 11 is connected to the pad electrode 10 of the upper chip 3U located above the unconnected pad electrode 10N. 10 is less likely to crack. The height of the dummy bump 16 is the same as or lower than the total thickness of the spacer 6 and the DAF 8 between the lower chip 3D and the spacer 6. For example, a gold wire is used as the dummy bump 16, and the dummy bump 16 is formed on the unconnected pad electrode 10 </ b> N by the nail head bonding (ball bonding) method in which ultrasonic vibration is used in combination with the thermocompression bonding similarly to the bonding wire 11. It is only electrically connected to the electrode (lead electrode) 9 of the wiring board.

  5A, 5B, 5C, and 5D are a plan view and a main part of a main part showing a part of a semiconductor device when memory chips are sequentially stacked from the first stage to the fourth stage, respectively. It is sectional drawing.

  As shown in FIG. 5A, dummy bumps 16 are connected to unconnected pad electrodes 10N of the first-stage memory chip 3a, for example, chip select pins. The height of the dummy bump 16 is equal to or lower than the total thickness (for example, 35 μm) of the thickness of the spacer 6a (for example, 25 μm) and the thickness of the DAF 8 (for example, 10 μm).

  As shown in FIG. 5B, the pad electrode 10 of the second-stage memory chip 3b stacked on the main surface of the first-stage memory chip 3a via the spacer 6a, the first-stage memory A bonding wire 11 is connected to the pad electrode 10 located immediately above the unconnected pad electrode 10N of the chip 3a. When the bonding wires 11 are connected, the dummy bumps 16 connected to the unconnected pad electrodes 10N of the first-stage memory chip 3a are supported to prevent the second-stage memory chip 3b from being bent.

  As shown in FIG. 5C, the first-stage memory chip 3a is positioned directly above the unconnected pad electrode 10N and stacked on the main surface of the second-stage memory chip 3b via the spacer 6b. Dummy bumps 16 are connected to unconnected pad electrodes 10N of the third-stage memory chip 3c, for example, chip select pins. The height of the dummy bump 16 is equal to or lower than the total thickness (for example, 35 μm) of the thickness of the spacer 6 b (for example, 25 μm) and the thickness of the DAF 8 (for example, 10 μm). When this dummy bump 16 is connected, the loop portion of the bonding wire 11 connected to the pad electrode 10 of the second-stage memory chip 3b is supported, and the deflection of the third-stage memory chip 3c can be prevented.

  As shown in FIG. 5D, the pad electrode 10 of the fourth-stage memory chip 3d stacked on the main surface of the third-stage memory chip 3c via the spacer 6c, and the first-stage memory A bonding wire 11 is connected to the unconnected pad electrode 10N of the chip 3a and the pad electrode 10 located immediately above the unconnected pad electrode 10N of the third-stage memory chip 3c. When the bonding wires 11 are connected, the dummy bumps 16 connected to the unconnected pad electrodes 10N of the third-stage memory chip 3c are supported, and the deflection of the fourth-stage memory chip 3d can be prevented.

  As shown in FIGS. 5A to 5D, when the memory chips 3a, 3b, 3c and 3d are stacked in multiple stages, the loop portion of the dummy bump 16 or the bonding wire 11 serves as a support. Deflection of the memory chips 3b, 3c and 3d can be prevented. Therefore, no matter which memory chip 3a, 3b, 3c and 3d the unconnected pad electrode 10N is located in, and where the unconnected pad electrode 10N is arranged in each memory chip 3a, 3b, 3c and 3d. The deflection of the memory chips 3b, 3c and 3d can be prevented.

  As the structure of the dummy bump 16, a flat bump, a normal bump (pull cut bump), a reverse bump (T bump), a ball-shaped bump, or the like can be used. FIGS. 6A, 6B, and 6C are structural diagrams of flat bumps, normal bumps, and reverse bumps, respectively.

  The flat bump shown in FIG. 6A can be formed as follows, for example. First, a wire end ball formed at the tip of the capillary is pressed against the pad electrode disposed on the main surface of the memory chip as the capillary is lowered. Subsequently, the capillary is raised once and the wire is cut by closing the clamp, and then the top of the ball is pushed flat with the flat top capillary to be flat. Since the top of the ball is flattened, the heights of the dummy bumps 16 can be made uniform.

  The normal bump shown in FIG. 6B can be formed as follows, for example. First, similarly to the flat bump, a wire end ball formed at the tip of the capillary is pressed and connected to a pad electrode arranged on the main surface of the memory chip as the capillary is lowered. Subsequently, the capillary is once raised and the wire is cut by closing the clamp, and then the same capillary is lowered to press the top of the ball. Therefore, since the ball can be formed and the top of the ball can be flattened with one capillary, TAT (Turn Around Time) can be shortened as compared with the flat bump.

  The reverse bump shown in FIG. 6C can be formed as follows, for example. First, similarly to the flat bump, a wire end ball formed at the tip of the capillary is pressed and connected to a pad electrode arranged on the main surface of the memory chip as the capillary is lowered. Subsequently, after the capillary is raised and reversed, the wire is cut by closing the clamp, and then the capillary is lowered to press the top of the ball. Therefore, since the height of the dummy bump 16 can be made higher than that of the flat bump or the normal bump, the dummy bump 16 having a desired height can be easily formed.

  Although illustration is omitted, ball-shaped bumps can be formed as follows, for example. First, after increasing the spark time, a ball larger than the normal bump is formed at the tip of the capillary, for example, and then pressed against the pad electrode disposed on the main surface of the memory chip as the capillary is lowered. Subsequently, the capillary is once raised and the wire is cut by closing the clamp, and then the same capillary is lowered to press the top of the ball. Therefore, by forming ball-shaped bumps, dummy bumps 16 larger than the normal bumps can be formed, so that the force that supports the deflection of the memory chip can be increased. However, it is preferable to make the diameter of the ball-shaped bump smaller than the planar dimension of the pad electrode.

  The shape of the dummy bumps 16 is not limited to these, but the height and size for supporting the deflection of the memory chip are required for the dummy bumps 16. For this reason, the spark time for forming the wire end ball when forming the dummy bump 16, the heating temperature for fusing the wire, the pressing load for pressing the capillary against the pad electrode, and plastic deformation of the wire are assisted. Wire bonding parameters such as ultrasonic oscillation for promoting fusion with the joint surface and time for applying the load and ultrasonic waves are optimized.

  Next, the manufacturing process of the semiconductor device 1A according to the first embodiment will be described with reference to FIGS. 7 to 14 are fragmentary cross-sectional views of the semiconductor device 1A during the manufacturing process.

  First, as shown in FIG. 7, the wiring board 2, the first-stage memory chip 3a, and the first-stage spacer 6a are prepared. The lead electrodes 9 on the main surface 2x of the wiring board 2 are through holes (not shown) of the wiring board 2 (and plugs made of a metal material or the like embedded in the through holes, or conductor layers formed on the side walls of the through holes). And the back surface pad electrode 14 on the back surface 2 y of the wiring board 2 through a wiring layer inside the wiring board 2 and the like.

  The memory chip 3a includes a plurality of semiconductor elements on a main surface of a semiconductor wafer made of, for example, single crystal silicon, and a multilayer wiring layer in which a plurality of insulating layers and wiring layers are stacked on the main surface of the semiconductor wafer. After the surface protective film formed so as to cover the multilayer wiring layer is formed, the back surface of the semiconductor wafer is ground if necessary, and then the semiconductor wafer is separated into each semiconductor chip by dicing or the like. For example, a FLASH memory or the like can be used as the memory chip 3a. A plurality of pad electrodes 10 and a plurality of unconnected pad electrodes 10N electrically connected to a plurality of semiconductor elements formed in the memory chip 3a are exposed on the main surface of the memory chip 3a from the surface protective film. Is formed.

  The spacer 6a may be made of, for example, single crystal silicon, and a semiconductor wafer on which a semiconductor element is not formed is ground as necessary, and then the semiconductor wafer is separated into semiconductor chips having a predetermined shape by dicing or the like. .

  Next, in the chip bonding step, the back surface of the memory chip 3 a is bonded (fixed) to a predetermined position of the wiring board 2 via the DAF 7. The memory chip 3a is mounted such that the main surface of the memory chip 3a faces upward and the back surface faces downward. Subsequently, a spacer 6a is bonded to a predetermined position of the memory chip 3a through the DAF 8. The DAF 8 is a thermosetting insulating resin (for example, an epoxy resin and may contain a filler). The DAF 8 can be cured by heating to fix the memory chip 3a on the wiring board 2, and the spacer 6a is attached to the memory chip. It can be fixed on 3a.

  Next, as shown in FIG. 8, in the wire bonding step, a predetermined pad electrode 10 of the memory chip 3a and a predetermined lead electrode 9 of the wiring board 2 are bonded to a bonding wire 11 made of a fine metal wire such as a gold wire, for example. At the same time, a dummy bump 16 made of the same material as the bonding wire 11, that is, a fine metal wire such as a gold wire, is formed on the unconnected pad electrode 10N of the memory chip 3a. Examples of the dummy bump 16 include the flat bump, the normal bump, the reverse bump, and the ball-shaped bump described above. As a result, the bonding wire 11 is connected to the pad electrode 10 of the memory chip 3a, and the dummy bump 16 is connected to the unconnected pad electrode 10N. The bonding wires 11 and the dummy bumps 16 are not formed by different processes by combining the bonding wire 11 group and the dummy bump 16 group, but in a series of wire bonding in one memory chip, for example, the bonding wire 11 and the dummy bump 16 16, the bonding wire 11 and the bonding wire 11 are formed continuously.

  Next, as shown in FIG. 9, a second-stage memory chip 3b and a second-stage spacer 6b are prepared. Since the memory chip 3b and the spacer 6b are the same as the first-stage memory chip 3a and the first-stage spacer 6a, respectively, description thereof is omitted here.

  Next, in the chip bonding step, the back surface of the memory chip 3b is bonded to a predetermined position of the spacer 6a via the DAF 7. The memory chip 3b is mounted such that the main surface of the memory chip 3b faces upward and the back surface faces downward. Subsequently, a spacer 6b is bonded to a predetermined position of the memory chip 3b via the DAF 8.

  Next, in the wire bonding step, the predetermined pad electrode 10 of the memory chip 3b and the predetermined lead electrode 9 of the wiring board 2 are electrically connected via a bonding wire 11 made of a fine metal wire such as a gold wire. At the same time, a dummy bump 16 made of the same material as the bonding wire 11, that is, a fine metal wire such as a gold wire, is formed on the unconnected pad electrode 10N of the memory chip 3b. Examples of the dummy bump 16 include the flat bump, the normal bump, the reverse bump, and the ball-shaped bump described above. As a result, the bonding wires 11 are connected to the pad electrodes 10 of the memory chip 3b, and the dummy bumps 16 are connected to the unconnected pad electrodes 10N.

  Next, as shown in FIG. 10, a third-stage memory chip 3c and a third-stage spacer 6c are prepared. Since the memory chip 3c and the spacer 6c are the same as the first-stage memory chip 3a and the first-stage spacer 6a, respectively, description thereof is omitted here.

  Next, in the chip bonding step, the back surface of the memory chip 3c is bonded to a predetermined position of the spacer 6b via the DAF 7. The memory chip 3c is mounted such that the main surface of the memory chip 3c faces upward and the back surface faces downward. Subsequently, a spacer 6c is bonded to a predetermined position of the memory chip 3c through the DAF 8.

  Next, in the wire bonding step, the predetermined pad electrode 10 of the memory chip 3c and the predetermined lead electrode 9 of the wiring board 2 are electrically connected via a bonding wire 11 made of a thin metal wire such as a gold wire. At the same time, a dummy bump 16 made of the same material as the bonding wire 11, that is, a fine metal wire such as a gold wire, is formed on the unconnected pad electrode 10N of the memory chip 3c. Examples of the dummy bump 16 include the flat bump, the normal bump, the reverse bump, and the ball-shaped bump described above. As a result, the bonding wire 11 is connected to the pad electrode 10 of the memory chip 3c, and the dummy bump 16 is connected to the unconnected pad electrode 10N.

  Thereafter, as shown in FIG. 11, the fourth to eighth memory chips 3d, 3e, 3f, 3g, and 3h are performed in the same manner as the first to third memory chips 3a, 3b, and 3c. The fourth to seventh memory chips 6d, 6e, 6f and 6g are stacked in the same manner as the first to third spacers 6a, 6b and 6c described above.

  Next, as shown in FIG. 12, the controller chip 4 is prepared. The controller chip 4 includes a plurality of semiconductor elements on a main surface of a semiconductor wafer made of, for example, single crystal silicon, and a multilayer wiring layer in which a plurality of insulating layers and wiring layers are stacked on the main surface of the semiconductor wafer. After the surface protective film formed so as to cover the multilayer wiring layer is formed, the back surface of the semiconductor wafer is ground if necessary, and then the semiconductor wafer is separated into each semiconductor chip by dicing or the like. A plurality of pad electrodes electrically connected to a plurality of semiconductor elements formed in the controller chip 4 are formed on the main surface of the controller chip 4 so as to be exposed from the surface protective film.

  Next, in the chip bonding step, the back surface of the controller chip 4 is bonded to a predetermined position of the eighth-stage memory chip 3h via the DAF 7. The controller chip 4 is mounted such that the main surface of the controller chip 4 faces upward and the back surface faces downward. Subsequently, in a wire bonding step, a predetermined pad electrode of the controller chip 4 and a predetermined lead electrode 9 of the wiring substrate 2 are electrically connected via a bonding wire 11 made of a fine metal wire such as a gold wire.

  Next, as shown in FIG. 13, in the molding process, the first to eighth stage memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h, the controller chip 4, A resin sealing body 15 made of, for example, an epoxy-based thermosetting insulating resin is provided so as to cover the first to seventh stage spacers 6a, 6b, 6c, 6d, 6e, 6f and 6g and the bonding wire 11. Form.

  Molding of the first to eighth memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h and the wiring board 2 on which the controller chip 4 is wire-bonded for forming a resin sealing body The mold is sandwiched between the first mold and the second mold, a resin material is injected into the cavity through the gate, and the resin is cured by heating, and then the first mold and the second mold are released. Then, the wiring board 2 on which the resin sealing body 15 is formed is released from the first mold by the ejector pins. In this way, the resin sealing body 15 is formed.

  The second mold, which is a lower mold, is provided with a plurality of vacuum suction holes. During the molding process, the back side of the wiring board 2 is sucked and sucked through the vacuum suction holes, thereby firmly holding the wiring board 2 and suppressing warping or distortion of the wiring board 2 due to the heat of the second mold. can do.

  The first mold, which is the upper mold, is provided with a cavity and a gate. The cavity is a resin injection region for forming a resin sealing body, and the resin material injected therein is cured to form the resin sealing body 15. The cavities are the first to eighth memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h mounted on the wiring board 2, the controller chip 4, and the first to seventh spacers. 6a, 6b, 6c, 6d, 6e, 6f and 6g, and a shape capable of accommodating the bonding wire 11. The gate is an injection port through which molten resin for forming the resin sealing body 15 is injected into the cavity. Further, the first mold is provided with an ejector pin that can protrude into the cavity, and the wiring board 2 on which the resin sealing body 15 is formed after the molding process can be released from the first mold by the ejector pin. It is configured as follows.

  Next, as shown in FIG. 14, solder bumps 5 are formed on the back surface 2 y of the wiring board 2. For example, a solder ball is mounted on the back surface pad electrode 14 provided on the back surface 2y of the wiring substrate 2 with the back surface 2y of the wiring substrate 2 facing upward, and a reflow process is performed at a temperature of about 240 ° C., for example. Solder bumps 5 to be bonded to the back surface pad electrodes 14 on the back surface 2y of the wiring board 2 are formed.

  Thereafter, if necessary, the wiring board 2 is cut at a predetermined position and separated into individual pieces, whereby the semiconductor device 1A is obtained. The manufactured semiconductor device 1 </ b> A can be mounted on a mother board or the like by the solder bumps 5.

  As another form, in the molding process, a plurality of first to eighth stage memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h mounted on the wiring substrate 2, and a controller chip 4 The first to seventh stage spacers 6a, 6b, 6c, 6d, 6e, 6f and 6g and the entire bonding wire 11 are sealed with a resin sealing body 15 made of a thermosetting insulating resin, and the like. Alternatively, the resin sealing body 15 and the wiring substrate 2 can be diced and cut or separated into individual pieces to manufacture the semiconductor device 1A.

  Thus, according to the first embodiment, the bonding wires 11 are connected to the pad electrodes 10 of the memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h, and the unconnected pad electrodes 10N are connected to the unconnected pad electrodes 10N. Since the dummy bumps 16 are connected, it is possible to avoid the problem that the upper chip bends when the bonding wire 11 is connected to the pad electrode 10 of the upper chip, and cracks occur in the electrode pad 10 of the upper chip. Since the generation of cracks in the pad electrodes 10 of the memory chips 3b, 3c, 3d, 3e, 3f, 3g and 3h can be prevented, the pad electrodes 10 of the memory chips 3b, 3c, 3d, 3e, 3f, 3g and 3h Connection failure with the bonding wire 11 can be prevented, and the memory chips 3b and 3c due to the spread of cracks in the subsequent processes (for example, the process of forming the resin sealing body 15 and the process of connecting the solder bumps 5). , 3d, 3e, 3f, 3g, and 3h can be prevented from cutting the wiring layer adjacent to the pad electrode 10.

(Embodiment 2)
The semiconductor device according to the second embodiment is the same as the first embodiment described above, and is a semiconductor device in which a plurality of semiconductor chips are stacked in multiple stages, but the upper chip provided on the unconnected pad electrode of the lower chip is used. The supporting dummy pattern is different from that of the first embodiment.

  That is, in the first embodiment described above, the dummy bumps 16 are arranged on the unconnected pad electrodes 10N of the lower chip as dummy patterns that support the upper chip. The upper chip is not bent when the bonding wire 11 is connected to the pad electrode 10 of the upper chip located above the unconnected pad electrode 10N of the lower chip, with the dummy bumps 16 as a support. Cracks are unlikely to occur in the electrode 10. On the other hand, in the second embodiment, instead of the dummy bumps 16, a support made of an inexpensive resin or paste material is formed on the unconnected pad electrode 10N of the lower chip.

  Such a semiconductor device in which a plurality of memory chips according to the second embodiment are stacked in multiple stages will be described with reference to a cross-sectional view of the main part of the semiconductor device shown in FIG.

  As shown in FIG. 15, the semiconductor device 1B is configured, and a resin 17 is arranged as a support on the unconnected pad electrodes 10N of the first to seventh memory chips 3a, 3b, 3c, 3d, 3e, 3f and 3g. Has been. The resin 17 is, for example, a resin formed by a potting method, for example, a liquid epoxy resin, and can be formed by applying a resin on the unconnected pad electrode 10N by a potting method and then curing it by heat treatment. it can. Instead of the resin 17, a paste material (for example, a paste-like ink obtained by adding an additive such as an organic resin component to a fine metal powder) may be used. For example, after applying the paste material on the unconnected pad electrode 10N, It can be formed by performing heat treatment to decompose and remove the resin component.

  As described above, according to the second embodiment, the inexpensive resin 17 or paste material can be disposed on the unconnected pad electrode 10N of the lower chip as a dummy pattern that supports the upper chip. As a result, it is possible to prevent the deflection of the upper chip, and to suppress the increased material cost due to placing the support on the unconnected pad electrode 10N of the lower chip at low cost.

(Embodiment 3)
The semiconductor device according to the second embodiment is the same as the first embodiment described above, and is a semiconductor device in which a plurality of semiconductor chips are stacked in multiple stages, but the upper chip provided on the unconnected pad electrode of the lower chip is used. The supporting dummy pattern is different from that of the first embodiment.

  That is, in the first embodiment described above, the dummy bumps 16 are arranged on the unconnected pad electrodes 10N of the lower chip as dummy patterns that support the upper chip. The upper bump is supported by the dummy bump 16 so that the upper chip does not bend when the bonding wire 11 is connected to the pad electrode 10 of the upper chip positioned on the unconnected pad electrode 10N of the lower chip. The pad electrode 10 is less likely to crack. On the other hand, the planar shape of the spacer placed between the upper chip and the lower chip, which has been a quadrangle in the first embodiment described above, is a planar shape having a convex portion in a quadrangle in the present third embodiment. The unconnected pad electrode 10N of the chip is covered with the convex portion which is a part of the spacer to support the upper chip.

  Such a semiconductor device in which a plurality of memory chips according to the third embodiment are stacked in multiple stages will be described with reference to a plan view of the main part of the semiconductor device shown in FIG. In FIG. 16, the first stage memory chip 3a, the second stage memory chip 3b, and the first stage provided between the first stage memory chip 3a and the second stage memory chip 3b of the semiconductor device 1C. Although the third embodiment has been described using the eye spacers 18, the present invention is not limited to this, and can be similarly applied to other stages of memory chips and spacers.

  As shown in FIG. 16, the basic planar shape is rectangular, the pad electrode 10 to which the bonding wire 11 of the memory chip 3a is connected is exposed, and the unconnected pad electrode 10N to which the bonding wire 11 of the memory chip 3a is not connected is formed. A spacer 18 having a convex portion is provided between the memory chip 3a and the memory chip 3b so as to cover it. When the bonding wire 11 is connected to the pad electrode 10 of the memory chip 3b positioned on the unconnected pad electrode 10N of the memory chip 3a, the convex portion of the spacer 18 is supported, and the memory chip 3b is not bent. Therefore, cracks are unlikely to occur in the pad electrode 10 of the memory chip 3b.

  As described above, according to the third embodiment, the number of steps for processing the spacer increases, but it is possible to reliably prevent the upper chip from being bent.

(Embodiment 4)
The semiconductor device according to the fourth embodiment is the same as that of the first embodiment described above, and is a semiconductor device in which a plurality of semiconductor chips are stacked in multiple stages, but the upper chip provided on the unconnected pad electrode of the lower chip. The dummy pattern that supports the difference is different from the first embodiment described above.

  That is, in the first embodiment described above, the dummy bumps 16 are arranged on the unconnected pad electrodes 10N of the lower chip as dummy patterns that support the upper chip. The upper chip is bent when the bonding wire 11 is connected to the pad electrode 10 disposed on the main surface of the upper chip located above the unconnected pad electrode 10N of the lower chip, with the dummy bump 16 as a support. Therefore, the pad electrode 10 disposed on the main surface of the upper chip is less likely to crack. On the other hand, in the fourth embodiment, the upper chip deflection is reduced by using a spacer having a larger planar dimension than that of the spacer used in the first embodiment.

  As described in the first embodiment, the spacer is generally made of, for example, single crystal silicon, and after grinding a semiconductor wafer on which a semiconductor element is not formed, if necessary, the semiconductor wafer is predetermined by dicing or the like. The separated semiconductor chip is used. For this reason, in order to increase the number of spacers acquired from the semiconductor wafer, the spacers are formed relatively small. In the first embodiment described above, for example, as shown in FIG. 2, the distance from the end of the spacer 6a to the end of the memory chip 3b, that is, the dimension (L1) at which the memory chip 3b overhangs is 3 μm or more. The dimension (L2) from the end of the spacer 6a to the pad electrode 10 of the memory chip 3b is 2 μm or more.

  In the fourth embodiment, the dimension from the end of the spacer to the unconnected pad electrode of the lower chip is, for example, less than 2 μm, and for example, the wiring that electrically connects the circuit element unit formed on the lower chip and the pad electrode Place the end of the spacer on top. Thereby, since the overhang of the upper chip is reduced, the deflection of the upper chip can be reduced.

  Such a semiconductor device in which a plurality of semiconductor chips according to the fourth embodiment are stacked in multiple stages will be described with reference to a plan view and a cross-sectional view of a relevant part of the semiconductor device shown in FIGS. 17 (a) and 17 (b). . In FIG. 17, the first stage memory chip 3a, the second stage memory chip 3b, and the first stage provided between the first stage memory chip 3a and the second stage memory chip 3b of the semiconductor device 1D. Although the fourth embodiment has been described using the eye spacers 19, the present invention is not limited to this, and can be similarly applied to other stages of memory chips and spacers.

  As shown in FIG. 17, by increasing the planar dimension of the spacer 19, the distance from the end of the spacer 19 to the unconnected pad electrode 10N of the memory chip 3a is set to, for example, less than 2 μm. Thus, the end of the spacer 19 is located between the memory mat of the memory chip 3a and the unconnected pad electrode 10N. For example, the memory mat (semiconductor element formation region) 20 of the memory chip 3a is completely covered by the spacer 19. Is called.

  As described above, according to the fourth embodiment, the deflection of the upper chip can be reduced by shortening the distance from the end of the spacer 19 to the unconnected pad electrode 10N of the lower chip, for example, less than 2 μm. it can.

(Embodiment 5)
In the first to fourth embodiments described above, the semiconductor devices 1A, 1B, 1C, and 1D on which the plurality of memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g, and 3h are stacked have been described. In the fifth embodiment, a semiconductor device will be described in which upper and lower chips having different functions and different chip sizes are stacked with a spacer interposed therebetween.

  That is, in the first embodiment described above, a plurality of memory chips 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h having the same chip size and the same pad electrode positions are stacked in multiple stages. The dummy bumps 16 are disposed on the unconnected pad electrodes 10N of the memory chips 3a, 3b, 3c, 3d, 3e and 3f. Therefore, the unconnected pad electrode 10N of the lower chip is disposed directly below the pad electrode 10 of the upper chip, and a dummy bump serving as a support is directly below the position where the strongest force from the capillary is applied when the bonding wire 11 is connected. 16 is formed. The upper bump is supported by the dummy bump 16 so that the upper chip does not bend when the bonding wire 11 is connected to the pad electrode 10 of the upper chip located directly above the unconnected pad electrode 10N of the lower chip. The pad electrode 10 is less likely to crack.

  On the other hand, in the fifth embodiment, the unconnected pad electrode 10N of the lower chip is not disposed directly below the pad electrode 10 of the upper chip, and the lower stage is located at a position shifted from just below the pad electrode 10 of the upper chip. An unconnected pad electrode 10N of the chip is arranged. Even in such a case, the upper chip is not bent when the bonding wire 11 is connected to the pad electrode 10 of the upper chip by providing means for supporting the upper chip to the unconnected pad electrode 10N of the lower chip. Therefore, cracks are unlikely to occur in the pad electrode 10 of the upper chip.

  A semiconductor device in which two semiconductor chips according to the fifth embodiment are stacked will be described with reference to FIG. 18A is a plan view of a main part of a wiring board in which a lower chip is mounted and a spacer is stacked on the lower chip and the upper chip, and FIG. 18B is a plan view of the lower chip and spacer shown in FIG. The principal part top view at the time of mounting an upper stage chip | tip further on the mounted board | substrate further, (c) has shown the principal part sectional drawing in the EE 'line of (b). The lower chip is, for example, a microcomputer chip, and the upper chip is, for example, a memory chip.

  As shown in FIG. 18A, a lower chip (microcomputer chip) 23 is mounted on the main surface of the wiring board 22 via a DAF. On the main surface of the wiring board 22, one or two rows of lead electrodes 24 are arranged along each side of the wiring board 22 in a region between the end of the lower chip 23 and the end of the wiring board 22. Has been. These lead electrodes 24 are constituted by a part of each of a plurality of uppermost layer wirings formed on the core material of the wiring board 22, and are formed on the protective film on the main surface of the core material corresponding to each lead electrode 24. It is exposed through the opening. In addition, a plurality of pad electrodes 25 in a row are arranged along the side edge on the main surface of the lower chip 22. These pad electrodes 25 are composed of the uppermost wiring of the multilayer wiring layers of the lower chip 22, and are exposed through openings formed in the surface protective film of the lower chip 22 corresponding to the pad electrodes 25. . A spacer 26 is mounted on the main surface of the lower chip 22 inside the region where the pad electrodes 25 are disposed via a DAF.

  A plurality of pad electrodes 25 arranged on the main surface of the lower chip 23 and a plurality of lead electrodes 24 arranged on the main surface of the wiring substrate 22 are electrically connected by a plurality of bonding wires 27, respectively. The bonding wire 27 is, for example, a gold wire of 15 to 20 μmφ, and is formed by, for example, a nail head bonding method in which ultrasonic vibration is used in combination with thermocompression bonding. The plurality of pad electrodes 25 arranged on the main surface of the lower chip 23 include an unconnected pad electrode 25N that is not electrically connected to the lead electrode 24 of the wiring board 22, and this unconnected pad A dummy bump 28 is connected to the electrode 25N.

  18B and 18C show a state where an upper chip (memory chip) 29 is mounted on the spacer 26 via a DAF. The planar shape intersecting the thickness direction of the upper chip 29 is a quadrangle, but the length of two sides along one direction (the X direction shown in FIG. 18) of the upper chip 29 is the other direction intersecting the one direction ( 18 has a shape shorter than the length of two sides along the Y direction), and the length of the two sides along one direction (X direction) of the upper chip 29 is shorter than one side of the spacer 26. The length of two sides along the other direction (Y direction) of 29 is longer than one side of the lower chip 23.

  On the main surface of the upper chip 29, one row of a plurality of pad electrodes 30 is arranged along a side edge portion in one direction (X direction). These pad electrodes 30 are composed of the uppermost wiring of the multilayer wiring layers of the upper chip 29 and are exposed through openings formed in the surface protective film of the upper chip 29 corresponding to the respective pad electrodes 30. . A plurality of pad electrodes 30 arranged on the main surface of the upper chip 29 and a plurality of lead electrodes 24 arranged on the main surface of the wiring substrate 22 are electrically connected by a plurality of bonding wires 31, respectively. The bonding wire 31 is, for example, a gold wire of 15 to 20 μmφ, and is formed by, for example, a nail head bonding method in which ultrasonic vibration is used in combination with thermocompression bonding. In the direction along the other direction (Y direction) of the upper chip 29, the distance from the end of the upper chip 29 to the end of the spacer 26 (overhang of the upper chip 29) is from the end of the spacer 26 to the lower chip 23. It is larger than the distance to the edge. For this reason, it is considered that the deflection of the upper chip 29 when the bonding wire 31 is connected to the pad electrode 30 of the upper chip 29 is relatively large. However, although not necessarily located directly below the pad electrode 30 of the upper chip 29, a bonding wire 27 is formed on the pad electrode 25 of the lower chip 23, and a dummy bump 28 is formed on the unconnected pad electrode 25N. Therefore, the bonding wires 27 and the dummy bumps 28 serve as a support, and the deflection of the upper chip 29 can be prevented.

  In the sixth embodiment, a semiconductor device in which the lower chip 23 is a microcomputer chip and the upper chip 29 is a memory chip is illustrated. However, the present invention is not limited to this, and the planar shape or the planar dimensions are different from each other. The present invention can be applied to the lower chip 23 and the upper chip 29.

  In the sixth embodiment, the dummy bumps 28 are exemplified as means for supporting the upper chip 29. However, the present invention is not limited to this. For example, the resin 17 or the paste material described in the second embodiment is used. Can do.

  As described above, according to the sixth embodiment, even when a plurality of semiconductor chips having different functions (for example, the lower chip 23 and the upper chip 29) are stacked via the spacers 26, Since the upper chip 29 can be supported by the bonding wire 27 connected to the pad electrode 25 and the dummy bump 28 connected to the unconnected pad electrode 25N, the upper chip 29 can be prevented from being bent.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the present invention, a plurality of semiconductor chips are stacked in multiple stages on a wiring board, and a plurality of pad electrodes arranged on the main surface of each semiconductor chip and a plurality of lead electrodes arranged on the main surface of the wiring board are bonded. The present invention can be applied to a semiconductor device connected with a wire.

1 is a main part sectional view for explaining the configuration of a semiconductor device according to a first embodiment; It is principal part sectional drawing to which the A area | region of FIG. 1 was expanded. (A) is a principal part top view in the BB 'line of FIG. 1, (b) is a principal part top view in the CC' line of FIG. (A) is an enlarged cross-sectional view of the main part of the upper and lower chip using the bonding wire according to the first embodiment as a support means, and (b) is the upper and lower chip using the dummy bump as a support means according to the first embodiment. It is the expanded principal part sectional drawing. (A), (b), (c) and (d) are principal planes showing a part of the semiconductor device when the memory chips according to the first embodiment are sequentially stacked from the first stage to the fourth stage, respectively. It is a figure and principal part sectional drawing. (A), (b) and (c) are bump structure diagrams for explaining various shapes of dummy bumps. 7 is a fragmentary cross-sectional view of the semiconductor device during the manufacturing process of the semiconductor device according to the first embodiment; FIG. FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step of the semiconductor device following that of FIG. 13; It is principal part sectional drawing of the semiconductor device by this Embodiment 2. FIG. It is a principal part top view of the semiconductor device by this Embodiment 3. FIG. (A) And (b) is the principal part top view and principal part sectional drawing of the semiconductor device by this Embodiment 4, respectively. (A) is a wiring board in which a lower chip is mounted and a spacer is stacked on the lower chip, and a plan view of the main part of the upper chip, and (b) is a mounting in which the lower chip and the spacer shown in (a) are mounted. The principal part top view at the time of mounting an upper stage chip | tip further on a board | substrate, (c) is principal part sectional drawing in the EE 'line of (b). It is a schematic diagram explaining the deflection | deviation of the semiconductor chip in the wire bonding process of the semiconductor device which laminated | stacked the several semiconductor chip investigated by the present inventors in multistage.

Explanation of symbols

1A, 1B, 1C, 1D Semiconductor device 2 Wiring board 2x Main surface 2y Back surface 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h Memory chip 3D Lower chip 3U Upper chip 4 Controller chip 5 Solder bump 6, 6a, 6b, 6c, 6d, 6e, 6f, 6g Spacer 7, 8 DAF
9 Lead Electrode 10 Pad Electrode 10N Unconnected Pad Electrode 11 Bonding Wire 13 Pad Electrode 14 Back Pad Electrode 15 Resin Encapsulant 16 Dummy Bump 17 Resin 18, 19 Spacer 20 Memory Mat 22 Wiring Substrate 23 Lower Chip 24 Lead Electrode 25 Pad Electrode 25N Unconnected pad electrode 26 Spacer 27 Bonding wire 28 Dummy bump 29 Upper chip 30 Pad electrode 31 Bonding wire 51 Mounting wiring 52 Lower chip 53 Spacer 54 Upper chip 55 Bonding wire

Claims (7)

A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing a wiring board having an upper surface, a plurality of lead electrodes formed on the upper surface, and a lower surface opposite to the upper surface;
(B) a first semiconductor chip having a first main surface, a plurality of first pad electrodes formed on the first main surface, and a first back surface opposite to the first main surface; A step of mounting on the upper surface of the wiring board such that is opposite the upper surface of the wiring board;
(C) mounting a spacer on the first main surface of the first semiconductor chip so that the plurality of first pad electrodes are exposed;
(D) electrically connecting the plurality of first pad electrodes of the first semiconductor chip and the plurality of lead electrodes of the wiring board via a plurality of first wires;
(E) a second semiconductor chip having a second main surface, a plurality of second pad electrodes formed on the second main surface, and a second back surface opposite to the second main surface; Mounting on the spacer so as to face the spacer;
(F) electrically connecting the plurality of second pad electrodes of the second semiconductor chip and the plurality of lead electrodes of the wiring board via a plurality of second wires;
here,
The plurality of first pad electrodes have unconnected pad electrodes that are not electrically connected to the lead electrodes of the wiring board,
Prior to the step (e), a dummy pattern is disposed on the unconnected pad electrode,
In the step (e), the second semiconductor chip is mounted on the spacer so that one of the plurality of second pad electrodes is positioned on the dummy pattern. In the manufacturing method of the semiconductor device according to claim 1,
In the step (f), the second wire and the second pad electrode are connected by pressing a part of the second wire against the second pad electrode with a capillary. Method. The method of manufacturing a semiconductor device according to claim 2.
After the step (f), the first semiconductor chip, the second semiconductor chip, the spacer, the plurality of first wires, and the plurality of second wires are sealed with resin. Production method. In the manufacturing method of the semiconductor device according to claim 3,
The dummy pattern consists of the first wire,
In the step (d), the dummy pattern is joined to the unconnected pad electrode. In the manufacturing method of the semiconductor device according to claim 3,
The dummy pattern is made of resin or paste material,
Prior to the step (e), the resin or the paste material is applied onto the unconnected pad electrode, and a heat treatment is performed. In the manufacturing method of the semiconductor device according to claim 3,
The dummy pattern consists of a part of the spacer,
Prior to the step (e), the spacer is mounted on the first main surface of the first semiconductor chip such that the part of the spacer is positioned on the unconnected pad electrode. A method for manufacturing a semiconductor device. A wiring board having an upper surface, a plurality of lead electrodes formed on the upper surface, and a lower surface opposite to the upper surface;
A first main surface; a plurality of first pad electrodes formed on the first main surface; and a first back surface opposite to the first main surface , wherein the first back surface is the top surface of the wiring board. A first semiconductor chip mounted on the upper surface of the wiring board so as to be opposed to
A spacer mounted on the first main surface of the first semiconductor chip such that the plurality of first pad electrodes are exposed ;
A second main surface, a plurality of second pad electrodes formed on the second main surface, and a second back surface opposite to the second main surface , wherein the second back surface faces the spacer. A second semiconductor chip mounted on the spacer;
Wherein the plurality of the lead electrodes of the plurality of first pad electrode and the wiring substrate of the first semiconductor chip, a plurality of first wires electrically connected,
Wherein the plurality of the lead electrodes of the plurality of second pad electrode and the wiring substrate of the second semiconductor chip, a plurality of second wires electrically connected,
It includes,
The plurality of first pad electrodes have unconnected pad electrodes that are not electrically connected to the lead electrodes of the wiring board ,
A dummy pattern is disposed on the unconnected pad electrode ,
In the second semiconductor chip, one of the plurality of second pad electrodes is the dummy pattern.
The semiconductor device is mounted on the spacer so as to be located on the surface.

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