JP5174433B2 - AD converter and scale - Google Patents

Description

  The present invention relates to an AD converter that converts analog data sampled at a predetermined time interval or for a predetermined time into a digital value and outputs the digital data, and a balance including the AD converter.

  Conventionally, as this type of AD converter, a double integral type AD converter disclosed in Patent Document 1 below is disclosed. This AD converter integrates and samples the measured voltage for a certain period of time with an integration circuit, performs inverse integration with the constant voltage, and converts the analog voltage to a digital value based on the inverse integration time until the output of the integration circuit reaches the standard voltage. Convert to By repeating such a conversion operation, a continuous analog voltage is converted into discrete digital data.

JP-A-62-231524

  In this type of AD converter, since the integration time in each conversion operation and the input voltage at the time of inverse integration are constant, if there is no significant change in the measured voltage, the sampling time interval in each conversion operation is also It tends to be kept constant. For this reason, when the period of noise mixed in the measurement voltage at a fixed period and the sampling time interval are synchronized, conversion to a digital value based on the measurement voltage mixed in noise is continuously performed, and the conversion accuracy to digital data There was a risk of a significant drop. Such a problem may occur similarly in other AD converters such as a successive approximation type in which the measurement voltage is sampled at a constant time interval.

  In particular, in an AD converter that suppresses conversion errors due to noise mixing by averaging each digital value obtained by sampling over a plurality of times and converting it to digital data, the noise mixing period and sampling frequency are reduced. When the time interval is synchronized, there is a possibility that the conversion accuracy is greatly lowered without suppressing the conversion error.

  An object of this invention is to provide the AD converter and scale which can solve the said subject.

In order to solve such a problem, the AD converter according to the present invention is an AD converter that integrates an input signal, and performs sampling of analog data at least at a conversion operation time different from the previous sampling. And
In addition, every time analog data is sampled and converted into a digital value, the present invention adds the accumulated digital value based on the sampling of the cumulative number of one or more times before that to the addition result. It is characterized in that digital data to be output is specified based on this.
Further, the present invention provides a value obtained by adding the conversion operation time for sampling analog data to the cumulative value of the conversion operation time during the sampling of the cumulative number over a plurality of times, at each sampling time point. The analog data is sampled so as to be equal to each other.
The balance of the present invention is characterized in that analog data supplied from a measuring instrument that measures an applied load is converted into a digital value by any of the above-mentioned AD converters to obtain digital data.

  ADVANTAGE OF THE INVENTION According to this invention, the AD converter which can raise the conversion precision to digital data can be provided.

The best mode of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an outline of the configuration of the weight scale 1 of the present embodiment. FIG. 2 is a block diagram showing an outline of the configuration of the AD converter 3 provided in the weight scale 1.

  As shown in FIG. 1, the scale 1 includes a differential amplifier circuit 2 that amplifies an output voltage from a bridge configured with a strain gauge as a resistor, and an analog voltage amplified by the differential amplifier circuit 2 into a digital value. An AD converter 3 that outputs digital data obtained by the conversion and a display device 4 that displays the digital data output from the AD converter 3 are provided. The strain gauge is a measuring instrument that measures a load applied to the scale 1, and changes the resistance value according to the strain amount of the load cell that receives the load. The output voltage from the bridge changes according to the change in the resistance value of each strain gauge, and the input voltage from the differential amplifier circuit 2 to the AD converter 3 also changes accordingly.

  As shown in FIG. 2, the AD converter 3 integrates the measurement voltage Vi input from the differential amplifier circuit 2 and determines whether the output voltage Vs from the integration circuit 31 has reached the standard voltage Vo. A comparator 32 for determining and a control device 33 for controlling the operation of each circuit included in the AD converter 3 are provided.

  The integrating circuit 31 is configured by connecting a resistor R to the inverting input terminal of the operational amplifier 31a, grounding the non-inverting input terminal, and connecting a capacitor C between the inverting input terminal and the output. The output of the integrating circuit 31 is connected to the inverting input terminal of the comparator 32. The resistor R is connected to the output of the differential amplifier circuit 2 and the reference voltage source 30 via the switch circuit s1 or the switch circuit s2, respectively. A reference voltage −Vr having a polarity opposite to that of the measurement voltage Vi is input from the reference voltage source 30. The comparator 32 has a non-inverting input terminal connected to the standard voltage source 36 and an output connected to the control device 33. A standard voltage Vo is input from the standard voltage source 36. The non-inverting input terminal of the comparator 32 may be grounded without being connected to the voltage source. In this case, the standard voltage Vo = 0V.

  The control device 33 is connected to a clock pulse generation circuit 34 that generates clock pulses, a counter 35 that counts the number of clock pulse generations, and switch circuits s1 and s2. The control device 33 controls the operation of the switch circuits s1, s2 and the counter 35 in synchronization with the clock pulse input from the clock pulse generation circuit 34, and turns on the switch circuit s1 until a predetermined integration time elapses. After the circuit s2 is turned off and the measurement voltage Vi is integrated, the switch circuit s1 is turned off and the switch circuit s2 is turned on until the output voltage Vs from the integration circuit 31 reaches the standard voltage Vo, and the reference voltage -Vr is deintegrated. Repeat the conversion operation.

  In each conversion operation, the control device 33 converts the measurement voltage Vi into a digital value based on the reverse integration time from the start to the end of the reverse integration. Here, the integration time and the inverse integration time for the control device 33 to perform the conversion operation are determined based on the count value of the clock pulse by the counter 35. In the memory circuit 33a of the control device 33, the count value of the counter 35 during the reverse integration time in the past m times (in the present embodiment, 4 times) of the conversion operation is cumulatively added as a digital value. Is remembered as The storage circuit 33a stores conversion information in which the digital cumulative value and the converted digital value output as digital data are associated with each other.

  Each time the control device 33 performs a conversion operation to acquire a digital value, the control device 33 adds the acquired digital value to the accumulated digital value stored in the storage circuit 33a, and m + 1 times obtained (4 + 1 = 5 times in this embodiment). The converted digital value is determined by referring to the conversion information stored in the storage circuit 33a on the basis of the digital total value of). In addition, the control device 33 outputs the determined converted digital value as digital data and causes the display device 4 to display it.

  The integration time in each conversion operation by the AD converter 3 is determined based on the integration time information stored in the storage circuit 33a. The integration time information is a table that stores the number of conversion operations from 1 to n in association with the count values a1 to an of the clock pulses that determine the integration time in each conversion operation. The count values a1 to an are used in the conversion operation in order from the count value a1 corresponding to one conversion operation. When the count value an is used, the count value a1 is used again. Each count value a1 to an is set to a value different from at least the count value a1 to an used in the previous conversion operation. For example, the count value a2 is different from the count values a1 and a3. Each count value a1 to an is set so that the sum of the count value obtained in the previous m conversion operations (four times in this embodiment) plus the current count value is equal. . That is, in the AD converter 3, the total count value for m + 1 times obtained by adding the count value in the conversion operation to the total count value obtained in the past m conversion operations is equal at each sampling time point. Sampling of analog data is performed to obtain a value.

  Next, an operation in which the AD converter 3 converts analog data into digital data and outputs it will be described. FIG. 3 is a timing chart for explaining the operation of the AD converter 3. This figure shows signal waveforms of the output voltage Vs from the operational amplifier 31a of the integrating circuit 31, the output voltage Vc from the comparator 32, the clock pulse, the reset pulse, and the count pulse.

  When the control device 33 closes the switch circuit s1 at the time T0, the voltage Vi is input from the differential amplifier circuit 2 through the resistor R to the inverting input terminal of the operational amplifier 31a included in the integrating circuit 31, and the capacitor C is associated therewith. The battery is charged with current. As a result, a voltage Vs having a reverse polarity proportional to the integral value of the input voltage to the inverting input terminal (a voltage having a reverse polarity proportional to the integral value of the input current to the capacitor C) is output from the operational amplifier 31a and inverted by the comparator 32. Input to the input terminal. The output voltage Vs of the operational amplifier 31a input to the inverting input terminal of the comparator 32 gradually decreases with the charging time. While the output voltage Vs of the operational amplifier 31a is higher than the standard voltage Vo input to the non-inverting input terminal of the comparator 32, the output voltage Vc of the comparator 32 is maintained at the Lo level.

  When the output voltage Vs of the operational amplifier 31a drops to the standard voltage Vo at time T1, the output voltage Vc of the comparator 32 changes from Lo level to Hi level. When the output voltage Vc of the comparator 32 changes to the Hi level, the control device 33 inputs a reset pulse to the counter 35. As a result, the counter 35 resets the count value to “0” and starts counting clock pulses. Thereafter, the counter 35 counts the number of clock pulses each time a clock pulse is input from the clock pulse generation circuit 34 to the control device 33, and outputs the count value to the control device 33. The count value is stored in the storage circuit 33a of the control device 33. While the output voltage Vs of the operational amplifier 31a continues to decrease and falls below the standard voltage Vo, the output voltage Vc of the comparator 32 maintains the Hi level.

  When the count value of the counter 35 stored in the storage circuit 33a reaches a predetermined value determined in the integration time information at time T2, the control device 33 opens the switch circuit s1 and closes the switch circuit s2. As a result, the reference voltage -Vr is input to the inverting input terminal of the operational amplifier 31a included in the integration circuit 31 via the resistor R, and accordingly, a current having a polarity opposite to that of the time T0 to the time T2 is input to the capacitor C. The output voltage Vs of the operational amplifier 31a increases. Further, the control device 33 inputs a reset pulse to the counter 35. Thus, the counter 35 resets the count value to “0”, starts a new count, and outputs the count value to the control device 33.

  When the output voltage Vs of the operational amplifier 31a input to the inverting input terminal of the comparator 32 gradually increases and exceeds the standard voltage Vo input to the non-inverting input terminal of the comparator 32 at time T3, the output voltage Vc of the comparator 32 is increased. It changes from Hi level to Lo level. When the output voltage Vc of the comparator 32 changes to the Lo level, the control device 33 inputs a reset pulse to the counter 35. Thereby, the count by the counter 35 is completed, and the count value is stored in the storage circuit 33a. Thereafter, at time T0, the control device 33 opens the switch circuit s2 and closes the switch open circuit s1, whereby the output voltage Vs of the operational amplifier 31a that has continued to rise is lowered, and the next conversion operation is performed.

  Thereafter, the control device 33 repeatedly performs the same conversion operation as from time T0 to time T3 with an integration time corresponding to the count value defined in the integration time information. In the five conversion operations shown in FIG. 3, the integration times Ts1, Ts2, Ts3, Ts4, and Ts5 are different times corresponding to the count values defined in the integration time information. In each conversion operation, the control circuit 33 changes the count value by the counter 35 in the past four conversion operations stored in the storage circuit 33a every time the output voltage Vc of the comparator 32 changes from the Hi level to the Lo level. Add to the accumulated count value. Then, a converted digital value is specified based on the conversion information stored in the storage circuit 33 a, the specified converted digital value is output as digital data, and display is performed on the display device 4.

  According to the present embodiment, the integration time for sampling analog data is not set to a fixed time, and analog data sampling is unlikely to be performed at a constant cycle. Can be continuously mixed over a plurality of samplings. For this reason, it becomes possible to improve the precision which converts analog data into digital data.

  In particular, in a scale such as the scale 1, there is no significant change in the measurement voltage Vi input to the integration circuit 31 when measuring the load. Therefore, if the integration time is constant, the inverse integration time in each conversion operation is also large. There is no change, and the time interval for sampling analog data tends to be kept constant. For this reason, if noise is mixed into the measurement voltage Vi at a constant period, there is a risk that the accuracy of conversion to digital data is greatly lowered in synchronization with the sampling time interval. However, according to the present embodiment, since the integration time in each conversion operation is not set to a fixed time, the analog data sampling time interval becomes constant even if the measurement voltage Vi does not change significantly. It is possible to avoid the synchronization of the noise mixing period and the sampling time, and it is possible to prevent the conversion accuracy to the digital value from being lowered.

  Further, according to the present embodiment, the digital data obtained by converting the analog data is added to the cumulative value of the digital values obtained based on the previous four samplings, and obtained based on the addition result. Since the converted digital value is output as digital data, even if noise is mixed in the sampled analog data or a part of the analog data sampled in the previous four conversion operations, the noise will improve the conversion accuracy of the digital data. It is possible to suppress the influence.

  In addition, in the AD converter 3 of the present embodiment in which the conversion error due to noise mixing is suppressed by obtaining digital data based on the cumulative value of each digital value obtained by sampling five times, the noise mixing period and sampling If the time interval is synchronized, there is a possibility that the conversion error cannot be suppressed.However, as described above, it is possible to prevent the noise generated at a constant period from being continuously mixed over a plurality of conversion operations. It is possible to suppress the deterioration of conversion accuracy.

  In addition, according to the present embodiment, the cumulative value of the integration time performed for obtaining digital data can be made equal for each digital data, so that the conversion accuracy to digital data can be improved.

  In the above embodiment, the case where the table is used as the integration time information for determining the integration time in each conversion operation has been described. However, the integration time may be determined by executing the calculation. The number of conversion operations for obtaining each converted digital value is arbitrary and is not limited to five. Further, the integration time in each conversion operation is arbitrary as long as it differs from at least the integration time in the previous sampling, depending on the number of conversion operations for obtaining each conversion digital value and the number of conversion operations specified in the table. It can be changed as appropriate. The number of conversion operations n determined in the integration time information is also arbitrary. The method of specifying the converted digital value based on the digital cumulative value is arbitrary. For example, the average value of each digital value may be calculated from the digital cumulative value, and the calculated value may be used as the converted digital value.

In the above embodiment, the case where the present invention is applied to the double integration AD converter 3 that samples an analog signal for a predetermined time has been described. However, the present invention can also be applied to the AD converter 5 of another system that samples an analog signal at a predetermined time interval or for a predetermined time.

  Hereinafter, the case where the present invention is applied to the successive approximation AD converter 5 will be described. FIG. 4 is a block diagram showing an outline of the configuration of the successive approximation AD converter 5. In the AD converter 5, the measurement voltage Vi is sampled by the sample hold circuit 51 at a predetermined time interval in accordance with the input of the sampling clock from the control device 53. Then, the sampled measurement voltage Vi is sequentially input to the analog comparator 52 and compared with the reference voltage Vr.

  In the control device 53, the data in the successive approximation register 53a is determined bit by bit in accordance with the comparison result in the analog comparator 52. The data in the successive approximation register 53a is converted into an analog voltage by the DA converter 54 and input to the analog comparator 52 as the reference voltage Vr, and the above-described processing is repeated based on the reference voltage Vr. In this manner, the data in the successive approximation register 53a is determined bit by bit to obtain a digital value, and the digital data is output from the control device 53 based on the obtained digital value.

  In the successive approximation AD converter 5 shown in FIG. 4, the measurement voltage Vi can be sampled at least at a time interval different from the previous sampling time by adjusting the input timing of the sampling clock to the sample hold circuit 51. . Even in the successive approximation AD converter 5, sampling of analog data is not continuously performed at a constant cycle, so that the same operational effects as those of the double integral AD converter 3 of the above embodiment can be obtained. Can do.

  Each time the successive approximation AD converter 5 samples analog data and converts it to a digital value, the successive approximation type AD converter 5 adds it to the cumulative value of each digital value converted based on one or more previous samplings. The conversion value of analog data sampled based on the addition result into digital data may be specified.

  In such a configuration, the analog value is obtained so that the value obtained by adding the sampling interval of the current sampling to the cumulative value of the sampling interval of the plurality of previous samplings is equal to each sampling time point. Data sampling may be performed.

  Even with these configurations, it is possible to obtain the same effect as the double integration AD converter 3 of the above embodiment by suppressing the influence of noise mixed in the sampled analog data on the conversion accuracy to digital data. it can. In addition, since the sampling time for obtaining digital data can be made equal for each digital data, the accuracy of conversion to digital data can be increased.

It is a block diagram which shows the outline of a structure of the weight scale of one Embodiment of this invention. It is a block diagram which shows the outline of a structure of AD converter with which the weight scale shown in FIG. 1 is provided. 3 is a timing chart for explaining the operation of the AD converter shown in FIG. 2. It is a block diagram which shows the outline of a structure of the successive approximation type AD converter to which this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Weight scale 2 Differential amplifier circuit 3 Double integration type AD converter 4 Display apparatus 31 Integration circuit 32 Comparator 33 Control apparatus 33a Memory | storage circuit 34 Clock pulse generation circuit 35 Counter 5 Successive comparison type AD converter 51 Sample hold circuit 52 Analog Comparator 53 Control device 53a Successive comparison register 54 DA converter

Claims (4)

An AD converter for integrating an input signal ,
An AD converter characterized in that analog data is sampled at least at a conversion operation time different from the previous sampling.   Each time analog data is sampled and converted to a digital value, it is added to the cumulative value of the converted digital value based on the previous one or multiple times of sampling, and the digital data output based on the addition result is added. The AD converter according to claim 1, wherein the AD converter is specified.   A value obtained by adding the conversion operation time for sampling the analog data to the cumulative value of the conversion operation time during the sampling of the cumulative number over a plurality of times is equal to each sampling time point. 3. The AD converter according to claim 1, wherein sampling of analog data is performed.   The analog data supplied from the measuring instrument for measuring the applied load is converted into a digital value by the AD converter according to claim 1 to obtain digital data. .

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