JP5165708B2 - Capacitance measurement circuit - Google Patents

Description

  The present invention relates to a capacitance measurement circuit, and more particularly to a capacitance measurement circuit capable of reducing noise.

  The capacitance measurement circuit is a circuit for measuring capacitance, and is mainly used for measuring the capacitance of various circuits or elements. Recently, however, various portable devices have provided user interfaces such as a touch pad, a touch screen, and a proximity sensor, thereby expanding the application range of a capacitance measurement circuit that senses a user's contact and proximity.

  FIG. 1 is a diagram showing an example of a conventional touch sensor, which is disclosed in Patent Document 1. As shown in FIG. 1 includes a measurement signal generator 10, a reference signal generator 20, a plurality of sensing signal generators 30-1 to 30-n, a plurality of variable delay units 35-1 to 35-n, and a plurality of sensors. The contact signal generators 40-1 to 40-n and the controller 50 are provided.

  The measurement signal generator 10 generates a clock signal as the measurement signal in and applies it to the reference signal generator 20 and the plurality of sensing signal generators 30-1 to 30-n.

  The reference signal generator 20 includes a first resistor R1-1 and a capacitor C, and always generates the reference signal ref by delaying the measurement signal in by a predetermined time regardless of the contact of the object. The first resistor R1-1 and the capacitor C are for setting a delay value of the reference signal ref with respect to the variable delay signals Vsen2-1 to Vsen2-n.

  Each of the plurality of sensing signal generators 30-1 to 30-n includes second resistors R2-1 to R2-1 positioned between the measurement signal generator 10 and each of the plurality of variable delay units 35-1 to 35-n. Positioned between R2-n, the second resistors R2-1 to R2-n, and each of the plurality of variable delay units 35-1 to 35-n, a contact object having capacitance is contacted. A pad PAD is provided. Each of the plurality of second resistors R2-1 to R2-n adjusts the delay component equally between the measurement signal generator 10 and each of the plurality of pads PAD. Each of the plurality of sensing signal generators 30-1 to 30-n includes a pad PAD with which a contact object comes into contact. When the contact object comes into contact with the pad PAD, the measurement signal in is delayed more than the reference signal ref. When not touched, the sensing signals sen2-1 to sen2-n are generated so that the measurement signal in is delayed to be smaller than the reference signal ref, and a delay time difference from the reference signal ref is generated.

  The contact object may be any object having a predetermined capacitance, and a typical example thereof is a human body that accumulates a large amount of charges.

  Each of the plurality of variable delay units 35-1 to 35-n varies the delay time of the sensing signals sen2-1 to sen2-n in response to the control signals D1 to Dn supplied from the control unit 50. The variable delay signals Vsen2-1 to Vsen2-n are output according to the delayed time. Each of the variable delay units 35-1 to 35-n can be composed of a plurality of delay cells and a buffer, and each of the plurality of delay cells is composed of one multiplexer and two inverters.

  The multiplexer includes two inputs, one output, and a selection input for selecting one of the two inputs. The selection input corresponds to one of control signals D1 to Dn supplied from the control unit 50. Controlled by a control signal. The two inverters serve to delay the output of the multiplexer by a predetermined time.

  Each of the plurality of contact signal generators 40-1 to 40-n samples and latches the variable delay signals VsenVsen2-1 to VsenVsen2-n in synchronization with the reference signal ref and outputs the contact signals S1 to Sn. Each of the plurality of contact signal generators 40-1 to 40-n receives the variable delay signals Vsen2-1 to Vsen2-n from the corresponding variable delay units 35-1 to 35-n, and the reference signal generator 20 It is configured as a D-flip-flop that receives the reference signal ref at the clock input CLK and generates the contact signals S1 to Sn.

  The control unit 50 senses that the contact sensor is in an operating state when a contact object is brought into contact with the pad PAD and the contact signals S1 to Sn continuously change, and the contact signal generation unit 40 corresponding to the touched pad PAD. The contact signals S1 to Sn are received from -1 to 40-n to generate contact outputs Tout-1 to Tout-n, the contact object is not contacted with the pad PAD, and the contact signals S1 to Sn do not change for a predetermined time. Then, the control unit 50 senses that the contact sensor is in a standby state, and starts adjusting the control signal supplied to each of the plurality of variable delay units 35-1 to 35-n for delay time adjustment.

  FIG. 2 is a diagram showing another example of a conventional touch sensor, which is disclosed in Patent Document 2. In FIG. The pulse signal generator 60 sets the pulse width of the pulse signal pul in accordance with the code value of the control code Code transmitted from the controller 90, and generates a pulse signal pul having the set pulse width.

  The pulse signal generator 60 includes a clock signal generator 61, a variable delay chain VDC, an inverter INV, and an AND gate AND. The clock signal generator 61 generates a clock signal clk and transmits it to the variable delay chain VDC and the AND gate AND. The variable delay chain VDC varies the delay time of the clock signal clk in response to the code value of the control code Code transmitted from the control unit 90. Inverter INV inverts clock signal dclk output from variable delay chain VDC. The AND gate AND is a pulse corresponding to the delay time of the variable delay chain VDC by AND-combining the clock signal clk transmitted from the clock signal generator 61 with the clock signal / dclk transmitted via the variable delay chain VDC and the inverter INV. A pulse signal pul having a width is generated.

  The pulse signal transmission unit 70 including the resistor R3 and the pad PAD transmits the pulse signal pul as it is to the pulse signal detection unit 80 when a contact object is not in contact with the pad PAD, but has a predetermined capacitance. When an object is touched, the pulse signal pul cannot be transmitted to the pulse signal detector 80 due to the capacitance of the contact object applied to the pad PAD.

  At this time, any object having a predetermined capacitance can be used as the contact object, and a typical example thereof is a human body that accumulates a large amount of electric charge.

  The pulse signal detector 80 detects the pulse signal pul transmitted from the pulse signal transmitter 70 and transmits the detection result to the controller 90. The pulse signal detector 80 can be realized as a T-flip flop TFF.

  The T flip-flop TFF toggles the output signal in synchronization with the rising edge or the falling edge of the pulse signal pul when the pulse signal pul is transmitted, and does not toggle the output signal when the pulse signal pul is not transmitted.

  The control unit 90 generates an output signal out for transmitting the contact possibility of the contact object based on the detection result of the pulse signal detection unit 80, outputs the output signal out to the external device, periodically performs the calibration operation, and performs the pulse signal pul in the non-contact state. Calibrate the pulse width to match the current operating environment. The controller 90 outputs an output signal out indicating that the contact object is not in contact when the T-flip flop TFF outputs an output signal toggling, and otherwise outputs an output signal out indicating that the contact object is contacted. Generate and output to the outside.

  The above-described contact detection sensor of FIGS. 1 and 2 only detects and outputs contact or non-contact, and does not output the magnitude of capacitance. Further, due to the characteristics of the portable device, various changes in the surrounding environment occur, and a capacitance measurement circuit is required to reduce the influence of noise so that the portable device does not malfunction due to various noises caused by the environmental change.

Korean Patent Gazette No. 0683249 Specification Korean Patent Gazette No. 0802656 Specification

  In order to solve the above problems, a capacitance measurement circuit of the present invention includes a measurement signal generation unit that generates a measurement signal, a fixed delay chain that outputs the measurement signal with a delay corresponding to a reference delay value, and the above A variable delay chain that outputs a measurement signal delayed by a time corresponding to a code value, a first delay unit that outputs a reference signal by delaying the output signal of the fixed delay chain, and a capacitance from the outside A second delay unit that includes a pad to be applied, variably delays the output signal of the variable delay chain in response to a capacitance applied through the pad, and outputs the sensing signal; the reference signal; and the sensing signal The capacitance value is increased or decreased in response to the delay time difference from the output, and the code value is output in response to the capacitance value. Characterized in that it comprises a data generator for varying and outputting.

  The data generation unit of the present invention includes a phase detection unit that outputs a sensing signal in response to a delay time difference between the reference signal and the sensing signal, and a capacitance value in accordance with a specified rule in response to the sensing signal. And a delay pump for sequentially increasing or decreasing and outputting the code value in response to the capacitance value and outputting the code value to the variable delay chain.

  The phase detector of the present invention is a logic circuit that latches the sensing signal in synchronization with the rising edge or falling edge of the reference signal and outputs the sensing signal, and is a flip-flop. To do.

  In the capacitance measuring circuit of the present invention, the delay pump outputs a capacitance value sequentially increased or decreased according to a specified rule in response to the sensing signal, and outputs the capacitance value from the reference delay value. A subtractor that subtracts and outputs the code value is provided.

  The counter according to the present invention is characterized in that the capacitance value is sequentially increased or decreased in designated units in response to the sensing signal.

  The counter according to the present invention is characterized in that, when the sensing signal is continuously applied to a high level or a low level, it is output by increasing or decreasing sequentially while changing the capacitance value in units of change.

  The delay pump according to the present invention further includes a digital filter that filters and outputs the code value or the capacitance value.

  The digital filter of the present invention is a low-pass filter or a band-pass filter that applies the code value or the capacitance value to be stabilized and removes noise.

  Further, the present invention includes a pulse signal generator that generates a pulse signal by varying the pulse width of the clock signal in response to the capacitance value of the present invention, and a pad for applying capacitance from the outside, and the pulse signal is applied from the pad. A pulse signal transmission unit that transmits or does not transmit the pulse signal in response to a capacitance applied, and a periodic detection of the pulse signal applied through the pulse signal transmission unit to detect a sensing signal. A pulse signal detector for outputting, a counter for sequentially increasing or decreasing a counting value in response to the sensing signal, and a digital for filtering the counting value and outputting the capacitance value And a filter.

  The pulse signal generator of the present invention includes a clock signal generator that generates the clock signal, a variable delay chain that variably delays and outputs the clock signal according to the capacitance value, and an output signal of the variable delay chain. An inverter that outputs the inverted signal; and an AND gate that ANDs the clock signal and the output signal of the inverter to generate the pulse signal having a pulse width corresponding to a delay time of the clock signal. And

  The pulse signal detection unit of the present invention senses the pulse signal in response to a clock signal and generates a toggled output signal in response to the pulse signal, and the T-flip flop. And a period discriminator that discriminates whether or not the output signal is periodically toggled and outputs a sensing signal.

  The pulse signal detection unit of the present invention includes an SR flip-flop that outputs the sensing signal in response to the pulse signal applied to any one of a set terminal and a reset terminal, and the clock signal. A D-flip-flop that latches and outputs the sensing signal in response, and selects one of the set terminal or the reset terminal in response to the output signal of the D-flip-flop and outputs the pulse signal. And a multiplexer for transmission.

  The counter according to the present invention is characterized in that in response to the sensing signal, the capacitance value is sequentially increased or decreased in a designated unit and output.

  The counter according to the present invention is characterized in that, when the sensing signal is continuously applied to a high level or a low level, it is outputted by increasing or decreasing sequentially while changing the capacitance value to a change unit.

  As described above, according to the present invention, the capacitance measuring circuit is configured such that the pad to which the capacitance is applied from the outside is disposed inside the feedback loop, and the capacitance value is increased or decreased in sequence to thereby increase or decrease the capacitance value. Since it is less affected, it is possible to measure an accurate capacitance value.

It is a figure which shows an example of the conventional touch sensor. It is a figure which shows the other example of the conventional touch sensor. It is a figure which shows an example of the capacitance measurement circuit which concerns on embodiment of this invention. It is a figure which shows the capacitance measurement circuit of FIG. 3 which shows the implementation example of delay time calculation and a data generation part. FIG. 5 is a diagram for explaining the operation of the capacitance measurement circuit of FIG. 4. FIG. 5 is a diagram for explaining the operation of the capacitance measurement circuit of FIG. 4. FIG. 5 is a diagram for explaining the operation of the capacitance measurement circuit of FIG. 4. It is a figure which shows the other example of the capacitance measurement circuit which concerns on embodiment of this invention. It is a figure which shows the implementation example of the T-flip-flop of FIG.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  FIG. 3 is a diagram showing an example of a capacitance measuring circuit according to the present invention. The capacitance measurement circuit of FIG. 3 includes a measurement signal generation unit 110, a variable delay unit 120, a fixed delay unit 130, and a delay time calculation and data generation unit 140, similar to the touch sensor of FIG. The measurement signal generation unit 110 can be realized as a clock generation circuit that generates a clock signal having a predetermined period as the measurement signal in.

  The variable delay unit 120 includes a variable delay chain VDC and a resistor R1 connected in series between the measurement signal generation unit 110 and the data generation unit 140. The pad PAD is connected between the resistor R1 and the data generator 140 and applies a capacitance from the outside. The variable delay chain VDC outputs the measurement signal in with variable delay in response to the code value Code fed back and applied from the delay pump 142, and the resistor R1 and the pad PAD are variable delay applied from the variable delay chain VDC. The measured signal is delayed by the resistance value of the resistor R1 and the capacitance applied through the pad PAD, and the sensing signal sen is output to the delay time calculation and data generation unit 140.

  The fixed delay unit 130 is connected in parallel with the variable delay unit 120, and includes a fixed delay chain FDC and a resistor R2 connected in series between the measurement signal generation unit 110 and the data generation unit 140. The fixed delay chain FDC applies a reference delay value Nref for adjusting the zero point of the code value Code applied to the variable delay chain in order to compensate the offset capacitance of the pad PAD and maximize the capacitance measurement range. The fixed delay chain FDC delays and outputs the measurement signal in response to the reference delay value Nref, and the resistor R2 further delays the measurement signal output after being delayed from the fixed delay chain FDC by the resistance value. Is output to the delay time calculation and data generation unit 140.

  The fixed delay chain FDC and the variable delay chain VDC are composed of a plurality of delay cells like the variable delay chains 35-1 to 35-n in FIG. 1, and each of the plurality of delay cells is one multiplexer MUX. And two inverters. The fixed delay chain FDC selects a delay cell that delays the measurement signal in response to the reference delay value Nref, and the variable delay chain VDC selects a delay cell that delays the measurement signal in response to the code value Code.

  The delay time calculation and data generation unit 140 includes a phase detection unit 141 and a delay pump 142. The phase detection unit 141 determines whether the phase of the sensing signal sen with respect to the reference signal ref is early or late, and outputs the sensing signal det. The delay pump calculates a capacitance value CV in response to the sensing signal det, and outputs the code value Code up or down in response to the calculated capacitance value CV.

  In the capacitance measurement circuit of FIG. 3, the variable delay unit 120 and the fixed delay unit 130 apply the measurement signal in directly from the measurement signal generator 110 to the variable delay chain VDC and the fixed delay chain FDC, respectively. Accordingly, the pad PAD to which the capacitance is applied from the outside is disposed between the variable delay chain VDC that applies the feedback capacitance value CV and the delay time calculation and data generation unit 140 that outputs the capacitance value CV. A pad PAD is disposed inside a feedback loop.

  Although noise is also generated from the inside of the capacitance measuring circuit, it is almost always introduced from the outside through the pad PAD. That is, in order to reduce noise, it is most efficient to remove noise applied from the pad PAD. However, in the case of the touch sensor of FIG. 1, since the pad PAD is connected outside the feedback loop, it is difficult to reduce noise applied from the pad PAD. On the other hand, in the capacitance measuring circuit of FIG. 3, a pad PAD for applying capacitance from the outside is connected to the inside of the feedback loop. When the pad is connected inside the feedback loop, noise can be attenuated by the characteristics of the feedback loop.

  FIG. 4 is a diagram illustrating a capacitance measurement circuit, which is an implementation example of the delay time calculation and data generation unit of FIG. In FIG. 4, the measurement signal generator 110, the variable delay unit 120, and the fixed delay unit 130 are the same as those in FIG.

  In the delay time calculation and data generation unit 140 of FIG. 4, the phase detection unit 141 is realized as a D-flip flop DFF, and the delay pump 142 includes a counter CNT and a subtracter sub. The D flip-flop DFF latches and outputs the sensing signal sen in synchronization with one of the rising edge or the falling edge of the reference signal ref. The D flip-flop DFF outputs a low level sensing signal det when the delay of the sensing signal sen is smaller than the reference signal ref, and outputs a high level sensing signal when the delay of the sensing signal sen is larger than the reference signal ref. det is output. If the sense signal is low level, the delay pump 142 increases the code value Code, and if the sense signal is high level, the delay pump 142 is variable by performing a negative feedback action to decrease the code value Code. Control is performed so that the phase of the output signal sen of the delay unit 120 matches the phase of the output signal ref of the fixed delay unit 130. The pad PAD may cause a delay offset between the fixed delay unit 130 and the variable delay unit 120. If this offset is large and exceeds the adjustment range of the variable delay chain, the operation range of the capacitance measurement circuit of FIG. Will deviate from. In this case, the reference delay value Nref of the fixed delay unit 130 compensates for the offset capacitance so that the code value Code of the variable delay chain falls within the variable delay range. In FIG. 4, the D-flip flop DFF is used as an example of the phase detector 141, but may be realized by another logic circuit.

  The counter CNT is an up / down counter that outputs the capacitance value CV up or down in response to the sensing signal det. The counter CNT can output the capacitance value CV up or down in units of 1 bit according to the level of the sensing signal det. However, if the counter CNT outputs the capacitance value CV up or down in units of 1 bit, the time for measuring the capacitance becomes long when the capacitance applied from the pad PAD is large. In order to compensate for such a problem, the counter CNT does not increase / decrease the capacitance value CV in 1-bit units, and if the sensing signal det is continuously applied to the high level or the low level, the counter CNT has 1 bit, 2 bits, The capacitance value CV can be increased or decreased in proportion to a multiplier of 2 in the order of 4 bits and 8 bits, or the capacitance value CV can be increased or decreased according to a predetermined rule. In the above description, the counter CNT applies the sensing signal det in response to the reference signal ref. However, the sensing signal det can also be applied in response to the measurement signal in.

  The subtracter sub subtracts the capacitance value CV from the reference delay value Nref and outputs a code value Code. Accordingly, the capacitance value CV indicates all capacitance values applied to the pad PAD, but when the capacitance value applied to the pad PAD increases, a feedback loop including the phase detector 141 and the delay pump 142 is applied from the pad PAD. As the capacitance increases, the code value Code is decreased to reduce the delay amount of the variable delay chain. Further, when the capacitance value applied to the pad PAD decreases, the code value Code is increased by the amount of the decrease, and the delay amount of the variable delay chain is increased. As a result, the sensing signal sen input to the phase detector 141 and the reference signal ref are controlled to have the same phase, and the capacitance value CV corresponds to the magnitude of the capacitance applied to the pad PAD.

  Here, the reference delay value Nref applied to the subtracter sub and the signal for controlling the fixed delay chain FDC have been described in the same manner, but they can be controlled by other methods. 3 and 4 have been described on the assumption that there is a fixed delay chain FDC, it may be deleted.

  5 to 7 are diagrams for explaining the operation of the capacitance measuring circuit of FIG. 4. FIG. 5 shows changes in the sensing signal sen and the sensing signal det when a capacitor is applied to the pad PAD. FIG.

  Since the reference signal ref is output from the fixed delay unit 130 after being delayed by the fixed delay time of the measurement signal in, the reference signal ref has the same cycle as the measurement signal in. Since the capacitance value CV is 0 at the first operation of the capacitance measurement circuit, the initial code value Code is equal to the reference delay value Nref, and the time that the variable delay chain VDC delays the measurement signal in is the fixed delay chain FDC Equal to delay time. Therefore, the sensing signal sen is output to the D-flip-flop DFF after the sensing signal sen is delayed further than the reference signal ref by the capacitance of the pad PAD itself in the initial operation of the capacitance measuring circuit.

  Since the sensing signal sen is further delayed from the reference signal ref, the sensing signal sen becomes high level at the falling edge of the reference signal ref, and the sensing signal det is output as high level. Since the sensing signal det is at a high level, the counter CNT increases the capacitance value CV and outputs 1, and the subtracter sub subtracts the capacitance value CV from the reference delay value Nref, so that the code value Code is pumped down. And output as a reference delay value Nref-1.

  The variable delay chain VDC reduces and outputs the delay time of the measurement signal in in response to the code value Code, and the delay time difference from the reference signal ref is reduced by reducing the delay time of the sensing signal sen. When the delay time difference between the sensing signal sen and the reference signal ref is gradually reduced and the delay time of the sensing signal sen is equal to or shorter than the delay time of the reference signal ref (t1), the D-flip flop DFF Causes the sensing signal det to transition to a low level.

  Thereafter, when a capacitance is applied from the outside through the pad PAD (t2), the sensing signal sen is further delayed by the applied capacitance, and the D-flip flop DFF outputs a high level sensing signal det. When the sensing signal det is output at a high level, the capacitance value CV is gradually increased until the delay time of the sensing signal sen is equal to or shorter than the delay time of the reference signal ref as described above (t3). . Thereafter, the capacitance value CV repeatedly increases and decreases.

  FIG. 6 is a diagram showing a change in the capacitance value CV of the capacitance measurement circuit including the counter CNT that increases / decreases the capacitance value CV by 1 bit unit, and FIG. 7 increases / decreases the capacitance value CV according to a specified rule. It is a figure which shows the change of the capacitance value CV of a capacitance measurement circuit provided with counter CNT.

  In FIG. 6, since the counter CNT performs up / down in 1-bit units, when the capacitance applied from the pad PAD is large, the time required until the capacitance to which the capacitance value CV is applied is indicated. However, similarly, since the counter CNT performs up / down in 1-bit units, even if a large amount of noise is temporarily applied, the capacitance value CV that is fluctuated by the noise is 1 bit and has an effect on the capacitance value CV. There are few.

  In FIG. 7, when the sensing signal det is applied to the high level or the low level three times continuously according to the rule that the counter CNT increases / decreases the capacitance value CV, the number of bits to be increased / decreased is increased. An example is shown. That is, when the sensing signal det is continuously applied at a high level, the number of bits that are increased every three times is increased. For example, when the sensing signal det is continuously applied to a high level or a low level, a 1-bit capacitance value is varied for three times, and a 2-bit capacitance value is varied for the subsequent three times. When the sense signal det is inverted to a low level, the previous number of bits to be increased / decreased is decreased and the capacitance value CV is decreased. Therefore, even if a large capacitance is applied, the capacitance value CV can be shown early. The capacitance value CV shown in FIG. 7 can be changed much more than the capacitance value CV shown in FIG. 6 when noise occurs. However, since the limit of the change width is not large, the influence of noise on the capacitance value CV is small. In particular, since the pad PAD is arranged inside the feedback loop, the variable delay chain VDC directly applies the measurement signal in that does not include noise, and the code value Code reflecting the noise applied through the pad PAD. Since the output is delayed in response to the noise, the noise is reduced by the characteristics of the feedback loop.

  In the above description, the data generation unit 140 includes the D-flip flop DFF and the up / down counter CNT, and gradually increases / decreases the capacitance value CV. However, the delay time difference of the sensing signal sen with respect to the reference signal ref is described. By directly counting, the capacitance value CV applied to the pad PAD can be output immediately.

  The delay pump 142 may further include a digital filter that filters and outputs the capacitance value CV to remove noise. In the above-described embodiment, the capacitance value CV is output so that the change width is limited. Therefore, the change width of the code value Code is also limited. However, if the code value Code changes within a predetermined level or more, it is determined that noise is included. Therefore, a digital low-pass filter or a digital band-pass filter can be further provided as a digital filter that applies the code value Code from the subtracter sub, filters it, and outputs it to the variable delay chain VDC. Further, the same effect can be obtained by directly filtering and outputting the capacitance value CV without filtering the code value Code. The digital filter is used to adjust the characteristics of the feedback loop along with the noise characteristics of the capacitance measurement circuit. Then, when the delay time difference between the reference signal ref and the sensing signal sen becomes sufficiently small and the feedback loop is stabilized, the capacitance value CV oscillates in increments of + 1 / -1 (repetitively increases and decreases). However, this can be fixed using a digital filter. That is, it is possible to give a hysteresis characteristic to the digital filter so that the digital filter is in a stable state, thereby preventing fine oscillation (continuous fluctuation) of the capacitance value CV.

  Furthermore, the counter CNT and the digital filter can be realized as software as well as hardware.

  FIG. 8 is a diagram showing another example of the capacitance measuring circuit according to the present invention. The pulse signal generator 210 and the pulse signal transmitter 220 have the same configuration as that of FIG.

  Further, only the T-flip flop TFF is used in the pulse signal detector 80 of FIG. However, as described above, most of the noise is often applied from the pad PAD, and the T-flip-flop TFF in FIG. 2 is directly connected to the pad PAD. When applied, the T-flip flop TFF may be toggled one or more times in one pulse signal. In order for the period discriminator 232 of FIG. 8 to accurately discriminate the periodicity of the pulses, it is required that the T-flip flop TFF is toggled only once for one pulse input. In order to solve such a problem, the T-flip flop TFF in FIG. 8 toggles one pulse input only once, and this corresponds to the toggle circuit in FIG.

  In the pulse signal detection unit 230 of FIG. 8, the T-flip flop 231 applies the pulse signal pul in response to the clock signal clk, so that the output signal of the T-flip flop 231 is not toggled by noise. 8 further includes a period discriminator 232 that discriminates whether or not the output signal of the T-flip flop 231 is periodically toggled. The period discriminator 232 determines whether the output signal of the T-flip flop 231 periodically changes in response to the clock signal clk, and when the output signal of the T-flip flop 231 periodically changes, A low level sensing signal det is output, and if there is no periodic transition, a high level sensing signal det is output.

  2 can sense only contact or non-contact, but the capacitance measurement circuit of FIG. 8 must measure the magnitude of the capacitance applied from the pad PAD and output the capacitance value CV. Therefore, the delay pump 240 includes a counter 241 and a digital filter 242 as shown in FIG. The counter 241 is an up / down counter that applies the sensing signal det in response to the clock signal clk, and outputs the counter value Cout up or down according to a 1-bit unit or a specified rule. As described above, the digital filter 242 is used to adjust the characteristic of the feedback loop together with the noise characteristic of the capacitance measuring circuit, and has a hysteresis characteristic to filter the counter value Cout and output the capacitance value CV to output the capacitance value. Continuous fluctuation of CV can be prevented.

  In the above description, the counter 241 applies the sensing signal det in response to the clock signal clk. However, when the counter 241 is an asynchronous counter, the clock signal clk may not be applied. Then, in order to determine whether or not the period discriminator 232 and the output signal of the T-flip flop 231 are periodically toggled, another signal other than the clock signal clk can be used.

  The variable delay chain VDC in FIG. 8 outputs the clock signal clk with variable delay in response to the capacitance value CV.

  FIG. 9 is a toggle circuit showing an implementation example of the T-flip-flop of FIG. 8, and includes one multiplexer Mux, SR flip-flop SRF, and D-flip-flop DF.

  The multiplexer 331 applies the pulse signal pul in response to the output signal of the D flip-flop 333 and applies it to the set terminal S or the reset terminal R of the SR flip-flop 332. The multiplexer 331 applies the pulse signal pul to the set terminal S when the sensing signal det is applied at a low level, and applies the pulse signal pul to the reset terminal R when the sensing signal det is at a high level.

  If no pulse signal is applied from the multiplexer 331, the SR flip-flop 332 maintains the previous sense signal det level as it is, and if a high level signal is applied to the set terminal S, the SR flip-flop 332 outputs the high level sense signal det to the delay pump 340. When a high level signal is applied to the reset terminal R, a low level sensing signal det is output.

  The D flip-flop 333 latches the sensing signal det in response to the clock signal clk applied from the clock signal generator 311 and outputs the latched signal to the multiplexer 331. Whether the D-flip flop 333 latches the sensing signal det in response to the clock signal clk, and causes the output signal of the multiplexer 331 to be applied to one of the set terminal S and the reset terminal R of the SR flip-flop 332 To decide.

  The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious that a person having ordinary knowledge in the technical field to which the present invention pertains can come up with various changes or modifications within the scope of the technical idea described in the claims. Of course, it is understood that these also belong to the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 110 Measurement signal generation part 120 Variable delay part 130 Fixed delay part 140 Data generation part 141 Phase detection part 142 Delay pump FDC Fixed delay chain VDC Variable delay chain

Claims (22)

A measurement signal generator for generating a measurement signal;
A fixed delay chain that outputs the measurement signal with a delay corresponding to a reference delay value; and
A variable delay chain that delays and outputs the measurement signal by a time corresponding to the code value;
A first delay unit that outputs a reference signal by delaying the output signal of the fixed delay chain by a fixed time;
A second delay unit comprising a pad for connecting a capacitance from the outside, and outputting a sensing signal by variably delaying the output signal of the variable delay chain in response to the capacitance connected from the pad;
A data generation unit that increases or decreases the capacitance value in response to a delay time difference between the reference signal and the sensing signal and outputs the code value in response to the capacitance value. ,
The data generator outputs a sensing signal in response to a delay time between the reference signal and the sensing signal, and when the sensing signal is continuously applied to a high level or a low level, a capacitance value changing unit. Capacitance measuring circuit, wherein the output is sequentially increased or decreased while changing the output. The data generator is
A phase detector that outputs a sensing signal in response to a delay time difference between the reference signal and the sensing signal;
A delay pump that sequentially increases or decreases a capacitance value in response to the sensing signal according to a specified rule, outputs the capacitance value in response to the capacitance value, and outputs the code value to the variable delay chain; ,
The capacitance measurement circuit according to claim 1, further comprising: The phase detector
3. The capacitance measuring circuit according to claim 2, wherein the capacitance measuring circuit is a flip-flop that is a logic circuit that latches the sensing signal in synchronization with an rising edge or a falling edge of the reference signal and outputs the sensing signal. . The delay pump is
A counter that outputs a capacitance value sequentially increasing or decreasing according to a specified rule in response to the sensing signal;
A subtractor that subtracts the capacitance value from the reference delay value and outputs the code value;
The capacitance measurement circuit according to claim 2, further comprising: The counter is
5. The capacitance measuring circuit according to claim 4, wherein a capacitance value is sequentially increased or decreased in a specified unit in response to the sensing signal. The counter is
5. The capacitance measuring circuit according to claim 4, wherein when the sensing signal is continuously applied to a high level or a low level, the capacitance is changed in increments or decrements sequentially while changing a capacitance value changing unit. . The delay pump is
The capacitance measurement circuit according to claim 4, further comprising a digital filter that filters and outputs the code value or the capacitance value. The digital filter is
The capacitance measurement circuit according to claim 7, wherein the capacitance measurement circuit is a low-pass filter or a band-pass filter that applies the code value or the capacitance value to be stabilized and removes noise. The counter and the digital filter are:
The capacitance measurement circuit according to claim 7, which is implemented as software. The counter is
5. The capacitance measuring circuit according to claim 4, wherein the sensing signal is applied in response to the reference signal. The counter is
The capacitance measuring circuit according to claim 4, wherein the sensing signal is applied in response to the measuring signal. The first delay unit includes:
The capacitance measuring circuit according to claim 2, wherein the capacitance measuring circuit is a first resistor connected between the fixed delay chain and the phase detector. The second delay unit is
The capacitance measuring circuit according to claim 12, further comprising a second resistor connected between the variable delay chain and the phase detector. A pulse signal generator for generating a pulse signal by varying the pulse width of the clock signal in response to the capacitance value;
A pulse signal transmission unit comprising a pad for connecting a capacitance from the outside, and transmitting or not transmitting the pulse signal in response to the capacitance connected from the pad;
A pulse signal detection unit that periodically detects the pulse signal applied via the pulse signal transmission unit and outputs a sensing signal;
A counter that outputs a counting value sequentially increasing or decreasing according to a specified rule in response to the sensing signal;
A digital filter that filters the counting value and outputs the capacitance value;
With
When the sensing signal is continuously applied to a high level or a low level, the counter sequentially increases or decreases and outputs a capacitance value changing unit. The pulse signal generator is
A clock signal generator for generating the clock signal;
A variable delay chain for delaying and outputting the clock signal according to the capacitance value;
An inverter that inverts and outputs the output signal of the variable delay chain;
ANDing the clock signal and the output signal of the inverter to generate the pulse signal having a pulse width corresponding to the delay time of the clock signal;
The capacitance measurement circuit according to claim 14, further comprising: The pulse signal transmission unit is
15. The device according to claim 14, further comprising a resistor connected between the pulse signal generation unit and the pulse signal detection unit, and a capacitance that suppresses transmission of the pulse signal together with a capacitance connected from the pad. Capacitance measurement circuit. The pulse signal detector is
A T-flip flop that senses the pulse signal in response to a clock signal and generates an output signal toggling in response to the pulse signal;
A period discriminator for discriminating whether an output signal of the T-flip flop is periodically toggled and outputting a sensing signal;
The capacitance measurement circuit according to claim 14, further comprising: The T-flip flop is
An SR flip-flop that outputs the sensing signal in response to the pulse signal applied to any one of a set terminal or a reset terminal;
A D-flip-flop that latches and outputs the sensing signal in response to the clock signal;
A multiplexer that selects one of the set terminal or the reset terminal in response to an output signal of the D-flip flop and transmits the pulse signal;
The capacitance measurement circuit according to claim 17, further comprising: The counter is
15. The capacitance measuring circuit according to claim 14, wherein a capacitance value is sequentially increased or decreased in a specified unit in response to the sensing signal. The counter is
15. The capacitance measuring circuit according to claim 14, wherein if the sensing signal is continuously applied to a high level or a low level, the capacitance signal is sequentially increased or decreased while changing a capacitance value changing unit. . The digital filter is
15. The capacitance measuring circuit according to claim 14, wherein the capacitance measuring circuit is a low-pass filter or a band-pass filter that applies the counting value to be stabilized, removes noise, and outputs the capacitance value. The counter and the digital filter are:
15. The capacitance measuring circuit according to claim 14, which is realized as software.

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