JP5143272B2 - Method for manufacturing EL display device - Google Patents

Description

  The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic apparatus in which such an electro-optical device is mounted as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices. In particular, thin film transistors are urgently developed as switching elements for image display devices (liquid crystal display devices and EL display devices).

  In a TFT used as a switching element, an amorphous silicon film or a polysilicon film is used as a semiconductor layer. When a glass substrate is used, a processing temperature in the TFT manufacturing process is about 400 ° C. to 600 ° C. . The polysilicon film is formed by laser crystallization or solid phase crystallization (600 to 1000 ° C.).

Currently, many glass substrates and quartz substrates are used, but they have the disadvantage of being easily broken and heavy. Further, in mass production, it is difficult to increase the size of a glass substrate or a quartz substrate, which is not suitable. Therefore, attempts have been made to form TFT elements on a flexible substrate, typically a flexible plastic film.

  In addition, in forming a TFT, a source region and a drain region are formed, so that doping with an impurity element is indispensable and occupies an extremely important position. As a typical impurity element doping method, an ion implantation method or an ion doping method can be given.

  After an impurity element imparting n-type conductivity is added to the semiconductor layer by a doping method of these impurity elements, a heat treatment for activation or a strong light irradiation treatment such as a laser is indispensable.

  In general, it is said that a heat treatment at a high temperature close to 1000 ° C. is necessary for the activation of the impurity element. However, when a glass substrate is used, a heat treatment above the strain point of the substrate cannot be performed. Heat treatment (500-600 ° C.) was required, and the throughput was deteriorated. In the case of using a glass substrate, this processing temperature (500 ° C. to 600 ° C.) was the highest process temperature in the manufacturing process of TFT activated by heat treatment.

  Also, when using a plastic substrate, the heat resistance is further low, so the maximum temperature of the process must be lowered, and as a result, TFTs with better electrical properties cannot be formed when formed on a glass substrate. is there. Therefore, a high-performance liquid crystal display device or light emitting element using a plastic film has not been realized.

  In particular, in the case of using an ion doping method, when an impurity element imparting n-type conductivity is added, the doped region of the crystalline semiconductor layer is damaged by the impurity element and becomes an amorphous region, which has a high resistance. It was converted. For this reason, conventionally, the crystallinity of the source region and the drain region is recovered by heat treatment at 500 ° C. to 600 ° C. and laser irradiation treatment to reduce the resistance.

  In addition, when the ion implantation method using ion mass separation is used, the impurity concentration and implantation depth can be accurately controlled. However, since the ion beam width of the ion implantation apparatus is very small, mass production using a large substrate is possible. Was unsuitable.

In addition, when laser light is used for activation, the activation process can be performed at a low temperature, but the controllability is poor and the throughput is poor because it is necessary to perform the process for each substrate.
Further, if laser treatment is performed on the doped substrate, chamber contamination may occur, and a special laser device or a modification of the device is necessary for activation, leading to an increase in equipment cost. Arise.

  In the TFT manufacturing process according to the above prior art, since the substrate must be heated to 400 ° C. or higher, there is no problem when a glass substrate is used as the substrate, but a low heat resistant substrate such as a plastic substrate is used. In such a case, there has been a problem that it cannot withstand the heating temperature.

  The present invention realizes a further low-temperature process (300 ° C. or lower, preferably 250 ° C. or lower), makes it possible to use a low heat-resistant plastic substrate as an element formation substrate, simplifies the process, and improves the throughput. The task is to do.

  Conventionally, it is difficult to reduce the resistance of amorphous portions of a source region and a drain region formed during doping unless the crystallinity is recovered by high-temperature heat treatment (500 to 600 ° C.) for several hours or laser treatment. Met. In the present invention, the resistance of the source region or the drain region can be reduced without performing such high-temperature heat treatment or laser light irradiation.

  In the present invention, an n-type impurity element and a hydrogen element are added to a semiconductor layer having a crystal structure (crystalline semiconductor layer) at a low acceleration voltage using an ion doping method, and then 100 to 300 ° C., preferably 150 to 250 ° C. By performing this heat treatment, a low resistance source region and drain region are formed. That is, the present invention can form a source region and a drain region which are low resistance at a low temperature in a short time.

In the present invention, in ion doping, it is important that hydrogen added at the same time as an impurity element imparting n-type is present in a high concentration in the source region and the drain region. The resistance of the source region or the drain region can be reduced by performing hydrogen diffusion by performing a heat treatment at 150 to 250 ° C. Note that immediately after ion doping, the concentration of hydrogen contained in the source region and the drain region is 1 × 10 ¹⁹ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²¹ to 1 × 10 ²² / cm ³ or more.

  In the present invention, it is important that the heat treatment in the steps after ion doping is 400 ° C. or lower, preferably 350 ° C. or lower. This is because when heat treatment at about 400 ° C. is performed, hydrogen is desorbed from the semiconductor film. That is, in the processes after ion doping, heat treatment for detaching hydrogen from the film and laser light irradiation are not performed.

  In the present invention, the source region and the drain region are amorphized by ion doping, but it is preferable that the doping conditions are such that they are not completely amorphized. For example, by doping at a low acceleration voltage of 10 kV or less, the upper layer portion in the source region and the drain region is damaged and becomes amorphous, while a crystalline structure remains in the lower layer portion to some extent. That is, the doping conditions are appropriately adjusted so that the impurity element is added at a high concentration toward the upper layer portion, and the impurity element is added at a low concentration toward the lower layer portion. Further, it can be estimated that a large amount of impurity element is added to the amorphous upper layer portion, and a large amount of hydrogen element doped simultaneously with the impurity element is also added. That is, in the present invention, it is desirable to dope hydrogen and impurity elements simultaneously. When only hydrogen is doped, since the mass number and the ion radius are small, the thin semiconductor film penetrates and it is very difficult to add only to the upper layer portion.

In addition, a region that is amorphous by doping with an impurity element (also referred to as an amorphous region) unless high-temperature heat treatment is performed after the heat treatment (100 to 300 ° C.) of the present invention.
Is the state as it is upon completion of the fabrication of the TFT. In other words, in the present invention, at the time of completing the fabrication of the TFT, the channel formation region that is not doped with the impurity element mainly has a crystal structure, and the source region and the drain region mainly have an amorphous state. Conventionally, the source region and the drain region are not kept in an amorphous state, and are recrystallized by heat treatment or laser light.

  In the structure of the invention disclosed in this specification, in a semiconductor device including a TFT over an insulating surface, a channel formation region of the TFT has a crystal structure, and a source region or a drain region of the TFT is mainly non- A semiconductor device having a crystalline structure. Preferably, in the semiconductor device, the channel formation region of the TFT is mainly crystalline, and the source region or drain region of the TFT is mainly amorphous. Here, “mainly” means 50% or more. At least the channel formation region of the TFT has a crystal structure, and at least the upper layer portion of the source region or drain region of the TFT has an amorphous structure.

  Further, according to the present invention, the resistance of the source region and the drain region can be reduced at 300 ° C. or lower, preferably 250 ° C. or lower, and all TFT manufacturing steps can be completed. It is possible to use a plastic substrate having excellent impact properties. Conventionally, since a plastic substrate has a limit in terms of heat resistance, it has been very difficult to manufacture a TFT having excellent characteristics on the plastic substrate.

  In the present invention, heat treatment at 100 to 300 ° C., preferably 150 to 250 ° C. may be performed after doping with an impurity element, and the process order is not particularly limited.

  In addition, if hydrogenation treatment (hydrogen plasma treatment or heat treatment in a hydrogen atmosphere) is performed at 100 to 300 ° C., preferably 150 to 250 ° C. instead of the heat treatment, a higher concentration of hydrogen is contained in the film. And a synergistic effect can be obtained. In this case, the heat treatment step can be reduced and the throughput is improved. Further, the same effect (reduction in resistance of the source region and the drain region) can be obtained even if the TFT manufacturing process other than the hydrogenation process, for example, the film formation process is performed at 100 to 300 ° C.

  Further, if all the circuits on the same substrate, that is, the driver circuit and the pixel TFT are manufactured only by N-channel TFTs, the number of masks can be reduced and the yield can be improved.

  Another structure of the invention disclosed in this specification is a semiconductor device including a pixel portion and a driver circuit over the same insulating surface, wherein the pixel portion and the driver circuit are formed using n-channel TFTs. This is a semiconductor device. The channel formation region of the n-channel TFT is mainly crystalline, and the source region or drain region of the n-channel TFT is mainly amorphous.

In the above structure, the insulating surface is an insulating film surface provided on a plastic substrate.

  In the above structure, a sputtering method, a PCVD method, an LPCVD method, a vacuum evaporation method, a photo CVD method, or the like can be used as a method for forming the semiconductor layer. A film-forming sputtering method is preferred.

  The structure of the TFT is not particularly limited, and may be a top gate type TFT or a bottom gate type TFT.

  The invention for realizing the above structure includes a first step of forming a semiconductor layer having a crystal structure on an insulating surface, and a second step of forming an insulating layer on the semiconductor layer having the crystal structure. A third step of forming a conductive layer on the insulating layer, an impurity element imparting n-type conductivity, and hydrogen to a part of the semiconductor layer having the crystal structure by an ion doping method and adding amorphous A fourth step of forming a quality region, and a fifth step of performing a heat treatment to reduce the resistance value of the amorphous region and using the amorphous region as a source region or a drain region. This is a feature of a method for manufacturing a semiconductor device. Note that a top gate type TFT is formed by these steps.

  In the above structure, the conductive layer is a gate electrode, and the impurity element imparting n-type conductivity and hydrogen are added to the upper layer portion of the semiconductor layer using the conductive layer as a mask.

  According to another aspect of the present invention, there is provided a first step of forming a conductive layer on an insulating surface, a second step of forming an insulating layer on the conductive layer, and a crystal structure on the insulating layer. A third step of forming a semiconductor layer having an amorphous region by adding an impurity element imparting n-type conductivity and hydrogen to a part of the semiconductor layer having the crystal structure by an ion doping method; And a fifth step of reducing the resistance value of the amorphous region by performing a heat treatment and using the amorphous region as a source region or a drain region. Is the method. Note that a bottom gate TFT is formed by these steps.

  In each of the above structures, the heat treatment is performed at a temperature of 100 to 300 ° C., and the resistance of the amorphous region is reduced to form a source region and a drain region. The heat treatment may be a heat treatment in a hydrogen atmosphere.

Alternatively, in the above structure, the heat treatment may be performed by hydrogen plasma treatment at 100 to 300 ° C. to reduce resistance of the source region and the drain region.

In each of the above structures, the insulating surface is an insulating film surface provided on a plastic substrate.

  In each of the above structures, the manufacturing process temperature after the step of adding the impurity element imparting n-type and hydrogen is 350 ° C. or lower, preferably 300 ° C. or lower.

  Each of the above structures is characterized in that the amorphous region is not recrystallized in the manufacturing process after the step of adding an impurity element imparting n-type conductivity and hydrogen.

  Further, the present invention reduces the electric resistance value of the source region and the drain region by heat treatment at a low temperature, and thus is very suitable for a plastic substrate, but it can also be applied to a glass substrate or a quartz substrate. Needless to say, you can. Even when applied to a glass substrate or a quartz substrate, effects such as cost reduction and throughput improvement due to a decrease in process temperature can be obtained.

According to the present invention, since the resistance of the source region and the drain region can be reduced by heat treatment (several minutes) at a low temperature (300 ° C., preferably 250 ° C. or less), a plastic substrate having low heat resistance is used as an element formation substrate. Even when used as a TFT, a TFT having a source region and a drain region having a sufficiently low sheet resistance value can be manufactured. Therefore, it is possible to form a TFT element on a flexible plastic film.

In addition, according to the present invention, an electro-optical device can be manufactured with a very small number of steps and a low temperature and in a short time. Therefore, yield and throughput can be improved, and manufacturing costs can be reduced.

In addition, since an inexpensive electro-optical device can be manufactured, various electric appliances using the electro-optical device for the display portion can be provided at a low price.

10A and 10B show a manufacturing process of a TFT. 10A and 10B illustrate a manufacturing process of an AM-LCD. Example 1 10A and 10B show a manufacturing process of a TFT. (Example 2) 10A and 10B show a manufacturing process of a TFT. (Example 3) The figure which shows the external appearance of AM-LCD. The figure which shows the circuit block diagram of AM-LCD. The graph which shows the experimental result of film thickness 50nm. The graph which shows the experimental result of film thickness 70nm. The graph which shows the experimental result of film thickness 100nm. The figure which shows a Raman scattering spectrum. FIG. 5 is a top view of a pixel portion. FIG. 6 is a cross-sectional view of a pixel portion. The figure which shows the structure of an NMOS circuit. FIG. 6 illustrates a structure of a shift register. FIG. 11 illustrates a structure of an active matrix EL display device. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device. The figure which shows the electrical property (VI characteristic) of TFT.

  Embodiments of the present invention will be described below. An example of the TFT manufacturing method of the present invention is shown in FIG.

  First, the base insulating film 102 is formed over the substrate 101. The substrate 101 is a plastic substrate. For example, polyimide, acrylic, PET (polyethylene terephthalate), polycarbonate (PC), polyarylate (PAR), PEEK (polyetheretherketone), PES (polyethersulfone), PEN (polyether). A plastic substrate made of nitrile), nylon, polysulfone (PSF), polyetherimide (PEI), polybutylene terephthalate (PBT), or the like can be used. Here, an example is shown in which a substrate made of polyimide that can sufficiently withstand heat treatment at 350 ° C. is used.

  The base insulating film 102 is formed by a sputtering method. When the plasma CVD method is used, the film may be formed at a substrate temperature of room temperature to 300 ° C.

Next, an amorphous semiconductor film is formed over the base insulating film 102 by a known technique (a sputtering method, a PCVD method, an LPCVD method, a vacuum evaporation method, a photo CVD method, or the like). Next, the amorphous semiconductor film is crystallized by a known technique to form a crystalline semiconductor film.
However, when a plastic substrate is used, it cannot withstand heat treatment exceeding 400 ° C., and thus it is preferably crystallized by laser light irradiation. Note that in the case of crystallization by laser light irradiation, the amount of hydrogen contained in the amorphous semiconductor film needs to be 5 atom% or less before irradiation, so that the film with a low hydrogen concentration is formed immediately after the film formation. It is preferable to use a method or film forming conditions.

As the laser light, a gas laser such as an excimer laser, a solid-state laser such as a YVO ₄ laser or a YAG laser, or a semiconductor laser may be used. The laser oscillation may be either continuous oscillation or pulse oscillation, and the laser beam may be linear, rectangular, circular, or elliptical. The wavelength used may be any of the fundamental wave, the second harmonic, and the third harmonic. The scanning method may be any of the vertical direction, the horizontal direction, and the diagonal direction, and may be further reciprocated.

  Next, the crystalline semiconductor film is patterned to form a semiconductor layer 103 that becomes an active layer of the TFT. Next, a gate insulating film 104 that covers the semiconductor layer 103 is formed. (FIG. 1A) The gate insulating film 104 is formed by a sputtering method or a plasma CVD method.

  Next, a gate electrode 105 is formed over the gate insulating film. (FIG. 1B) The gate electrode 105 is formed by patterning a conductive film formed by a sputtering method into a desired shape.

  Next, the insulating film is etched using the gate electrode 105 as a mask to form the gate insulating film 106. (Figure 1 (C))

  Next, an impurity element imparting n-type (phosphorus) is doped in a self-aligning manner using an ion doping method. (FIG. 1D) In this doping, it is important to add hydrogen simultaneously with phosphorus, and the upper layer portion of the semiconductor region to which phosphorus and hydrogen are added is made amorphous. In addition, the acceleration voltage at this time is about 1 to 20 kV. However, it is preferable to adjust the doping conditions (acceleration voltage and the like) as appropriate so that a certain amount of crystallinity remains in the lower layer portion of the semiconductor layer. In addition, it is preferable to appropriately adjust the doping conditions (such as the pressure in the doping treatment chamber) so that more hydrogen is added than phosphorus.

  In the present invention, after the insulating film is etched before ion doping to expose a part of the semiconductor layer, ion doping may leave a certain amount of crystalline in the lower layer portion of the semiconductor layer. This is preferable because it is possible.

  Next, the resistance of the source region and the drain region is reduced by heat treatment at 150 to 300 ° C. (FIG. 1E) Hydrogen diffuses by this low-temperature heat treatment, and the resistance of the semiconductor region 107 to be a source region or a drain region is reduced. However, the region to which phosphorus is added remains in an amorphous state. At this heat treatment temperature (300 ° C. or lower), the crystallinity of the region made amorphous by doping is not recovered.

  Next, an interlayer insulating film 110 is formed, a contact hole reaching the source region or the drain region is formed, and then a source wiring 111 electrically connected to the source region and a drain wiring 112 electrically connected to the drain region are formed. .

  Next, hydrogenation is performed to improve TFT characteristics. As this hydrogenation, heat treatment in a hydrogen atmosphere or plasma hydrogenation at a low temperature is performed. Here, heat treatment is performed at 350 ° C. for one hour in a hydrogen atmosphere.

  Through the above manufacturing process, a top-gate TFT is completed on a plastic substrate at a process temperature of 350 ° C. or lower. Note that if plasma hydrogenation is performed at a low temperature by hydrogenation, a TFT is completed on a plastic substrate at a process temperature of 300 ° C. or lower.

  Although the source region or drain region of the TFT thus obtained has an amorphous state, its sheet resistance shows a very low value. The sheet resistance immediately after doping shows a value of 20 kΩ / □ or more, whereas the sheet resistance after heat treatment at a low temperature (250 ° C. to 350 ° C., 4 hours) shows a value of 10 kΩ / □ or less. Shows a very low value of 5 kΩ / □ or less.

  In addition, the following experiment was conducted.

First, an amorphous silicon film was formed on a substrate by a sputtering method, and laser treatment (XeCl laser, 30 Hz, 1 mm / sec) was performed, and phosphorus was added to the crystallized polysilicon film by an ion doping method. The sputtering conditions for the amorphous silicon film were a substrate temperature of 150 ° C., a deposition pressure of 0.4 Pa, a sputtering power of 3 kW, and an Ar flow rate of 50 sccm. Further, phosphine gas diluted with hydrogen is used, and the doping dose is 5 × 10 ¹⁵ / cm ² , 1 × 10 ¹⁶ / cm ² , 2 × 10 ¹⁶ / cm ² , 3 × 10 ¹⁶ / cm ^{2, respectively.} As shook conditions.

  Conditions were varied at 150 ° C., 250 ° C., 350 ° C., 450 ° C., and 550 ° C. (comparative example) on a substrate provided with a polysilicon film to which phosphorus was added at each dose. Moreover, the heat processing for 4 hours was performed at each temperature, and each electric resistance value, here, sheet resistance value was measured.

  7 shows the measurement result when the thickness of the polysilicon film is 50 nm, FIG. 8 shows the measurement result when the thickness of the polysilicon film is 70 nm, and FIG. 9 shows the measurement result when the thickness of the polysilicon film is 100 nm. It was shown to.

  As shown in the measurement results of FIG. 7, the resistance is greatly reduced after the heat treatment. When the heat treatment temperature is set to 150 ° C., the resistance of the semiconductor region to which the impurity is added is drastically reduced. When comparing before and after heat treatment, the sheet resistance after heat treatment was reduced to about half of that before heat treatment. This is considered to be due to the temperature at which hydrogen begins to freely diffuse in the film (equilibrium temperature of hydrogen glass (around 130 ° C.)). This diffusion of hydrogen occurs more easily as the dangling bond density is higher and the impurity element concentration (P concentration) is higher.

  For comparison, the resistance is also reduced in the comparative example in which the heat treatment at 550 ° C. is performed as in the conventional case, but the cause of the reduction is different from the present invention, and the doping is performed by the high temperature heat treatment at 550 ° C. This is thought to be because the crystallinity of the doped region which became amorphous due to the recovery was recovered and recrystallized.

FIG. 10 is a diagram showing a Raman scattering spectrum of a silicon film after doping a polysilicon film having a thickness of 50 nm with phosphorus. This doped silicon film can be regarded as the same as the source region or the drain region when a TFT is manufactured. In the range of wave numbers of 500 to 520 / cm- ¹ , it has a maximum value with respect to the scattering intensity. It is smaller than the maximum value of the source region or the drain region that is recrystallized by heat treatment at 550 ° C., and when heated at 450 ° C. or lower, it is almost amorphous. This shows that when a TFT is manufactured, the source region and the drain region are not recrystallized and remain mainly amorphous in heat treatment at 450 ° C. or lower. Thus, according to the present invention, the sheet resistance value can be lowered even when the source region and the drain region are amorphous.

In this specification, crystalline refers to a crystal structure having a very strong peak in the wave number range of 500 to 520 / cm- ¹ in the Raman scattering spectrum of a silicon film. On the other hand, “amorphous” refers to an amorphous state.

  In addition, when a time-dependent experiment was performed in the heat treatment at 150 ° C., it was found that the sheet resistance value greatly decreased in the initial stage (several minutes). From this experimental result, the time required for the heat treatment of the present invention (100 to 300 ° C., preferably 150 to 250 ° C.) may be about several minutes.

  Further, when the heat treatment in a nitrogen atmosphere and the heat treatment in a hydrogen atmosphere were compared, the sheet resistance value was lower in the hydrogen atmosphere. The sheet resistance of the sample subjected to heat treatment at 350 ° C. for 4 hours in a nitrogen atmosphere showed a value of 4834Ω / □, whereas the sheet sheet of the sample subjected to heat treatment for 4 hours at 350 ° C. in a hydrogen atmosphere The resistance was a very low value of 3626 Ω / □.

  Japanese Patent Application Laid-Open No. 6-104280 discloses a technique for injecting and activating protons simultaneously with addition of an impurity element by an ion doping method, but a region in which impurity elements and protons are added simultaneously with an ion doping process. Is finally crystallized into a polycrystalline state, which is different from the present invention. In the publication, the sheet resistance value is low immediately after doping, which is different from the present invention. In the present invention, the sheet resistance value immediately after doping is as high as about 20 kΩ / □. Further, this self-activation technique is not suitable for a plastic substrate because the semiconductor layer becomes very high temperature due to a high dose and a high acceleration voltage.

  Japanese Patent Application Laid-Open No. 8-181302 discloses a technique for forming a silicide simultaneously with the addition of impurity atoms by a doping method and reducing the resistance of the source region and the drain region. The region is crystallized into a polycrystalline state, which is different from the present invention. In this publication, the sheet resistance value is low immediately after doping, which is different from the present invention. In the present invention, the sheet resistance value immediately after doping is as high as about 20 kΩ / □. Further, since the silicide is formed, there is a concern that the TFT characteristics may be deteriorated due to the metal element forming the silicide.

  Further, unlike the conventional laser activation, the heat treatment at a low temperature (350 ° C. or lower) of the present invention can process a large amount of substrates at a time, so that the throughput is improved.

  In addition, the present invention is not limited to the structure shown in FIG. 1. If necessary, a lightly doped drain (LDD) structure having an LDD region between a channel formation region and a drain region (or source region) may be used. Good. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. Further, a so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film may be employed. Alternatively, a region or a layer containing a high concentration of hydrogen element may be formed in these LDD regions or GOLD regions.

  The present invention having the above-described configuration will be described in more detail with the following examples.

  The present invention is characterized in that the pixel portion and the drive circuit are all formed of n-channel TFTs by a low temperature process of 350 ° C. or lower. Therefore, in this embodiment, a manufacturing process for forming pixel TFTs on a plastic substrate will be described below.

  First, a plastic substrate 201 made of an organic material is prepared. In this embodiment, a substrate 201 made of polyimide is used. The heat resistant temperature of the polyimide substrate is about 399 ° C., and the color of the substrate itself is not transparent but brown. Next, a base insulating film 202 is formed over the substrate 201. The base insulating film is not particularly limited as long as it is a film forming method in which the process temperature does not exceed 300 ° C., and is formed by using a sputtering method here.

  Next, an amorphous semiconductor film is formed and crystallized by laser irradiation to form a crystalline semiconductor film. The amorphous semiconductor film is not particularly limited as long as the process temperature does not exceed 300 ° C., and is formed by sputtering here. Next, the semiconductor layer 203 is formed by patterning the crystalline semiconductor film into a desired shape. Next, a gate insulating film 204 that covers the semiconductor layer 203 is formed. The gate insulating film is not particularly limited as long as the process temperature does not exceed 300 ° C., and is formed by sputtering here. (Fig. 2 (A))

  Next, the gate electrode 205 is formed. (FIG. 2B) The gate electrode 205 is formed of an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. May be. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used.

Next, the gate insulating film is etched in a self-aligning manner using the gate electrode as a mask to form the gate insulating film 206, and an impurity element which imparts n-type to a part of the semiconductor layer after exposing a part of the semiconductor layer Here, phosphorus is added (doping)
Thus, the impurity region 207 is formed. (Fig. 2 (C))

  In this embodiment, the doping is performed after the gate insulating film is etched. However, after the gate electrode is formed, the doping may be performed through the gate insulating film. In this case, the impurity element passes through the gate insulating film and is doped in a self-aligned manner using the gate electrode as a mask.

  Next, heat treatment is performed at 150 ° C. to 350 ° C. for at least 2 minutes and a margin of 10 minutes or more, and the impurity region 208 having low sheet resistance is formed by the action of hydrogen contained in the semiconductor layer. (Fig. 2 (D))

  Next, an interlayer insulating film 210 is formed, a contact hole reaching the source region or the drain region is formed, a source wiring 211 electrically connected to the source region, and a pixel electrode 212 electrically connected to the drain region are formed. .

  Next, hydrogenation is performed to improve TFT characteristics. As this hydrogenation, heat treatment in a hydrogen atmosphere (350 ° C., 1 hour) or plasma hydrogenation is performed at a low temperature.

  Through the above manufacturing process, a top-gate TFT is completed on a plastic substrate at a process temperature of 400 ° C. or lower. (FIG. 2 (E)) Although the source region and drain region of the TFT completed according to the present embodiment were mainly amorphous, the sheet resistance value was as low as about 5 kΩ. If necessary, a passivation film made of an inorganic insulating film may be formed.

The electrical characteristics of the TFT (single gate structure) completed according to this example showed good values. FIG. 18 shows the TFT characteristics (VI characteristics). Further, the threshold value (Vth) indicating the voltage value at the rising point in the VI characteristic graph is 2.33V. In addition, S value is 0.357 (V / dec), mobility (μ _FE )
Is as excellent as 128.8 (cm ² / Vs).

  After completing the TFT, a reflective liquid crystal display device is completed through steps such as formation of an alignment film 216a, rubbing treatment, bonding of the counter substrate 214 provided with the alignment film 216b and the counter electrode 215, and injection of liquid crystal 213.

Here, as the pixel electrode 212, a reflective metal material, for example, a material mainly containing Al, Ag, or the like is used. In this embodiment, an example of a reflective liquid crystal display device is shown. However, a transparent conductive film such as ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), If zinc oxide (ZnO) or the like is used, a transmissive liquid crystal display device can be formed.

  A basic logic circuit such as a NAND circuit or a NOR circuit is configured by using the N-channel TFT shown in this embodiment, and a more complex logic circuit (signal division circuit, operational amplifier, γ correction circuit, etc.) is also configured. Can do.

  Note that the TFT shown in this embodiment is enhanced by adding an element belonging to Group 15 of the periodic table (preferably phosphorus) or an element belonging to Group 13 of the periodic table (preferably boron) to the semiconductor to be a channel formation region. A mold and a depletion mold can be created separately.

When an NMOS circuit is formed by combining N-channel TFTs, an enhancement type TFT is formed (hereinafter referred to as an EEMOS circuit), or an enhancement type and a depression type are combined (hereinafter referred to as an EDMOS circuit). Called). By combining these circuits, the driving circuit of the liquid crystal display device can all be constituted by N-channel TFTs.

  In this embodiment, an example in which the resistance of the impurity region is reduced simultaneously with the heat treatment by hydrogenation is shown in FIG. Since the processes up to the doping process are the same as those in the first embodiment, detailed description thereof is omitted.

  First, in accordance with Embodiment 1, a base insulating film 302, a semiconductor layer 303, and a gate insulating film 304 are formed over a substrate 301. (FIG. 3A) Next, a gate electrode 305 is formed as in the first embodiment. (FIG. 3B). Next, in the same manner as in Example 1, etching is performed to form the gate insulating film 306. (FIG. 3C).

  Next, as in Example 1, an impurity region is formed by adding an impurity element in a self-aligning manner using the gate electrode 305 as a mask. (Fig. 3 (D))

  Next, the interlayer insulating film 310 is formed without performing heat treatment, a contact hole reaching the source region or the drain region is formed, and then the source wiring 311 that is electrically connected to the source region and the drain that is electrically connected to the drain region An electrode 312 is formed.

  Next, hydrogenation is performed to improve TFT characteristics. As this hydrogenation, heat treatment (350 ° C., 1 to 4 hours) in a hydrogen atmosphere is performed. Simultaneously with this hydrogenation, the resistance of the source and drain regions is also reduced. Although the source region and drain region of the TFT completed in accordance with this example (heat treatment at 350 ° C. for 4 hours in a hydrogen atmosphere) are mainly amorphous, the sheet resistance value is about 3.6 kΩ, which is a very low value. It became.

  Thus, since the resistance of the source region and the drain region can be reduced by the heat treatment at a low temperature, the heat treatment step performed only for the activation is omitted, and the source region and the drain region are reduced at the same time as the hydrogenation. It was possible to make it resistant.

  Note that although an example in which the resistance of the source region and the drain region is reduced simultaneously with hydrogenation is shown in this embodiment, there is no particular limitation, and among the steps after the doping step, 100 to 300 ° C., preferably 150 to It can be performed at the same time as a process in which a heat treatment at 250 ° C. is applied (for example, formation of an interlayer insulating film, formation of a passivation film, etc.).

  In the first embodiment, a TFT having a top gate structure (specifically, a planar type TFT) is exemplified as the TFT. However, the present invention is not limited to the TFT structure, and can be applied to a TFT having a bottom gate structure.

  In this embodiment, an example in which an inverted stagger TFT is typically shown is shown in FIG.

  First, a plastic substrate 400 made of an organic material is prepared. Note that a base insulating film 401 is provided for preventing the diffusion of impurities from the substrate and improving the electrical characteristics of the TFT. As a material for the base insulating film, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOx Ny), or a laminated film thereof can be used in a film thickness range of 100 to 500 nm. A formation method such as a thermal CVD method, a plasma CVD method, a vapor deposition method, a sputtering method, or a low pressure thermal CVD method can be used.

Next, a gate wiring (including a gate electrode) 402 having a single layer structure or a stacked structure is formed. After forming a conductive film having a film thickness of 10 to 1000 nm, preferably 30 to 300 nm, using a thermal CVD method, a plasma CVD method, a low pressure thermal CVD method, a vapor deposition method, a sputtering method, or the like as a means for forming the gate wiring 402. Then, it is formed by a known patterning technique. In addition, as a material of the gate wiring 402, a material containing a conductive material or a semiconductor material as a main component, for example, Ta (tantalum), Mo (molybdenum)
, High melting point metal materials such as Ti (titanium), W (tungsten), chromium (Cr), silicide, which is a compound of these metal materials and silicon, materials such as polysilicon having N-type or P-type conductivity, Any structure having at least one material layer mainly composed of a low-resistance metal material Cu (copper), Al (aluminum) or the like can be used without particular limitation.

  Next, a gate insulating film is formed. As the gate insulating film, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOx Ny), an organic resin film (BCB (benzocyclobutene) film), or a laminated film of these is a film thickness range of 100 to 400 nm. Can be used. As a means for forming the base film, a formation method such as a thermal CVD method, a plasma CVD method, a low pressure thermal CVD method, a vapor deposition method, a sputtering method, or a coating method can be used. Here, as shown in FIG. 4A, stacked gate insulating films 403a and 403b are used. As the lower gate insulating film 403a, a silicon nitride film or the like that effectively prevents diffusion of impurities from the substrate and the gate wiring is formed in a film thickness range of 10 nm to 60 nm.

  Next, an amorphous semiconductor film is formed. As the amorphous semiconductor film 404, an amorphous silicon film containing silicon as a main component can be used in a thickness range of 20 to 100 nm, more preferably 20 to 60 nm. As a method for forming the amorphous semiconductor film, a formation method such as a thermal CVD method, a plasma CVD method, a low pressure thermal CVD method, a vapor deposition method, or a sputtering method can be used.

  Note that if the gate insulating films 403a and 403b and the amorphous semiconductor film are continuously formed without being exposed to the atmosphere, impurities are not mixed into the interface between the gate insulating film and the amorphous semiconductor film, so that favorable interface characteristics are obtained. Can be obtained.

  Next, the amorphous semiconductor film is crystallized to form a crystalline semiconductor film, and then the obtained crystalline semiconductor film is patterned into a desired shape. Note that the order of steps for patterning the semiconductor film is not particularly limited, and may be performed, for example, after adding an impurity element. As the crystallization treatment, a crystallization method by laser light irradiation may be used. Also, if the native oxide film on the surface of the amorphous semiconductor film is removed with a hydrofluoric acid-based etchant such as buffer hydrofluoric acid immediately before the crystallization treatment, the silicon bonds near the surface are terminated with hydrogen and bonded to impurities. This is preferable because a good crystalline semiconductor film can be formed.

  Next, an insulating layer 405 is formed over the crystalline semiconductor layer 404. This insulating layer 405 protects the channel formation region during the impurity element addition step. As the insulating layer 405, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOx Ny), an organic resin film (BCB film), or a laminated film thereof is used in a film thickness range of 100 to 400 nm. it can. The insulating layer 405 is formed using a known patterning technique such as normal exposure or back exposure. (Fig. 4 (B))

Next, a doping step of adding an impurity element imparting n-type conductivity to the crystalline semiconductor film is performed using the insulating layer 405 as a mask, so that an impurity region 406 is formed. (FIG. 4C) As an impurity element imparting n-type conductivity to a semiconductor material, an impurity element belonging to Group 15, for example, P, As, Sb, N, Bi, or the like can be used.
In this step, doping conditions (dose amount, acceleration voltage, etc.) are appropriately set by plasma doping, and P (phosphorus) is added to the crystalline semiconductor film whose surface is exposed. An ion implantation method can also be used as another doping method. The impurity region 406 is a high-concentration impurity region and becomes a later source / drain region.

  Next, heat treatment (150 to 350 ° C., 1 hour or longer) is performed, so that an impurity region 407 with low sheet resistance is formed by the action of hydrogen contained in the semiconductor layer. Although the source region and drain region of the TFT completed according to this example were mainly amorphous, the sheet resistance value was as low as about 5 kΩ.

  Next, an interlayer insulating film 408 is formed on the entire surface. As the interlayer insulating film 408, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film (such as a polyimide film or a BCB film), or a stacked film thereof can be used.

  Next, after forming a contact hole using a known technique, wirings 409 and 410 are formed to obtain the state shown in FIG. The wirings 409 and 410 function as source wirings or drain wirings. Finally, heat treatment is performed in a hydrogen atmosphere, and the whole is hydrogenated to complete an N-channel TFT.

  In the present embodiment, an example in which the patterning of the active layer is performed before the formation of the insulating layer 405 is shown, but there is no particular limitation. For example, the patterning may be performed before the crystallization step, before doping, or after the heat treatment. Good.

  In the present embodiment, a step of adding a small amount of an impurity element to the channel formation region and controlling the threshold value of the TFT (also referred to as a channel doping step) may be added.

  This embodiment can be combined with the second embodiment.

  An example of manufacturing a liquid crystal display panel using the active matrix substrate obtained by any one of Embodiments 1 to 3 will be described below.

  The top view shown in FIG. 5 includes a pixel portion, a driving circuit, an external input terminal to which an FPC (Flexible Printed Circuit Board: Flexible Printed Circuit) is pasted, wiring 81 for connecting the external input terminal to the input portion of each circuit, and the like. The active matrix substrate and the counter substrate 82 provided with a color filter or the like are bonded to each other with a sealant 83 interposed therebetween.

  A light shielding layer 86 a is provided on the counter substrate side so as to overlap with the gate side driving circuit 84, and a light shielding layer 86 b is formed on the counter substrate side so as to overlap with the source side driving circuit 85. Further, the color filter 88 provided on the counter substrate side on the pixel portion 87 is provided with a light shielding layer and colored layers of red (R), green (G), and blue (B) corresponding to each pixel. It has been. When actually displaying, a color display is formed with three colors of a red (R) colored layer, a green (G) colored layer, and a blue (B) colored layer. It shall be arbitrary.

  Here, the color filter 88 is provided on the counter substrate for colorization. However, the present invention is not particularly limited, and the color filter may be formed on the active matrix substrate when the active matrix substrate is manufactured.

  In addition, a light-shielding layer is provided between adjacent pixels in the color filter to shield light other than the display area. Here, the light shielding layers 86a and 86b are also provided in the region covering the drive circuit. However, the region covering the drive circuit is covered with a cover when the liquid crystal display device is incorporated later as a display portion of an electronic device. It is good also as a structure which does not provide a light shielding layer. Further, when the active matrix substrate is manufactured, a light shielding layer may be formed on the active matrix substrate.

  Further, without providing the light-shielding layer, the light-shielding layer is appropriately disposed between the counter substrate and the counter electrode so as to be shielded from light by stacking a plurality of colored layers constituting the color filter. Or the drive circuit may be shielded from light.

  An FPC 89 made of a base film and wiring is bonded to the external input terminal with an anisotropic conductive resin. Furthermore, the mechanical strength is increased by the reinforcing plate.

  The liquid crystal display device manufactured as described above can be used as a display portion of various electronic devices.

  FIG. 6 shows a block diagram of the liquid crystal display device. FIG. 6 shows a circuit configuration for performing analog driving. In this embodiment, a source side driver circuit 90, a pixel portion 91, and a gate side driver circuit 92 are provided. Note that in this specification, the drive circuit is a generic name including a source side processing circuit and a gate side drive circuit.

  The source side driver circuit 90 includes a shift register 90a, a buffer 90b, and a sampling circuit (transfer gate) 90c. The gate side driving circuit 92 includes a shift register 92a, a level shifter 92b, and a buffer 92c. Note that the shift registers shown in FIG. 16 may be used as the shift registers 90a and 92a. Further, if necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.

In this embodiment, the pixel portion 91 includes a plurality of pixels, and each of the plurality of pixels is provided with a TFT element.

  The source side driver circuit 90 and the gate side driver circuit 92 are all formed of N-channel TFTs, and all the circuits are formed with the EEMOS circuit shown in FIG. 15A as a basic unit. However, the power consumption is slightly increased as compared with the conventional CMOS circuit.

  Although not shown, a gate side drive circuit may be further provided on the opposite side of the gate side drive circuit 92 with the pixel portion 91 interposed therebetween.

  This embodiment can be freely combined with any one of Embodiments 1 to 3.

In this embodiment, a pixel structure is shown in FIG. 11, and a cross-sectional structure is shown in FIG. A-A 'sectional view and B-B' sectional view are shown, respectively.

  In this embodiment, the storage capacitor is formed of the second semiconductor layer 1002 and the capacitor electrode 1005 using the insulating film on the second semiconductor layer 1002 as a dielectric. Note that the capacitor electrode 1005 is connected to the capacitor wiring 1009. The capacitor electrode 1005 is formed over the same insulating film as the first electrode 1004 and the source wiring 1006 at the same time. The capacitor wiring is simultaneously formed over the same insulating film as the pixel electrode 1011, the connection electrode 1010, and the gate wiring 1007.

  In this embodiment, an impurity element imparting n-type is added to the impurity regions 1012 to 1014. Reference numeral 1012 denotes a source region, and 1013 denotes a drain region.

  Further, although an example in which the gate electrode and the source wiring are formed at the same time has been described in this embodiment, the number of masks may be increased by one, and the gate electrode, the first electrode, and the capacitor wiring may be formed in another process. That is, first, only a portion that overlaps with a semiconductor layer and becomes a gate electrode is formed, an n-type impurity element is added, heat treatment is performed at a low temperature, and then a first electrode is formed so as to overlap with the gate electrode. At this time, the contact between the gate electrode and the first electrode is formed by simple superposition without forming a contact hole. In addition, a source wiring and a capacitor wiring are formed simultaneously with the first electrode. This makes it possible to use low resistance aluminum or copper as a material for the first electrode and the source wiring. Further, an n-type impurity element can be added to the semiconductor layer overlapping the capacitor wiring to increase the storage capacitor.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 4.

The n-channel TFT shown in Example 1 is obtained by adding an element belonging to Group 15 of the periodic table (preferably phosphorus) or an element belonging to Group 13 of the periodic table (preferably boron) to the semiconductor serving as a channel formation region. The enhancement type and the depression type can be created separately.

  When an NMOS circuit is formed by combining n-channel TFTs, an enhancement type TFT is formed (hereinafter referred to as an EEMOS circuit), or an enhancement type and a depression type are combined (hereinafter referred to as an EDMOS circuit). Called).

Here, FIG. 13A shows an example of an EEMOS circuit, and FIG. 13B shows an example of an EDMOS circuit. In FIG. 13A, reference numerals 31 and 32 denote enhancement-type n-channel TFTs (hereinafter referred to as E-type NTFTs). FIG. 13B
, 33 is an E-type NTFT, and 34 is a depletion-type n-channel TFT (hereinafter referred to as a D-type NTFT).

  13A and 13B, VDH is a power supply line to which a positive voltage is applied (positive power supply line), and VDL is a power supply line to which a negative voltage is applied (negative power supply line). . The negative power source line may be a ground potential power source line (ground power source line).

  Further, FIG. 14 shows an example of manufacturing a shift register using the EEMOS circuit shown in FIG. 13A or the EDMOS circuit shown in FIG. In FIG. 14, 40 and 41 are flip-flop circuits. Reference numerals 42 and 43 denote E-type NTFTs. A clock signal (CL) is input to the gate of the E-type NTFT 42, and a clock signal (CL bar) having an inverted polarity is input to the gate of the E-type NTFT 43. Reference numeral 44 denotes an inverter circuit. As shown in FIG. 14B, the EEMOS circuit shown in FIG. 13A or the EDMOS circuit shown in FIG. 13B is used. Therefore, it is also possible to configure all the drive circuits of the display device with n-channel TFTs.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 5.

In this example, an example in which an EL (electroluminescence) display device is manufactured using the TFT obtained in Example 1 or Example 3 will be described below with reference to FIGS. Note that this embodiment is an example of an EL display device in which all TFTs used for the pixel portion and the driver circuit are N-channel TFTs.

  FIG. 15 shows an example of a light-emitting device having a pixel portion and a driving circuit for driving the pixel portion on the same insulator (but a state before sealing). Note that a CMOS circuit serving as a basic unit is shown in the driver circuit, and one pixel is shown in the pixel portion.

  In FIG. 15, reference numeral 1501 denotes a plastic substrate. First, a base insulating film is formed on the plastic substrate 1501 according to the embodiment.

  On the base insulating film, a driving circuit including an N-channel TFT 1504 and an N-channel TFT 1505, a switching TFT 1506 including an N-channel TFT, and a current control TFT 1507 including an N-channel TFT are formed. Note that description of the N-channel TFT is omitted because it is only necessary to refer to the first embodiment. In this embodiment, all TFTs are formed by top gate type TFTs.

The switching TFT has a structure having two channel formation regions between a source region and a drain region (double gate structure). However, the switching TFT is not particularly limited, and a single channel formation region is formed. A gate structure or a triple gate structure in which three are formed may be used.

In addition, a contact hole is provided in the first interlayer insulating film before the second interlayer insulating film is provided on the drain region of the current control TFT. This is to simplify the etching process when forming a contact hole in the second interlayer insulating film.
A contact hole is formed in the second interlayer insulating film so as to reach the drain region, and a pixel electrode connected to the drain region is provided. The pixel electrode is an electrode that functions as a cathode of the EL element, and is formed using a conductive film containing an element belonging to Group 1 or Group 2 of the periodic table. In this embodiment, a conductive film made of a compound of lithium and aluminum is used.

Further, an insulating film provided so as to cover the end portion of the pixel electrode is referred to as a bank in this specification. The bank may be formed of an insulating film containing silicon or a resin film. When a resin film is used, carbon particles or metal particles are added so that the specific resistance of the resin film is 1 × 10 ⁶ to 1 × 10 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm). Insulation breakdown during filming can be suppressed.

  The EL element 1505 includes a pixel electrode (cathode), an EL layer, and an anode. As the anode, a conductive film having a large work function, typically an oxide conductive film is used. As the oxide conductive film, indium oxide, tin oxide, zinc oxide, or a compound thereof may be used.

Note that in this specification, a stacked body in which a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, or an electron blocking layer is combined with the light-emitting layer is defined as an EL layer.

Although not shown here, it is effective to provide a passivation film so as to completely cover the EL element 1505 after the anode is formed. As the passivation film, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a combination thereof.

  In the subsequent steps, the light emitting device may be completed according to a known technique.

  Further, by forming the gate side driver circuit and the source side driver circuit with only the N-channel TFT, the pixel portion and the driver circuit can all be formed with the N-channel TFT. Accordingly, the yield and throughput of the TFT process can be significantly improved in manufacturing an active matrix electro-optical device, and the manufacturing cost can be reduced.

  Note that this embodiment can also be implemented when one of the source side driver circuit and the gate side driver circuit is an external IC chip.

  In this embodiment, the drive circuit is configured using only the E-type NTFT, but it may be formed by combining the E-type NTFT and the D-type NTFT.

  Further, in this embodiment, an example in which light is emitted upward is shown, but a structure in which light is emitted downward may be formed by appropriately changing the configuration of the EL element.

  Note that this embodiment can be freely combined with Embodiment 1, Embodiment 2, or Embodiment 6. In this embodiment, a top gate type TFT is used, but there is no particular limitation, and an inverted stagger type TFT as shown in Embodiment 3 can also be used.

  The driving circuit and the pixel portion formed by implementing the present invention can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated in the display unit.

Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) and the like. . Examples of these are shown in FIGS.

FIG. 16A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other driving circuits.

FIG. 16B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be applied to the display portion 2102 and other driver circuits.

FIG. 16C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like. The present invention can be applied to the display portion 2205 and other driving circuits.

FIG. 16D illustrates a goggle type display including a main body 2301, a display portion 2302, an arm portion 2303, and the like. The present invention can be applied to the display portion 2302 and other driving circuits.

FIG. 16E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other driving circuits.

FIG. 16F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, an operation switch 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502 and other driving circuits.

  FIG. 17A illustrates a mobile phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, and the like. The present invention can be applied to the display portion 2904 and other driving circuits.

  FIG. 17B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003 and other driving circuits.

  FIG. 17C illustrates a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-7.

Claims (4)

Forming a gate insulating film over the semiconductor layer having a crystal structure;
Forming a gate electrode on the gate insulating film and at a position overlapping with the first region of the semiconductor layer;
By simultaneously adding an impurity element imparting n-type conductivity and hydrogen to the second region and the third region of the semiconductor layer, the upper layer portion of the second region and the upper layer portion of the third region are amorphous. And a step of leaving crystalline in the lower layer portion of the second region and the lower layer portion of the third region,
Diffusing the hydrogen in the second region and the third region by performing a heat treatment at a temperature of 100 to 300 ° C., and
The method for manufacturing an EL display device, wherein the first region is disposed between the second region and the third region. Forming a gate insulating film over the semiconductor layer having a crystal structure;
Forming a gate electrode on the gate insulating film and at a position overlapping with the first region of the semiconductor layer;
By simultaneously adding an impurity element imparting n-type conductivity and hydrogen to the second region and the third region of the semiconductor layer, the upper layer portion of the second region and the upper layer portion of the third region are amorphous. And a step of leaving crystalline in the lower layer portion of the second region and the lower layer portion of the third region,
Diffusing the hydrogen in the second region and the third region by performing a heat treatment at a temperature of 100 to 300 ° C .;
Forming an interlayer insulating film on the gate electrode;
Forming an EL element electrically connected to one of the second region or the third region on the interlayer insulating film,
The method for manufacturing an EL display device, wherein the first region is disposed between the second region and the third region. Forming a gate insulating film over the semiconductor layer having a crystal structure;
Forming a gate electrode on the gate insulating film and at a position overlapping with the first region of the semiconductor layer;
By simultaneously adding an impurity element imparting n-type conductivity and hydrogen to the second region and the third region of the semiconductor layer, the upper layer portion of the second region and the upper layer portion of the third region are amorphous. And a step of leaving crystalline in the lower layer portion of the second region and the lower layer portion of the third region,
Diffusing the hydrogen in the second region and the third region by forming an interlayer insulating film on the gate electrode at a temperature of 100 to 300 ° C., and
The method for manufacturing an EL display device, wherein the first region is disposed between the second region and the third region. Forming a gate insulating film over the semiconductor layer having a crystal structure;
Forming a gate electrode on the gate insulating film and at a position overlapping with the first region of the semiconductor layer;
By simultaneously adding an impurity element imparting n-type conductivity and hydrogen to the second region and the third region of the semiconductor layer, the upper layer portion of the second region and the upper layer portion of the third region are amorphous. And a step of leaving crystalline in the lower layer portion of the second region and the lower layer portion of the third region,
Diffusing the hydrogen in the second region and the third region by forming an interlayer insulating film on the gate electrode at a temperature of 100 to 300 ° C .;
Forming an EL element electrically connected to one of the second region or the third region on the interlayer insulating film,
The method for manufacturing an EL display device, wherein the first region is disposed between the second region and the third region.

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