JP5031705B2 - DC offset removal circuit and receiver - Google Patents

Description

  The present invention relates to a DC offset removal circuit often used in a zero-IF or low-IF radio receiver.

  Zero-IF or low-IF architecture that eliminates the need for external components is effective for integration of wireless receivers, particularly integration in a CMOS process that is expected to reduce costs.

  FIG. 15 is a block diagram illustrating a configuration example of a radio receiver of a general zero-IF architecture. The radio receiver 200 includes an antenna 210, a variable gain amplification circuit (RF-VGA, Radio Frequency-Variable Gain Amplifier) 220, a frequency synthesizer (Frequency Synthesizer) 230, an I channel signal path 240, a Q channel signal path 250, and a DSP demodulation circuit. (Digital signal processing block) 260 is provided.

  A radio signal output from the antenna 210 is amplified by the RF-VGA 220 and output to the I channel signal path 240 and the Q channel signal path 250. Further, the frequency synthesizer 230 generates a local signal corresponding to the radio signal frequency to be received and outputs the local signal to the I channel signal path 240 and the Q channel signal path 250. The I channel signal path 240 and the Q channel signal path 250 convert the output of the RF-VGA 220 to near zero frequency, perform amplification and filtering, and output a digital signal to the DSP demodulation circuit 260. The DSP demodulation circuit 260 processes the digital signal and performs demodulation.

  The I channel signal path 240 includes a mixer 241, a signal processing circuit 242, an AD conversion circuit 243, and a DC offset removal circuit (DCOC) 244. The signal processing circuit 242 includes an LPF (Low Pass Filter) 242a and a variable gain amplification. Circuit (IF-VGA, Intermediate Frequency-Variable Gain Amplifier) 242b. Similarly, the Q channel signal path 250 includes a mixer 251, a signal processing circuit 252, an AD conversion circuit 253, and a DC offset removal circuit 254. The signal processing circuit 252 includes an LPF 252a and an IF-VGA 252b.

  The mixers 241 and 251 mix the local signal from the frequency synthesizer 230 with the output from the RF-VGA 220. The LPFs 242a and 252a filter the output signals from the mixers 241 and 251 and the IF-VGAs 242b and 252b amplify the outputs of the LPFs 242a and 252a. Outputs from the IF-VGAs 242b and 252b are converted into digital values by the AD conversion circuits 243 and 253, respectively.

  Since the LPFs 242a and 252a can perform a filtering process for attenuating signals other than the reception channel at a low frequency, it is possible to integrate steep filters and reduce external components. On the other hand, since the mixers 241 and 251, LPFs 242 a and 252 a, and IF-VGA 242 b and 252 b are composed of analog circuits, unnecessary signals due to DC offset and second-order distortion of these circuits are generated near zero frequency, and I channel signals There is a possibility of saturating the circuits of the path 240 and the Q channel signal path 250. The DC offset removal circuits 244 and 254 are circuits that are essential for removing unnecessary signals and DC offsets near these DCs.

  FIG. 16 is a circuit diagram showing a configuration of a DC offset removal circuit 300 and an analog signal processing circuit (ASPC, Analog Signal Processing Circuit) 310 described in Non-Patent Document 1. The DC offset removal circuit 300 is integrated as an LSI, and includes a transconductance stage 301, a capacitor 302, a buffer circuit 303, and a subtraction circuit 304.

  Transconductance stage 301 converts the output voltage of ASPC 310 into a current. The output current of the transconductance stage 301 is integrated by the capacitor 302, and the buffer circuit 303 converts the output voltage of the capacitor 302 into the output signal X_DC and feeds it back to the subtraction circuit 304. The subtraction circuit 304 subtracts the output signal X_DC of the buffer circuit 303 from the input signal X, and outputs a signal Y from which the DC offset is removed. The signal Y is processed by the ASPC 310 and output as a signal Z.

  As described above, the entire DC offset removal circuit 300 can be configured with an analog circuit.

  FIG. 17 is a circuit diagram showing a configuration of a DC offset removal circuit 400 and a signal processing circuit 410 described in Patent Document 1. The DC offset removal circuit 400 includes a digital integration circuit 401, a gain stage 402, a noise shaping circuit 403, and a subtractor 404. The signal processing circuit 410 includes a low-pass filter and a multiplier, processes the input signal Y, and outputs a digital output signal Z.

  The output signal Z is integrated by the digital integration circuit 401, and the output signal of the digital integration circuit 401 is amplified or attenuated by the gain stage 402. The noise shaping circuit 403 performs noise shaping on the output of the gain stage and feeds back the offset signal X_DC to the subtractor 404. The subtractor 404 removes the offset signal X_DC from the digital input signal X and outputs a signal Y to the signal processing circuit 410.

With this configuration, the DC offset included in the digital input signal X is removed, and after the signal processing circuit 410 performs desired signal processing, it is output as the output signal Z. Patent Document 1 shows that the use of a noise shaping circuit for the feedback system can reduce the circuit scale.
H. Kawamura, T. Fujiwara, et. Al., “A 184mW Fully Integrated DVB-H Tuner Chip with Distortion Compensated Variable Gain LNA,” 2006 Symposium on VLSI Circuits Digest of Technical Papers. US Pat. No. 6,324,231 (registered on November 27, 2001)

  In the configuration of Non-Patent Document 1 shown in FIG. 16, the input / output characteristics from the signal X to the signal Z indicate the characteristics of a first-order high-pass filter (HPF) near the zero frequency. Usually, the cut-off frequency of the HPF is set to a low value of 100 Hz to 1 kHz. When the ASPC 310 is an amplifier circuit having a gain G, the capacitance of the capacitor 302 is Cext, and the transconductance of the transconductance stage 301 is Gm, the cutoff frequency fc and the input / output characteristic Z / X are respectively expressed by the following formulas (1 ) And formula (2).

  Usually, since the maximum value of the gain G is as large as about 30 dB, it is necessary to reduce the transconductance Gm value in order to reduce the cut-off frequency fc to about 500 Hz. When the transconductance Gm value is 1 mS, the value of the capacitance Cext is as large as 10 uF, and the DC offset removal circuit 300 cannot be integrated. At this time, many terminals are required to connect the external capacitor to the LSI internal circuit. Further, even when an external capacitor is used, since the capacitance is large, a large size capacitor is required, and the size and height of the module on which the LSI is mounted cannot be reduced.

  Furthermore, when realizing a small transconductance, it is necessary to reduce the size of the transistors constituting the transconductance stage 301. Therefore, the input equivalent offset voltage of the transconductance stage 301 is increased, and the offset voltage appears at the output Z, so that the DC offset removal performance is deteriorated. Further, in the configuration in which the DC offset removal circuit 300 shown in FIG. 16 is applied to the DC offset removal circuits 244 and 254 shown in FIG. 15, the offset generated from the ADC cannot be removed, and a large residual DC offset remains in the ADC output. .

  As described above, in the configuration of Non-Patent Document 1 shown in FIG. 16, a capacitor having a large capacity is required to realize a high-pass filter having a low cutoff frequency, and an analog circuit that realizes a DC offset removal circuit. Depending on the performance, there is a problem that the DC offset removal performance also deteriorates.

  In the configuration of Patent Document 1 shown in FIG. 17, the output signal Z of the signal processing circuit 410 is a digital signal. However, in the radio receiver 200 shown in FIG. 15, since the signal processing circuit 242 is an analog signal processing circuit, the signal from which the DC offset is to be removed is the output signal of the AD converters 243 and 253 from the output of the mixers 241 and 251. Except for the AD converters 243 and 253, all analog signal processing is required. Therefore, the DC offset removal circuit 400 of Patent Document 1 shown in FIG. 17 causes a problem that it cannot be applied as it is to the radio receiver 200 shown in FIG.

  The present invention has been made in view of the above problems, and an object of the present invention is to realize a DC offset removal circuit that can be applied to an analog signal processing circuit and that can remove a DC offset component with a small circuit scale and high accuracy. There is.

In order to solve the above problems, a DC offset removal circuit according to the present invention is a DC offset removal circuit that removes a DC offset component mixed in a digital output signal of a signal processing circuit that performs signal processing on an analog input signal. A first quantization circuit for quantizing the digital output signal, a digital integration circuit for integrating the output signal of the first quantization circuit, and a first noise shaping for shaping the output signal of the digital integration circuit circuit and, above the DA converter circuit for the output signal of the first noise shaping circuit for converting an analog signal, the output signal of the DA converter circuit and a feedback circuit for feeding back to said analog input signal, said first quantizing circuit as characterized by a second noise shaping circuit to perform noise shaping That.

  According to the above-described configuration, unlike the conventional DC offset removal circuit using an analog circuit, the integration circuit can be configured by a digital circuit, so that a capacitor having a large capacity is not required for the integration circuit. Compared to analog integrators, digital integrators can easily realize high-precision integrators by increasing the number of bits, so that it is easy to improve DC offset removal performance, so that the circuit scale can be reduced and high DC offset can be removed with high accuracy. Further, the present invention can be applied to an analog signal processing circuit, and has an effect of realizing a DC offset removal circuit that can remove a DC offset component with a small circuit scale and high accuracy. Furthermore, since the number of output bits of the first noise shaping circuit can be set low without degrading the resolution near DC, the resolution of the DA converter circuit can be kept low, and the circuit area of the DA converter circuit can be reduced. At the same time, the design of the DA converter circuit becomes easy.

  In the DC offset removal circuit according to the present invention, it is preferable that the number of bits of the output signal of the first quantization circuit is smaller than the number of bits of the digital output signal.

  According to the above configuration, the number of bits of the signal is reduced in the first quantization circuit, so that the circuit scale and power consumption of the digital integration circuit and the like provided after the first quantization circuit can be reduced.

  In the DC offset removal circuit according to the present invention, it is preferable that a low-pass filter is provided between the DA conversion circuit and the feedback circuit.

  According to the above configuration, since the quantization noise shaped by the first noise shaping circuit can be filtered and fed back to the input analog signal, noise and spurious due to the shaping operation can be reduced.

  In the DC offset removal circuit according to the present invention, the feedback circuit is preferably a subtraction circuit that subtracts the output signal of the DA converter circuit from the analog input signal.

  A DC offset removal circuit according to the present invention is a DC offset removal circuit that removes a DC offset component mixed in a digital output signal of a signal processing circuit that performs signal processing on an analog input signal, and the digital output signal is quantized. A first quantization circuit for integrating the output signal, a digital integration circuit for integrating the output signal of the first quantization circuit, a second quantization circuit for quantizing the output signal of the digital integration circuit, and the second quantum circuit A first noise shaping circuit that shapes a difference between an input signal and an output signal of the quantization circuit, a first DA conversion circuit that converts an output signal of the second quantization circuit into an analog signal, and an output of the first noise shaping circuit A second DA converter circuit for converting a signal into an analog signal, an output signal of the first DA converter circuit, and an output signal of the second DA converter circuit; It is characterized in that it comprises a feedback circuit for feeding back to the analog input signal.

  According to the above configuration, it is possible to realize a DC offset removing circuit that can not only remove a DC offset component with a small circuit scale and high accuracy, but can further reduce noise and reduce a circuit area.

  In the DC offset removal circuit according to the present invention, it is preferable that a low-pass filter is provided between the second DA conversion circuit and the feedback circuit.

  According to the above configuration, since the quantization noise shaped by the first noise shaping circuit can be filtered and fed back to the input analog signal, noise and spurious due to the shaping operation can be reduced.

  In the DC offset removal circuit according to the present invention, the feedback circuit adds an output signal of the first DA converter circuit and an output signal of the second DA converter circuit, and outputs the output signal of the adder circuit to the analog input. And a subtracter for subtracting from the signal.

  In the DC offset removal circuit according to the present invention, the second DA converter circuit preferably has 2 to 5 output levels.

  According to the above configuration, the DA converter circuit is simpler when the number of bits is smaller, so the circuit scale of the second DA converter circuit can be reduced.

  In the DC offset removal circuit according to the present invention, the second DA conversion circuit preferably includes a plurality of 1-bit DA conversion circuits having the same size, and the 1-bit DA conversion circuits are preferably connected in parallel to each other.

  According to said structure, the glitch, spurious, etc. resulting from the switching operation | movement of the 2nd DA converter circuit which operate | moves at high speed can be reduced.

  In the DC offset removal circuit according to the present invention, the second DA conversion circuit includes a current steering type DA conversion circuit that converts an input digital signal into a current, a first MOS transistor that converts the current into a voltage, and the first MOS. And a second MOS transistor that forms a current mirror circuit together with the transistor and converts the voltage into an output current of the second DA converter circuit, and the low-pass filter includes a gate of the first MOS transistor and a gate of the second MOS transistor. It is preferable to be provided in between.

  According to said structure, a 2nd DA converter circuit and a low-pass filter can be mounted easily and compactly.

  In the DC offset removal circuit according to the present invention, it is preferable that the order of the first noise shaping circuit is the first order.

  According to said structure, the circuit scale of a 1st noise shaping circuit can be made small. Further, sufficient DC offset removal performance can be obtained by the primary shaping.

  In the DC offset removal circuit according to the present invention, it is preferable that the first noise shaping circuit includes a first pseudo random noise generation circuit.

  According to said structure, the periodicity in a 1st noise shaping circuit can be reduced, the spurious which a 1st noise shaping circuit generate | occur | produces can be reduced, and the high precision of a DC offset removal circuit can be achieved.

  In the DC offset removal circuit according to the present invention, it is preferable that the second quantization circuit has a hysteresis characteristic.

  According to the above configuration, when the output signal level of the second quantization circuit is an intermediate value between two adjacent output thresholds of the second quantization circuit, the output level of the second quantization circuit is the two outputs. A phenomenon that fluctuates at high speed between threshold levels can be avoided, and performance degradation of the DC offset removal circuit due to the phenomenon can be avoided.

  In the DC offset removal circuit according to the present invention, the second quantization circuit includes a mid-rise quantizer and a mid-tread quantizer, and the mid-rise quantizer according to a 1-bit state. It is preferable to have the hysteresis characteristic by switching between the output of the above and the output of the mid-tread type quantizer.

  According to said structure, a hysteresis characteristic is easily realizable.

  In the DC offset removal circuit according to the present invention, the first quantization circuit is preferably a second noise shaping circuit that performs noise shaping.

  According to said structure, the DC offset component contained in the output signal of a DC offset removal circuit can be quantized with a high dynamic range, and DC offset removal performance can be improved. Further, the number of output bits of the first quantization circuit can be reduced by the shaping operation, and the circuit scale and power consumption of the circuits after the first quantization circuit and the digital integration circuit can be reduced.

  In the DC offset removal circuit according to the present invention, it is preferable that the second noise shaping circuit has a bit number of 1 bit and an order of 1st order.

  According to the above configuration, the configuration of the first quantization circuit can be simplified, and at the same time, the number of output bits of the first quantization circuit can be reduced to 1 bit. The circuit scale and power consumption of the circuit and digital integration circuit can be reduced.

  In the DC offset removal circuit according to the present invention, the second noise shaping circuit preferably includes a second pseudo random noise generation circuit.

  According to the above configuration, the cutoff frequency of the high-pass characteristic of the DC offset removal circuit can be set to a desired value without depending on the signal level of the input analog signal.

  In the DC offset removal circuit according to the present invention, a variable gain stage disposed between the first quantization circuit and the digital integration circuit or between the digital integration circuit and the first noise shaping circuit; A saturation state detection circuit for detecting that the output of any circuit in the signal processing circuit is saturated, and the gain of the variable gain stage is controlled according to the detection result of the saturation state detection circuit. preferable.

  According to the above configuration, when the circuit in the DC offset removal circuit is saturated, it is possible to avoid deterioration of the tracking speed with respect to the DC offset fluctuation, and thus it is possible to recover from the saturated state in a short time.

  In the DC offset removal circuit according to the present invention, the saturation state detection circuit further includes a saturation frequency detection circuit for detecting the saturation frequency of the output, and the gain of the variable gain stage is controlled according to the saturation frequency. It is preferable.

  According to the above configuration, the configuration of the saturation state detection circuit can be simplified. Further, the time constant at the time of saturation can be made approximately equal to the time constant at the time of normal operation where it is not saturated.

  In the DC offset removal circuit according to the present invention, the first quantization circuit is arranged in a first LSI, and circuits other than the first quantization circuit of the DC offset removal circuit are arranged in a second LSI. It is preferable.

  According to the above configuration, since the number of bits of the first quantization circuit is small, the interface between LSIs can be simplified even when the DC offset removal circuit is divided and mounted on two LSIs. In addition, the number of LSI pins, I / O power consumption, and PCB area can be reduced.

  In the DC offset removal circuit according to the present invention, the number of bits of the first quantization circuit is preferably 1 bit.

  According to the above configuration, the number of LSI pins, I / O power consumption, and PCB area can be further reduced.

  A DC offset removal circuit according to the present invention is a DC offset removal circuit that removes a DC offset component mixed in a digital output signal of a signal processing circuit that performs signal processing on an analog input signal, and integrates the digital output signal. A digital integration circuit that performs quantization, a second quantization circuit that quantizes an output signal of the digital integration circuit, and a first noise that shapes quantization noise that is a difference between an input signal and an output signal of the second quantization circuit A shaping circuit; a first DA conversion circuit that converts an output signal of the second quantization circuit into an analog signal; a second DA conversion circuit that converts an output signal of the first noise shaping circuit into an analog signal; and the first DA conversion. A feedback circuit that feeds back the output signal of the circuit and the output signal of the second DA converter circuit to the analog input signal. It is characterized in that it comprises a back circuit.

  According to the above configuration, the number of bits of the signal input to the integration circuit increases, but the integration circuit can be configured with a digital integration circuit, and the quantization circuit can be eliminated, so that the circuit scale can be reduced.

  A receiver according to the present invention has at least one signal path including a baseband analog circuit that processes an output signal of a mixer and an AD conversion circuit that converts the output signal of the baseband analog circuit into a digital signal. The above-mentioned DC offset removing circuit is provided as a DC offset removing circuit for removing a DC offset component mixed in the output signal of the signal path.

  According to said structure, the receiver which can remove the DC offset component of a signal path with high precision with a simple structure is realizable.

The DC offset removal circuit according to the present invention is a DC offset removal circuit for removing a DC offset component mixed in a digital output signal of a signal processing circuit that performs signal processing on an analog input signal, as described above. A first quantization circuit for quantizing the digital output signal; a digital integration circuit for integrating the output signal of the first quantization circuit; a first noise shaping circuit for shaping the output signal of the digital integration circuit; said the DA converter circuit for the output signal of the first noise shaping circuit for converting an analog signal, the output signal of the DA converter circuit and a feedback circuit for feeding back to said analog input signal, said first quantizing circuit, noise since the second noise shaping circuit for performing shaping of the analog signal processing circuit Application can, an effect that can realize a DC offset removal circuit capable of removing DC offset components with high precision small circuit scale.

Embodiment 1
The first embodiment of the present invention will be described below with reference to FIG. In this embodiment, a case where a DC offset removing circuit is applied to a signal processing circuit that processes an analog input signal and outputs a digital signal will be described.

FIG. 1 is a block diagram showing a configuration of a DC offset removal circuit 100 according to the present embodiment. The DC offset removal circuit 100 is a circuit that removes a DC offset component mixed in the output signal Z of the signal processing circuit 110, and includes a quantizer 1, a gain stage 2, a digital integrator 3, a noise shaping circuit 4, and a DA converter. 5, a low-pass filter 6 and a subtractor 7 are provided. The signal processing circuit 110 includes an analog signal processing circuit 111, an AD converter 112, and a digital filter 113. Analog signal processing circuit 111 performs filtering, amplification processing and the like to the output signal Y ₀ from the subtracter 7, and outputs a signal Y _1. AD converter 112 converts the output signal _{Y 1} from the analog signal processing circuit 111 into a digital signal _{Y 2.} The digital filter 113 performs a filtering process on the digital signal Y ₂ and outputs an M-bit digital signal Z as an output signal of the signal processing circuit 110.

Quantizer 1 outputs a signal Z _Q N-bit signal Z by quantizing (N <M). Gain stage 2, by amplifying or attenuating the signal Z _Q outputs a signal Z _I. Although it is possible to perform the DC offset removal function without providing the gain stage 2, the gain stage 2 is provided in a normal offset removal circuit in order to adjust the cutoff frequency of the DC offset removal. . Further, the gain stage 2 may be disposed between the digital integrator 3 and the noise shaping circuit 4.

Digital integrator 3 is substantially identical to the digital integrating circuit 401 shown in FIG. 17, by integrating the output signal Z _I of the gain stage 2, and outputs a signal Z _O. The signal Z _O is noise-shaped by the noise shaping circuit 4. The DA converter 5 converts the digital output signal from the noise shaping circuit 4 into an analog signal, and the low-pass filter 6 attenuates unnecessary signals other than the DC component included in the output signal from the DA converter 5 to obtain a DC signal. The offset signal X_DC is fed back to the subtractor 7. The subtractor 7 subtracts the DC offset signal X_DC calculated from the output signal Z as described above from the analog input signal X, and outputs the signal Y ₀ to the analog signal processing circuit 111.

Here, the noise shaping circuit 4 is a generally well-known circuit, and includes an adder 4A, a quantizer 4B, a subtractor 4C, and a one-clock delay unit 4D. Adder 4A adds the feedback signal from the signal Z _O and 1 clock delayer 4D from the digital integrator 3. The quantizer 4B quantizes the output of the adder 4A. The subtractor 4C calculates the difference between the input signal and the output signal of the quantizer 4B. The difference from the subtracter 4C is output as a feedback signal to the adder 4A via the 1-clock delay 4D. The low-pass filter 6 includes a resistor 6A and a capacitor 6B. The low pass filter 6 may include a buffer connected to the resistor 6A and the capacitor 6B.

  Unlike the conventional DC offset removal circuit using an analog circuit, the DC offset removal circuit 100 can configure an integrator with a digital circuit, so that a capacitor having a large capacity is not required for the integrator. Compared to an analog integrator, a digital integrator can easily realize a high-accuracy integrator by increasing the number of bits, so that it is easy to improve the DC offset removal performance.

  The output signal Z of the signal processing circuit 110 is a digital signal having a high resolution, usually 10 to 16 bits. However, since only the DC component of the output signal Z needs to be extracted, a high resolution is often unnecessary as a feedback signal of the DC offset removal circuit 100. In that case, in the quantizer 1, the circuit size and power consumption of the gain stage 2 and the digital integrator 3 can be reduced by reducing the number of bits from M bits to N bits (N <M).

However, since the DC offset removal circuit 100 is a circuit that removes DC offset components included in the output signal Z (that is, zeros), the quantizer 1 performs DC truncation or the like on the output signal Z. Care must be taken not to mix any ingredients. Even if rounding is performed instead of bit truncation, there is a possibility that a DC offset component may be mixed in the output signal Z depending on the characteristics of the output signal of the DC offset removal circuit 100. In other words, the quantizer 1 for a non-linear element, for example, by second-order distortion and the like, which may occur an unnecessary DC component from the frequency component other than the DC output signal Z in the Z _Q. Therefore, it is preferable to use a method of performing quantization by inputting sufficient pseudo noise to the signal Z input to the quantizer 1 or a 1-bit noise shaping circuit described in the second embodiment described later.

  Further, the quantization noise mixed from the quantizer 1 has a gain of almost 1 and the noise filtered by the low-pass filter having the same cutoff frequency as that of the DC offset removal circuit 100 is output to the output signal Z. appear. It is necessary to consider the quantization noise component of the quantizer 1 that appears in the output signal Z when selecting the number of quantization bits.

Here, the output signal of the quantizer 1 is represented by the sum of the quantization noise Q and the input signal, and the digital integrator 3 is Z ⁻¹ / (1−Z ⁻¹ ) to 1 / (s · Ts), Assume that the gain of the gain stage 2 is k, the noise shaping circuit 4, the DAC 5 and the low-pass filter 6 are circuits having no frequency characteristic of gain 1 at a low frequency, and the analog signal processing circuit 111 has a gain of _{GIF VGA} and no frequency characteristic. Assuming that the AD converter 112 and the digital filter 113 are also circuits having no frequency characteristic of gain 1, the filter characteristic for the input signal X and the quantization noise Q of the DC offset removal circuit is that the frequency is near zero, If you simplify each block,

It is expressed. Here, Ts is an operation cycle of the DC offset removal circuit. From this equation (3), the frequency characteristic from the input signal X to the output signal Z has a high-pass characteristic at a low frequency, and the cut-off frequency fc depends on the gain of the gain stage 2 and the analog signal processing circuit 111. (Fc = k · G _IFVGA / (2πTs)). It can also be seen that the frequency characteristic from the quantization noise Q mixed in the quantizer 1 to the output signal Z has a low-pass characteristic.

  When the DC offset removal circuit 100 shown in FIG. 1 is applied to a baseband circuit for a direct conversion radio receiver, the analog signal processing circuit 111 has a maximum gain of 40 to 50 dB, so that the spurious included in the DC offset signal X_DC is an analog signal. It is amplified by the processing circuit 111 and appears in the output signal Z. At this time, when the output of the digital integrator 3 is directly converted into an analog signal by the DA converter 5 without using the noise shaping circuit 4 or the low-pass filter 6 and fed back to the subtractor 7, the spurious component is made sufficiently small. Therefore, the DA converter 5 needs a high resolution of about 12 to 14 bits. However, designing such a high-performance DA converter requires a lot of time and increases the circuit area.

On the other hand, as shown in FIG. 1, the number of bits required for the DA converter 5 can be greatly reduced by converting the output of the digital integrator 3 to low bits by the noise shaping circuit 4 (about 7 bits). . In addition to the output component of the digital integrator 3, the quantization noise generated by the quantizer 4B by the noise shaping operation of the noise shaping circuit 4 is H (z) = 1−Z ^{− in} the output of the DA converter 5. A noise component shaped with a characteristic of ¹ is included. This noise component is small in the vicinity of DC, but has a characteristic of increasing as the frequency becomes higher (the operating frequency fs of the noise shaping circuit 4).

  A low-pass filter 6 is arranged to remove this noise component. The low-pass filter 6 is a primary filter including a resistor 6A and a capacitor B, and the cut-off frequency may be set to a low frequency so that the shaped noise component can be sufficiently attenuated. Since the cut-off frequency can be set larger than the cut-off frequency fc of the high-pass characteristic of the conventional DC offset removing circuit 300 shown in FIG. 16, the size of the capacitor 6B constituting the low-pass filter 6 can be reduced. Therefore, by using the configuration of the DC offset removal circuit 100 shown in FIG. 1, the required capacitor size is small and the configuration of the DA converter 5 is simple. Can be realized.

  In FIG. 1, for simplification of explanation, the first order is selected as the order of the noise shaping circuit 4 and the order of the low-pass filter 6.

  In FIG. 1, the low-pass filter 6 is arranged to remove the high-frequency quantization noise shaped by the noise shaping circuit 4, but the desired signal included in the input signal X even if the quantization noise is inputted. When the signal is not deteriorated or when the role of the low-pass filter 6 can be used in the analog signal processing circuit 111, the low-pass filter 6 is not necessary.

  In the present embodiment, the subtractor 7 feeds back the DC offset signal X_DC by subtracting it from the input signal X. However, the present invention is not limited to this. For example, a DC offset signal X_DC may be fed back to the input signal X by providing a gain stage with a gain of −1 in the DC offset removal circuit and providing an adder instead of the subtractor 7.

[Embodiment 2]
A second embodiment of the present invention will be described below with reference to FIGS.

  FIG. 2 is a block diagram showing a configuration of the DC offset removal circuit 120 according to the present embodiment. The DC offset removal circuit 120 includes a quantizer 11, a gain stage 12, a digital integrator 3, a noise shaping circuit 14, a DA converter 15, a low-pass filter 16, and a subtractor 7. That is, in the DC offset removal circuit 100 shown in FIG. 1, instead of the quantizer 1, the gain stage 2, the noise shaping circuit 4, the DA converter 5, and the low-pass filter 6, the quantizer 11, the gain stage 12, and the noise shaping are used. The circuit 14, the DA converter 15, and the low-pass filter 16 are provided. As described later, the quantizer 11 is preferably composed of a 1-bit primary noise shaping circuit.

The signal processing circuit 110 has substantially the same configuration as the signal processing circuit 110 illustrated in FIG. 1 and includes an analog signal processing circuit 111, an AD converter 112, and a digital filter 113. Analog signal processing circuit 111, for example, an analog filter 111A for extracting only a desired frequency component from the analog input signal Y _0, and a variable gain stage 111B for amplifying the filter output from the subtracter 7 to filter and amplification processing or the like of the output signal Y _0.

  When the DC offset removal circuit 120 of FIG. 2 is applied to a baseband circuit for a direct conversion radio receiver, the variable gain stage 111B requires a wide range of 30 to 40 dB and a gain range of 30 dB. Further, since the gain of the gain stage 12 is controlled according to the amplitude of the input signal X, it is controlled independently of the feedback loop of the DC offset removal circuit 120. Therefore, the gain change of the variable gain stage 111B affects the filter characteristics of the DC offset removal circuit 120.

In order to reduce this effect, the gain stage 12 has a gain stage 12A for determining the time constant of the loop and a gain stage 12B for correcting the gain change of the variable gain stage 111B. When the gain of the gain stage 111B is G _IFVGA , the gain of the gain stage 12B is controlled to be 1 / G _{IF VGA} . Although not shown in FIG. 2, a saturation state detection circuit for controlling the gain of the gain stage 12A is connected to the gain stage 12A. The saturation state detection circuit will be described in detail with reference to FIG.

  The noise shaping circuit 14, the DA converter 15 and the low pass filter 16 may be configured as simple as the noise shaping circuit 4, the DA converter 5 and the low pass filter 6 in the DC offset removal circuit 100 of the first embodiment. Good. However, in the configuration of the first embodiment, the thermal noise of the resistor 6A output to the subtractor 7 becomes a problem. In order to reduce thermal noise without lowering the resistance value of the resistor 6A, there is a method in which the output of the low-pass filter 6 is attenuated and fed back to the subtractor. However, in this method, the amplitude range of the DC offset signal X_DC that determines the range in which the DC offset component included in the input signal X can be removed becomes small. In order to reduce the influence of the thermal noise of the resistor 6A without sacrificing the amplitude range of X_DC, the resistance value of the resistor 6A must be set small. At this time, it is necessary to increase the capacitor of the low-pass filter 6, and the capacitor area increases.

  On the other hand, in this embodiment, this problem is avoided by dividing the DA converter into two DA converters.

FIG. 3 is a block diagram showing detailed configurations of the DA converter 15 and the low-pass filter 16 shown in FIG. The DA converter 15 is divided into an MSB side DA converter 15A and an LSB side DA converter 15B. The output P bit of the noise shaping circuit 14 is divided into the MSB side L bit and the LSB side P-L bit, the MSB side L bit is input to the MSB side DA converter 15A, and the LSB side P-L bit is converted to the LSB side. Input to the DA converter 15B. Low pass filter 16, resistor 16, capacitor 16B and the gain is provided with a gain stage 16C is 1/2 ^L. An adder 17 is provided between the low-pass filter 16 and the subtractor 7. The adder 17 adds the output of the MSB side DA converter 15A and the output of the low-pass filter 16.

  The output of the MSB side DA converter 15 </ b> A is output to the adder 17 provided between the low pass filter 16 and the subtracter 7 without passing through the low pass filter 16. Thus, the output of the MSB side DA converter 15A is directly fed back to the input signal X. On the other hand, the output of the LSB side DA converter 15 B is output to the adder 17 via the low-pass filter 16. That is, the output of the LSB side DA converter 15B is fed back to the input signal via the low pass filter 16.

The amplitude range of the DC offset signal X_DC is set by the output range of the MSB side DA converter 15A. On the other hand, the output range of the low-pass filter 16 can be reduced to 1/2 ^L compared to the amplitude range of the DC offset signal X_DC. By using this configuration, the thermal noise of the resistor 16A constituting the low-pass filter 16 is attenuated to 1/2 ^L by the gain stage 16C, so that the influence of the thermal noise can be reduced. Therefore, the resistance value of the resistor 16A of the low-pass filter 16 can be set to a large value, and the size of the capacitor 16B can be reduced.

  3 is a conceptual diagram for simply explaining that the problem of thermal noise (capacitor size problem of the low-pass filter 16) can be avoided. Therefore, a more realistic circuit configuration can be represented by noise shaping. The circuit 14 will be described below with reference to FIG.

  FIG. 4 is a block diagram showing detailed configurations of the noise shaping circuit 14 and the DA converter 15 shown in FIG. The noise shaping circuit 14 includes a quantizer 14A, an MSB side quantizer 14B, a subtractor 14C, a gain stage 14D, an adder 14E, an LSB side quantizer 14F, a subtractor 14G, and a one-clock delay element 14H. .

  The quantizer 14A quantizes the 24-bit output of the integrator 3 shown in FIG. 2 into 15 bits. The MSB side quantizer 14B quantizes the 15-bit quantized output of the quantizer 14A into 7 bits (dac_msb [6: 0]) and outputs the quantized output to the MSB DA converter 15A. The subtractor 14C outputs the difference between the output of the quantizer 14A and the output after quantization by the MSB side quantizer 14B. The gain stage 14D amplifies the output of the subtracter 14C. The adder 14E, the LSB side quantizer 14F, the subtractor 14G, and the one-clock delay element 14H constitute a 1-bit noise shaping circuit, and the output of the gain stage 14D is a four-value output (3-bit width, dac_lsb [2 : 0]).

  The output of the integrator 3 may be input to the MSB side quantizer 14B without providing the quantizer 14A. However, in this case, since the number of output bits of the subtractor 14C increases, it is necessary to increase the circuit scale after the gain stage 14D.

  The LSB side DA converter 15B DA-converts the noise-shaped quaternary output (dac_lsb [2: 0]), and the MSB side DA converter 15A outputs the output (dac_msb [6: 0] of the MSB side quantizer 14B). ]) Is DA converted. The low-pass filter 16 performs low-pass filtering on the output of the LSB side DA converter 15B, and the output of the MSB side DA converter 15A and the output of the low-pass filter 16 are added by the adder 17.

  The input signal of the MSB side DA converter 15A is not a noise-shaped signal but a value determined by the upper bits of the output of the integrator 3. On the other hand, the input signal of the LSB side DA converter 15B is a signal obtained by noise shaping the residual of the MSB side quantizer 14B. The output of the LSB side quantizer 14F is converted into a thermometer code that can take four values and input to the LSB side DA converter 15B (dac_lsb [2: 0] = “000” or “001” or “011” ”Or“ 111 ”). The thermometer code may be 2, 4 or 5 values. The output of the MSB side DA converter 15A changes slowly until the feedback loop of the DC offset removal circuit 120 becomes stable, but does not change after stabilization, so a low-pass filter is not required for the output of the MSB side DA converter 15A. It is.

  Assuming that after the feedback loop is stabilized, the input signal does not change beyond the quantization threshold of the MSB side quantizer 14B, the output of the MSB side quantizer 14B and the output of the MSB side DA converter 15A change. do not do. Therefore, it is preferable to set the number of quantization bits of the MSB side quantizer 14B low enough that the output of the MSB side quantizer 14B does not change after the feedback loop is stabilized.

  On the other hand, the LSB side DA converter 15B always operates at a high speed before and after the feedback loop becomes stable, and the quantized noise of the shaped LSB side quantizer 14F is generated at the output of the LSB side DA converter 15B. included. In order to reduce the quantization noise, the low-pass filter 16 is required. Further, as the LSB side DA converter 15B, it is preferable to use a DA converter that inputs a thermometer code that can easily reduce the spurious component of the LSB side DA converter 15B. In this case, the thermometer code DA converter has better spurious characteristics during high-speed operation than the binary weight DA converter.

When the configuration of FIG. 4 is used, when the DC component included in the DC offset signal X_DC becomes an intermediate value between two adjacent output levels of the MSB side DA converter 15A, the output of the MSB side DA converter 15A, that is, the MSB side quantum The output of the generator 14B fluctuates at high speed between digital values corresponding to the two output levels, and many spurious signals are generated in the DC offset signal X_DC. In order to avoid this, if the MSB side quantizer 14B has a hysteresis characteristic, the fluctuation can be avoided. Hereinafter, an implementation method for providing the MSB side quantizer 14B with hysteresis characteristics will be briefly described with reference to FIG. Note that the number of output bits of the MSB side quantizer 14B in FIG. 4 is 7 bits, and the possible output value is 2 ⁷ = 128 levels, but here, for the sake of simplicity, the MSB side quantization is performed. The possible value of the output value of the device 14B is assumed to be 7 levels.

  As shown in FIGS. 5A and 5B, the MSB side quantizer 14B includes two quantization characteristics having different output thresholds, a mid-rise type and a mid-tread (Mid-tread). ) Type quantizers are combined in parallel. FIG. 5A is a graph showing the relationship between the input INPUT and the output OUTPUT of the mid-rise quantizer, and FIG. 5B is the relationship between the input INPUT and the output OUTPUT of the mid-tread quantizer. It is a graph which shows.

  The output values that the mid-rise quantizer can take are four levels, -3, -1, 1, and 3. On the other hand, the output values that the mid-tread quantizer can take are three levels, -2, 0, and 2. The two quantizers together have a total of 7 levels. Only one of the mid-rise quantizer and the mid-tread quantizer is effective, and the output of the other quantizer is zero at that time. Whether to use a mid-rise quantizer or a mid-tread quantizer is determined as follows.

The MSB side quantizer 14B has a 1-bit state. The MSB side quantizer 14B performs the following processes (1) to (3).
(1) When a state = 0, a mid-rise quantizer is used, and when a state = 1, a mid-tread quantizer is used to quantize and output an input signal.
(2) When the output value of the MSB side quantizer 14B changes, the next state is set according to the graph showing the correspondence between the input value INPUT and the state value of the quantizer 14B in FIG. Update. When the output of the quantizer 14B does not change, the current state value is maintained.
(3) At the next clock, the process returns to (1) and the same processing is repeated.

  By this operation, hysteresis characteristics can be realized, high-speed fluctuations between the digital values as described above are eliminated, and spurious generation does not occur. Note that the above-described method for realizing the hysteresis characteristic is an example, and the present invention is not limited to this method.

  In FIG. 4, the 1-bit noise shaping circuit composed of the adder 14E, LSB side quantizer 14F, subtractor 14G, and 1 clock delay element 14H is assumed to be primary noise shaping. A noise shaping circuit may be used. Further, a pseudo random noise generator for generating pseudo random noise is provided, and the pseudo random noise is added to the input section of the quantizer 14F to reduce spurious due to the periodicity of the 1-bit noise shaping circuit. preferable. This spurious component appears at the output Z of the DC offset removal circuit 120 through the LSB side DA converter 15B / low-pass filter 16 of FIG. 4, the analog signal processing circuit 111, the AD converter 112 and the digital filter 113 of FIG. In addition, said pseudo random noise generator is corresponded to the 1st pseudo random noise generator as described in a claim.

  Further, the configuration using the noise shaping circuit and the quantizer 14B, which are composed of the adder 14E, LSB side quantizer 14F, subtractor 14G, and one clock delay element 14H shown in FIG. This is also effective when the signal X is not an analog signal but a digital signal, and the DC offset removal circuit 120 shown in FIG. However, in this case, the DA converter 15 is unnecessary, and the low-pass filter 16 is realized by a digital circuit.

  Next, a specific configuration of the MSB side DA converter 15A will be described.

  FIG. 6 is a circuit diagram showing a specific configuration example of the fully differential MSB side DA converter 15A. The configuration shown in FIG. 6 is a generally well-known current steering type DA converter, which includes current sources M1, M4, and M5 and a differential pair M2 and M3. The current source M1 is realized by an N-channel MOS transistor and is weighted by 2 to the power of I. The differential pair M2 and M3 determines whether the current of the current source M1 flows to the differential output terminal voutp or the differential output terminal voutm. The current sources M4 and M5 cause a constant current to flow from the power supply VDD side to the differential output terminal voutp and the differential output terminal voutm, respectively. A bias voltage vb1_msb and a bias voltage vb2_msb for setting the current source current value to desired values are applied to the gates of the current source M1 and the current sources M4 and M5, respectively. The configuration of the MSB side DA converter 15A is not limited to this method.

  Next, specific configurations of the LSB DA converter 15B and the low-pass filter 16 illustrated in FIG. 4 will be described.

  FIG. 7 is a circuit diagram showing a specific configuration example of the fully differential LSB DA converter 15B and the low-pass filter 16. As shown in FIG. The LSB side DA converter 15B shown in FIG. 7 is a current steering type DA converter similarly to the MSB side DA converter 15A of FIG. The LSB side DA converter 15B has a symmetric full differential configuration.

  The LSB side DA converter 15B has a configuration in which a plurality of 1-bit DA converter circuits of the same size are connected in parallel, and includes a current source M11, a differential pair M12 / M13, two P-channel MOS transistors M16, and two P-channels. A MOS transistor M17 and two current sources M18 are provided. The low pass filter 16 includes a resistor 16A and a capacitor 16B.

  The current source M11 is composed of three N-channel MOS transistors, and each current source M11 has the same size. The differential pair M12 and M13 switches the current of the current source M11 to flow to one side of the two P-channel MOS transistors M16. The P-channel MOS transistor M16 has a gate and a drain connected (diode connection), adds the output currents of the differential pairs M2 and M3, and converts them into a voltage.

  Resistor 16A and capacitor 16B output the output voltage of P-channel MOS transistor M16 by low-pass filtering. The P-channel MOS transistor M17 extracts the low-pass filtered voltage as a current, and the current source M18 extracts a constant current from the differential output terminal voutp and the differential output terminal voutm to the GND side.

Current output range of LSB side DA converter 15B (if the LSB side DA converter 7 bits, about ^{1/2 5)} can be reduced as compared with the MSB side DA converter 15A, the influence of the thermal noise of the resistor 16A Can be made small enough to be ignored.

  As described above, the MSB side DA converter 15A and the LSB side DA converter 15B are both configured as a current steering type DA converter, and the differential output terminal voutp shown in FIG. 6, the differential output terminal voutp shown in FIG. The adder 17 shown in FIG. 4 can be realized by connecting the differential output terminal voutm shown in FIG. 6 and the differential output terminal voutm shown in FIG. 7 to each other. However, since the output signal is a current signal, the input impedance of the subtractor 7 or the analog signal processing circuit 111 connected to the differential output terminals voutp · voutm needs to be lowered.

  The configuration example of the current steering type DA converter is shown as an example of the MSB side DA converter 15A and the LSB side DA converter 15B. However, the voltage output DA converter is composed of a plurality of resistance ladders and buffers. But you can. In this case, it is preferable to set the input impedance of the subtractor 7 or the analog signal processing circuit 111 connected to the differential output terminals voutp / voutm high.

  Next, a configuration example of the gain stage 12A in FIG. 2 will be described. When there is no signal saturation in the DC offset removal circuit 120 and it is desired to keep the loop time constant constant, the gain stage 12A may be always set to a constant gain. Further, when the DC offset component included in the output signal Z is large, the gain of the gain stage 12A is set large, and when the DC offset component is small, the gain of the gain stage 12A is set small. The gain of the gain stage 12A may be changed according to the DC offset amount of the output signal Z. By performing such setting, even if a large DC offset occurs, the DC offset can be reduced in a short time, and distortion due to the DC offset to the output signal Z can be reduced. Since such a gain setting can be easily conceived, further detailed explanation is omitted here.

  Next, a case where signal saturation (clipping) occurs in the signal processing circuit 110 will be described. The input range of the AD converter 112 is finite, and the AD converter 112 is saturated when a large DC offset is suddenly generated in the input signal X or the gain of the variable gain stage 111B is greatly changed to generate a large DC offset. . This signal saturation is likely to occur particularly when the gain of the variable gain stage 111B is set large. While the AD converter 112 is saturated, a large distortion occurs in the output signal Z. At this time, due to the saturation of the AD converter 112, the output value of the AD converter 112 becomes smaller than the output value obtained when it is assumed that there is no signal saturation, and the signal processing circuit 110 which is a part of the DC offset removal loop. The gain of is significantly reduced. Such a state is considered to occur even when the power is turned on. This is because the internal state of each circuit at power-on is indefinite, and the AD converter 112 and the like are likely to be in a saturated state. At this time, the settling for the DC offset removal becomes extremely slow, and the output signal Z may be distorted for a long time.

To solve this problem, in the present embodiment, for example, a digital signal Y ₂ and the output signal Z is according to the frequency to be saturated, to change the gain of the gain stage 12A. That is, when the circuit arranged in the feedback loop, for example, the AD converter 112 is saturated, the gain of the gain stage 12A is set high, and when it is not saturated, the gain is set to a desired loop time constant. As a result, even when the AD converter 112 arranged in the feedback loop is saturated, it is possible to immediately return from the saturated state and reduce the saturated state of the output signal Z. A configuration example of the gain stage 12A and the saturation state detection circuit 8 for performing such control will be described with reference to FIG.

  FIG. 8 is a block diagram illustrating a specific configuration example of the gain stage 12 </ b> A and the saturation state detection circuit 8. The gain stage 12 </ b> A is a variable gain stage whose gain is controlled based on the output from the saturation state detection circuit 8. The saturation state detection circuit 8 includes a lookup table 8A, a counter 8B, a comparator 8C, and an absolute value circuit 8D. The absolute value circuit 8 </ b> D is a circuit that takes the absolute value of a signal for which it is desired to check whether or not it is saturated. Here, a signal for detecting saturation is an output signal Z of the signal processing circuit 110. The comparator 8C compares the output of the absolute value circuit 8D with a certain threshold value THRESHOLD. The counter 8B counts the output of the comparator 8C and counts the frequency with which the output signal Z is saturated. The look-up table 8A holds a gain setting corresponding to the output value of the counter 8B, and the gain of the gain stage 12A is changed according to the look-up table 8A.

  Here, the counter 8B is reset every certain period, and the saturation value of the output signal Z can be obtained by outputting the count value immediately before the reset to the lookup table 8A.

  FIG. 9A is a graph showing an example of data held in the lookup table 8A. The horizontal axis is the saturation frequency of the signal Z, and the vertical axis is the average value of the amplitude ratio between the amplitude of the signal Z when it is assumed that it is not saturated and the amplitude of the signal Z when it is saturated at a certain saturation frequency.

  Here, the relationship between the saturation frequency and the average value of the amplitude ratio will be described with reference to FIG.

  FIG. 9B is a graph showing the output waveform of the circuit in a state where the triangular wave is clipped. Thus, when the triangular wave is output continuously, the triangular wave is clipped at a certain saturation level by the circuit. A broken line indicates a waveform that should be output originally, and the signal indicated by the broken line is clipped to a saturation level. The saturation frequency is a time ratio at which the triangular wave is clipped, and is expressed by D / C. On the other hand, the average value of the amplitude ratio is represented by (area of area A + area of area B) / area of area A. Here, the region A indicates a trapezoid formed below the saturation level, and the region B indicates a triangle above the saturation level.

  In FIG. 9A, the alternate long and short dash line indicates the look-up table characteristic when a certain signal Z is a sine wave, and the broken line indicates the look-up table characteristic when a certain signal Z is a random signal. Yes. By preparing a look-up table that has characteristics close to those of sine waves and random signals, even when the circuit placed in the feedback loop is saturated, the settling characteristics similar to those when it is not saturated are approximately realized. can do.

  In addition, the look-up table characteristic indicated by the solid line in FIG. 9A is approximated so as to be close to the characteristic in the case of the sine wave or the random signal. This characteristic has saturation frequency threshold values of 0.5, 0.5 * (1 + 1/2), 0.5 * (1 + 1/2 + 1/4), and so on. It can be realized compactly.

  Next, a preferred example of the quantizer 11 shown in FIG. 2 will be described with reference to FIGS. Since the quantizer 11 only needs to be able to quantize only the DC offset with high resolution, a 1-bit primary noise shaping circuit is preferable.

  FIG. 10 is a circuit diagram showing a quantizer 11 composed of a 1-bit primary noise shaping circuit. The quantizer 11 includes an adder 11A, a delay unit 11B, an LFSR (Linear Feedback Shift Register) 11C, a gain stage 11D, an adder 11E, a quantizer 11F, and a subtractor 11G. The adder 11A adds the signal Z and the feedback signal from the subtractor 11G. The delay device 11B delays the output of the adder 11A by one clock. The LFSR 11C is a circuit that generates pseudo-random noise. The gain stage 11D amplifies or attenuates the output of the LFSR 11C. The adder 11E adds the delay device 11B and the output of the gain stage 11D. The quantizer 11F quantizes the output of the adder 11E by 1 bit, and the subtractor 11G calculates the difference between the output of the delay device 11B and the output of the quantizer 11F. The LFSR 11C corresponds to the second pseudo random noise generating circuit described in the claims.

  Here, the importance of using pseudo-random noise in the noise shaping circuit will be described with reference to FIG.

  FIG. 11 is a graph showing the FFT spectrum of the output signal Z when the DC offset removal circuit 120 is applied to the signal processing circuit 110 shown in FIG. 2. FIG. 11A shows the gain stage 11D of the quantizer 11. A case where the gain is zero, that is, a case where pseudo-random noise is not input is shown, and (b) shows a case where the gain of the gain stage 11D is set to a desired value. Here, a 1 MHz sine wave and an appropriate level of noise corresponding to circuit noise were input to the input signal X. The operating frequency of the digital circuit after the AD converter 112 was set to 20 MHz. Further, the gain of the gain stage 12A is set so that the cut-off frequency of the high-pass filter characteristic of the DC offset removal circuit 120 is about 2.8 kHz.

  As a result, a 1 MHz sine wave output input to the input signal X was observed in the graphs of FIGS. The reason why the noise floor rises from around 8 MHz is that the quantization noise of the AD converter 112 is shaped to a high frequency because the ΔΣ AD converter is used as the AD converter 112 in FIG. At a frequency of 10 kHz or less, the input pseudo-random noise is attenuated according to the high-pass characteristic of the DC offset removal circuit 120.

As shown in FIG. 11A, when no pseudo-random noise is input, the cut-off frequency of the high-pass characteristic is about 8 kHz. On the other hand, as shown in FIG. 11B, when pseudo-random noise is input, the cutoff frequency of the high-pass characteristic is around 2.5 kHz, which is close to the initial set value of 2.8 kHz. Deviation of the cut-off frequency of the high-pass characteristic when you do not enter a pseudorandom noise, conspicuous when the signal component in the output Z _Q is small. This is due to the characteristics of the quantizer 11, which is a 1-bit quantizer shown in FIG. Specifically, quantizer 11, without entering the pseudo-random noise, and, when the level of the signal Z is small, the gain from the signal Z to the output Z _Q is greater than 1 is a desired value In addition, it is considered that the deviation of the cut-off frequency occurs.

In addition, in the quantizer 11 of FIG. 10 which is a noise shaping circuit, when no pseudo-random noise is input and the level of the signal Z is low, periodicity appears in the internal state of the quantizer 11, and the periodicity thereof. depending on the gain from the signal Z to the output Z _Q fluctuates temporally. Due to this gain variation, the cutoff frequency of the high-pass filter varies temporally according to the periodicity. In order to prevent such a variation in the cut-off frequency, it is preferable to input pseudo-random noise in the 1-bit quantizer shown in FIG.

  Further, when the quantizer 11 is a 1-bit quantizer that does not have a noise shaping function, large quantization noise is mixed in the band and appears in the output signal Z. However, if the quantization noise is not a problem, the quantizer 11 may be a 1-bit quantizer that does not have a noise shaping function.

[Embodiment 3]
The following describes the third embodiment of the present invention with reference to FIG. In the DC offset removal circuit 120 according to the second embodiment, it is assumed that the input signal of the signal processing circuit is an analog signal and the output signal is a digital signal, but the output signal of the signal processing circuit may be an analog signal. In the present embodiment, a case where the output signal of the signal processing circuit is an analog signal will be described.

  FIG. 12 is a block diagram showing a configuration of the DC offset removal circuit 130 according to the present embodiment. The DC offset removal circuit 130 includes a quantizer 21, a gain stage 12, a digital integrator 3, a noise shaping circuit 14, a DA converter 15, a low-pass filter 16, and a subtractor 7, and outputs from the analog signal processing circuit 111. This circuit removes a DC offset component mixed in a signal. That is, the DC offset removal circuit 130 is configured to provide the quantizer 21 in place of the quantizer 11 in the DC offset removal circuit 120 shown in FIG.

Since the AD converter 112 and the digital filter 113 are not provided, the output signal Z is an analog signal. The quantizer 21, the number of output bits ΔΣ-type AD converter is a one-bit is suitably used, the quantizer 21 converts the output signal Z into a digital signal Z _Q. Since the number of output bits of the quantizer 21 is 1, the circuit scale of the gain stage 12 and the digital integrator 3 after the quantizer 21 can be reduced. The ΔΣ AD converter is easy to design.

  The quantizer 21 may be a Nyquist AD converter instead of the ΔΣ type. In this case, the number of output bits of the AD converter is desirably 1 to 12 bits.

  Here, since the DC offset component generated by the quantizer 21 cannot be removed, when it is desired to remove the DC offset component with high accuracy, some function for removing the DC offset component may be added to the quantizer 21. preferable. For example, as a technique for realizing the function, an auto zero technique, a chopping technique, and the like can be given. Since these techniques are generally known techniques, description thereof is omitted here.

  In the DC offset removal circuit 120 according to the second embodiment and the DC offset removal circuit 130 according to the present embodiment, the low-pass filter 16 removes unnecessary high-frequency signals generated by the noise shaping circuit 14 and at the same time, the DA converter 15. Is provided to smooth the waveform. On the other hand, when there is no problem without such processing, or when the function of the low-pass filter 16 can be substituted by the analog filter 111A in the analog signal processing circuit 111, the low-pass filter 16 is not provided. Good.

[Embodiment 4]
The following describes the fourth embodiment of the present invention with reference to FIG. In the present embodiment, a case will be described in which the DC offset removal circuit 130 according to the third embodiment is further configured with an analog circuit as much as possible.

  FIG. 13 is a block diagram showing the configuration of the DC offset removal circuit 140 according to this embodiment. The DC offset removal circuit 140 includes an analog gain stage 22, an analog integrator 13, a noise shaping AD conversion circuit 24, a DA converter 15, a low-pass filter 16, and a subtractor 7. That is, the DC offset removal circuit 140 does not include the quantizer 21 in the DC offset removal circuit 130 shown in FIG. 12, and instead of the gain stage 12, the digital integrator 3, and the noise shaping circuit 14, the analog gain stage 22, In this configuration, an analog integrator 13 and a noise shaping type AD conversion circuit 24 are provided. Since the quantizer 21 is not provided, each circuit from the analog gain stage 22 to the noise shaping AD conversion circuit 24 is configured to be able to process an analog signal. Thereby, the quantizer 21 can be made unnecessary.

  Further, even when the output signal Z is a digital signal as in the signal processing circuit 110 shown in FIGS. 1 and 2, the signal Z is output to the gain stage 2 or the gain stage 12 without providing a quantizer. Also good. Even in this case, since the integrator can be constituted by a digital integrator, the circuit scale can be reduced.

[Embodiment 5]
The following describes the fifth embodiment of the present invention with reference to FIG. In particular, when the signal processing circuit is used to process the output signal from the mixer of the wireless device, the input signal X is very susceptible to disturbance noise. For this reason, in the signal processing circuit, it is preferable that the portion for processing the analog signal processing and the portion for processing the digital signal are mounted on different chips. Therefore, in the present embodiment, a configuration will be described in which the DC offset removal circuit and the signal processing circuit are divided and mounted on two integrated circuits when the DC offset removal circuit is integrated.

  FIG. 14 is a block diagram showing the configurations of the DC offset removal circuit 150, the signal processing circuit 110, and the DSP demodulation circuit 260 according to this embodiment. The signal processing circuit 110 and the DSP demodulation circuit 260 are substantially the same as the signal processing circuit 110 shown in FIG. 2 and the DSP demodulation circuit 260 shown in FIG.

  Among the circuits constituting the signal processing circuit 110, the analog signal processing circuit 111 is mounted on the integrated circuit LSI1, and the AD converter 112 and the digital filter 113 are mounted on the integrated circuit LSI2. The AD converter 112 may be mounted on the integrated circuit LSI1.

The DC offset removal circuit 150 has a configuration in which the quantizer 21 shown in FIG. 12 is provided in place of the quantizer 11 in the DC offset removal circuit 120 shown in FIG. Of the circuits constituting the DC offset removal circuit 150, only the quantizer 21 is mounted on the integrated circuit LSI1, and the gain stage 12, the digital integrator 3, the noise shaping circuit 14, the DA converter 15, the low-pass filter 16, and the subtractor 7 are included. Is mounted on the integrated circuit LSI2. Thus, the DC offset removal circuit 150, the output signal _{Z Q} of the quantizer 21 is used as the inter Fes between the integrated circuit LSI1 an integrated circuit LSI 2. Thus, since the output signal _ZQ becomes a 1-bit signal by using a 1-bit noise shaping circuit as a quantizer, the number of interfaces between LSIs, that is, the number of LSI pins, PCB (printed circuit board) The number of wires can be greatly reduced. As a result, the LSI can be made compact and the PCB area can be saved.

[Summary of Embodiment]
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The DC offset removal circuit according to the present invention can be applied not only to a wireless receiver but also to a wired receiver.

It is a block diagram which shows the structure of the DC offset removal circuit which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the DC offset removal circuit which concerns on the 2nd Embodiment of this invention. FIG. 3 is a block diagram showing a detailed configuration of a DA converter and a low-pass filter of the DC offset removal circuit shown in FIG. 2. FIG. 3 is a block diagram showing a detailed configuration of a noise shaping circuit and a DA converter of the DC offset removal circuit shown in FIG. 2. (A) is a graph showing the relationship between the input INPUT and output OUTPUT of the mid-rise quantizer, and (b) is a graph showing the relationship between the input INPUT and output OUTPUT of the mid-tread quantizer. is there. It is a circuit diagram which shows the specific structural example of a full differential type MSB side DA converter. It is a circuit diagram which shows the specific structural example of a full differential LSB side DA converter and a low-pass filter. FIG. 3 is a block diagram illustrating a specific configuration example of a gain stage and a saturation state detection circuit of the DC offset removal circuit illustrated in FIG. 2. (A) is a graph which shows an example of the data hold | maintained at the look-up table of the said saturation state detection circuit, (b) is a graph which shows the output waveform of the circuit in the state in which the triangular wave is clipped. It is a circuit diagram which shows the quantizer comprised by a 1-bit primary noise shaping circuit. 6 is a graph showing an FFT spectrum of an output of a DC offset removal circuit, where (a) shows a case where the gain of the gain stage is set to zero in the quantizer, and (b) shows a desired gain of the gain stage. It shows the case of the value of. It is a block diagram which shows the structure of the DC offset removal circuit which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the DC offset removal circuit which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the DC offset removal circuit, signal processing circuit, and DSP demodulation circuit which concern on the 5th Embodiment of this invention. It is a block diagram which shows the structural example of the radio receiver of a general zero-IF architecture. It is a circuit diagram which shows the structure of the conventional DC offset removal circuit and an analog signal processing circuit. It is a circuit diagram which shows the structure of the other conventional DC offset removal circuit and analog signal processing circuit.

Explanation of symbols

1 Quantizer (first quantization circuit)
2 Gain stage (variable gain stage)
3 Digital integrator (digital integration circuit)
4 Noise shaping circuit (first noise shaping circuit)
5 DA converter (DA conversion circuit)
6 Low-pass filter 7 Subtractor (feedback circuit, subtraction circuit)
8 Saturation state detection circuit 8B Counter (saturation frequency detection circuit)
11 Quantizer (first quantization circuit)
11C LFSR (second pseudo random noise generator)
12A gain stage (variable gain stage)
13 Analog integrator (analog integration circuit)
14B MSB side quantizer (second quantization circuit)
14E Adder (first noise shaping circuit)
14F LSB side quantizer (first noise shaping circuit)
14G subtractor (first noise shaping circuit)
14H 1-clock delay element (first noise shaping circuit)
15A MSB DA converter (first DA converter)
15B LSB DA converter (second DA converter)
16 Low-pass filter 17 Adder (adder circuit)
21 Quantizer (first quantizer, AD converter, ΔΣ AD converter)
24 Noise shaping type AD converter circuit (first noise shaping circuit)
100, 120, 130, 140, 150 DC offset removal circuit 110 Signal processing circuit 111 Analog signal processing circuit 200 Wireless receiver (receiver)
241,251 Mixer 242,252 Signal processing circuit (baseband analog circuit)

Claims (23)

A DC offset removal circuit for removing a DC offset component mixed in a digital output signal of a signal processing circuit that performs signal processing on an analog input signal,
A first quantization circuit for quantizing the digital output signal;
A digital integration circuit for integrating the output signal of the first quantization circuit;
A first noise shaping circuit for shaping the output signal of the digital integration circuit;
A DA conversion circuit for converting an output signal of the first noise shaping circuit into an analog signal;
A feedback circuit for feeding back the output signal of the DA converter circuit to the analog input signal ,
The DC offset removal circuit according to claim 1, wherein the first quantization circuit is a second noise shaping circuit that performs noise shaping .   2. The DC offset removal circuit according to claim 1, wherein the number of bits of the output signal of the first quantization circuit is smaller than the number of bits of the digital output signal.   3. The DC offset removal circuit according to claim 1, further comprising a low-pass filter between the DA conversion circuit and the feedback circuit.   4. The DC offset removal circuit according to claim 1, wherein the feedback circuit is a subtraction circuit that subtracts an output signal of the DA conversion circuit from the analog input signal. A DC offset removal circuit for removing a DC offset component mixed in a digital output signal of a signal processing circuit that performs signal processing on an analog input signal,
A first quantization circuit for quantizing the digital output signal;
A digital integration circuit for integrating the output signal of the first quantization circuit;
A second quantization circuit for quantizing the output signal of the digital integration circuit;
A first noise shaping circuit for shaping a difference between an input signal and an output signal of the second quantization circuit;
A first DA conversion circuit for converting an output signal of the second quantization circuit into an analog signal;
A second DA conversion circuit for converting an output signal of the first noise shaping circuit into an analog signal;
A DC offset elimination circuit comprising: a feedback circuit that feeds back an output signal of the first DA conversion circuit and an output signal of the second DA conversion circuit to the analog input signal.   6. The DC offset removal circuit according to claim 5, further comprising a low-pass filter between the second DA conversion circuit and the feedback circuit. The feedback circuit includes an adder circuit that adds the output signal of the first DA converter circuit and the output signal of the second DA converter circuit;
7. The DC offset removal circuit according to claim 5, further comprising: a subtracter that subtracts the output signal of the adder circuit from the analog input signal.   8. The DC offset removal circuit according to claim 5, wherein the second DA conversion circuit has 2 to 5 output levels. The second DA converter circuit includes a plurality of 1-bit DA converter circuits of the same size,
9. The DC offset removal circuit according to claim 5, wherein the 1-bit DA conversion circuits are connected in parallel to each other. The second DA conversion circuit includes a current steering type DA conversion circuit that converts an input digital signal into a current;
A first MOS transistor for converting the current into a voltage;
A current mirror circuit together with the first MOS transistor, and a second MOS transistor for converting the voltage into an output current of the second DA converter circuit;
7. The DC offset removal circuit according to claim 6, wherein the low-pass filter is provided between the gate of the first MOS transistor and the gate of the second MOS transistor.   11. The DC offset removal circuit according to claim 1, wherein the order of the first noise shaping circuit is first order.   12. The DC offset removal circuit according to claim 1, wherein the first noise shaping circuit includes a first pseudo random noise generation circuit. DC offset removal circuit according to any one of claims 5-10 said second quantizing circuit, characterized in that it has a hysteresis characteristic.   The second quantization circuit includes a mid-rise quantizer and a mid-tread quantizer, and outputs the mid-rise quantizer and the mid-tread quantizer according to a 1-bit state. 14. The DC offset removal circuit according to claim 13, wherein the hysteresis characteristic is obtained by switching between the output and the output of the DC offset. 11. The DC offset removal circuit according to claim 5 , wherein the first quantization circuit is a second noise shaping circuit that performs noise shaping.   16. The DC offset removal circuit according to claim 15, wherein the second noise shaping circuit has a bit number of 1 bit and an order of 1st order.   17. The DC offset removal circuit according to claim 15, wherein the second noise shaping circuit includes a second pseudo random noise generation circuit. A variable gain stage disposed between the first quantization circuit and the digital integration circuit, or between the digital integration circuit and the first noise shaping circuit;
A saturation state detection circuit for detecting that the output of any circuit in the signal processing circuit is saturated,
18. The DC offset removal circuit according to claim 1, wherein a gain of the variable gain stage is controlled according to a detection result of a saturation state detection circuit. The saturation state detection circuit further includes a saturation frequency detection circuit for detecting the saturation frequency of the output,
The DC offset removal circuit according to claim 18, wherein the gain of the variable gain stage is controlled according to the saturation frequency. The first quantization circuit is disposed in a first LSI,
The DC offset removal circuit according to any one of claims 1 to 19 , wherein circuits other than the first quantization circuit of the DC offset removal circuit are arranged in a second LSI. 21. The DC offset removal circuit according to claim 20 , wherein the number of bits of the first quantization circuit is one bit. A DC offset removal circuit for removing a DC offset component mixed in a digital output signal of a signal processing circuit that performs signal processing on an analog input signal,
A digital integration circuit for integrating the digital output signal;
A second quantization circuit for quantizing the output signal of the digital integration circuit;
A first noise shaping circuit that shapes quantization noise that is a difference between an input signal and an output signal of the second quantization circuit;
A first DA conversion circuit for converting an output signal of the second quantization circuit into an analog signal;
A second DA conversion circuit for converting an output signal of the first noise shaping circuit into an analog signal;
A DC offset elimination circuit comprising: a feedback circuit that feeds back an output signal of the first DA conversion circuit and an output signal of the second DA conversion circuit to the analog input signal. In a receiver having at least one signal path including a baseband analog circuit that processes an output signal of a mixer and an AD conversion circuit that converts the output signal of the baseband analog circuit into a digital signal,
23. A receiver comprising the DC offset removal circuit according to any one of claims 1 to 22 as a DC offset removal circuit for removing a DC offset component mixed in an output signal of the signal path.

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