JP5022042B2 - Laminated structure of semiconductor element embedded support substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a stacked structure of a semiconductor element embedded support substrate and a method for manufacturing the same, and more particularly to a stacked structure formed by stacking a support substrate after a semiconductor element is embedded in the support substrate and a method for manufacturing the stacked structure.

With the dramatic development of the electronic industry, the research and development of electronic products has advanced in the direction of multi-functionality and high performance, thereby meeting the requirements for integration and miniaturization of semiconductor package materials. In order to respond to the trend of downsizing, increasing capacity, and speeding up of electronic products by improving the performance and capacity of semiconductor package members, in the past, a multi-chip module (Multi Chip Module, Semiconductor package members are formed by the MCM method, and this type of package member can reduce the overall package size and improve electrical performance, making it one of the mainstream of current packages. ing. In this multi-chip module, at least two semiconductor chips are joined to a chip support member in a single package member, and each semiconductor chip and the support member are joined in a stack system. This stack type chip package structure is disclosed in US Pat. No. 6,798,049.

FIG. 1 is a cross-sectional view of a CDBGA (Cavity-Down Ball Grid Array) package member disclosed in US Pat. No. 6,798,049. This CDBGA includes a circuit board 10 having a circuit layer 11. The circuit board 11 having the connection pad 11a and the bonding pad (Bound Pad) 11b is formed on at least one surface of the wiring substrate 10, and two stacked semiconductor chips 121 and 122 are formed in the opening 102. The semiconductor chips 121 and 122 are electrically connected to each other through a bonding layer (bonding layer) 13. The semiconductor chip 122 is electrically connected to the bonding pads 11b of the circuit layer 11 by a conductive device 14, which is a gold wire, for example. After that, the sealing resin 15 is filled in the opening 102 of the wiring substrate 10 to cover the semiconductor chips 121 and 122 and the conductive device 14, and the circuit layer 11 of the wiring substrate 10 is insulated. The layer 16 is formed, and then the connection pad 11a is exposed by forming a plurality of openings 16a in the insulating protective layer 16, and the conductive element 17 such as a solder ball is formed in the opening 16a of the insulating protective layer 16. This completes the package manufacturing process.

However, in such a package member, since the stacked semiconductor chips 121 and 122 are electrically connected to the circuit layer 11 by wire bonding, the thickness of the package in wire bonding depends on the height of the loop. As a result, the weight and size can not be achieved. Moreover, the semiconductor chips 121 and 122 need to be electrically connected by the bonding layer 13 by flip-chip connection on a chip scale. That is, the semiconductor chips 121 and 122 are first laminated in the foundry for electrical connection. Then, packaging is performed by a package maker, which complicates the manufacturing process and increases the manufacturing cost.

Also, in the method of improving the electrical performance and module performance in the stack, in order to further improve the performance, more stacks must be performed, which increases the complexity of the circuit layer 11 and increases the circuit layer. When it is necessary to increase the number of the 11 bonding pads 11b, and when it is intended to improve the circuit density and increase the number of the bonding pads 11b within a limited or fixed use area, the semiconductor chips 121 and 122 are formed. The circuit board to be mounted must achieve circuit miniaturization. However, there is a limit to the effect of reducing the circuit board area by circuit miniaturization, and the semiconductor chips 121 and 122 are directly stacked. When improving the electrical performance and module performance using the same method, the number of stacked chips is limited, so the purpose of effectively improving the electrical performance is achieved. Difficult to do.

Therefore, the density at which the multichip module is bonded to the multilayer wiring board is improved, the area where the semiconductor element is installed on the multilayer wiring board is reduced, and the semiconductor package size is reduced at the same time, and the semiconductor package manufacturing process is simplified. Reducing manufacturing costs is an important issue for the printed wiring board industry.
US Patent No. 6,798,049

  In order to solve the above-mentioned problems of the prior art, the present invention mainly provides a laminated structure of a semiconductor element embedded support substrate in which a modular structure can be formed by embedding a semiconductor element in a support substrate, and a manufacturing method thereof. The issue is to provide.

  In addition, the present invention provides a laminated structure of a semiconductor element embedded support substrate that can freely change the number of semiconductor elements as required, and can obtain a better degree of freedom of product combination, and a method for manufacturing the same. The issue is to provide.

  Another object of the present invention is to provide a laminated structure of a semiconductor element embedded support substrate and a method for manufacturing the same, which can reduce the size of the module by effectively using the space of the support substrate.

  It is another object of the present invention to provide a laminated structure of a semiconductor element embedded support substrate that can simplify the semiconductor package manufacturing process and reduce the manufacturing cost, and a manufacturing method thereof.

In order to solve the above problems, a manufacturing method of a laminated structure of a semiconductor device embedded support substrate to the present invention includes providing a first support substrate, the opening through the first support substrate at least one formed prepares a second supporting substrate, an opening through the second support substrate to form at least one first protection to the first surface of the supporting substrate to seal the opening of the first support substrate Forming a layer , forming a second protective layer on the surface of the second support substrate to seal the opening of the second support substrate, and forming at least one first semiconductor element in the opening of the first support substrate And installing in the first protective layer, and installing at least one second semiconductor element in the opening of the second support substrate and bonding to the second protective layer; A first protective layer and a second protective layer are formed on the second supporting substrate; A step of pressing a dielectric layer between non-surfaces and filling the openings of the first and second support substrates with the dielectric layer, thereby fixing the first and second semiconductor elements to the openings; And removing the second protective layer to form a stacked structure in which the first and second semiconductor elements are embedded.

The first and second support substrates may be either an insulating substrate or a wiring substrate having a circuit, and the first and second protective layers may be tapes.
The method for manufacturing a laminated structure of a semiconductor element embedded support substrate according to the present invention further includes at least one dielectric layer on both surfaces of the laminated structure, a circuit layer laminated on the dielectric layer, and a circuit. Forming first and second build-up structures each including a conductive structure formed in the dielectric layer so that the layer is electrically connected to the electrode pads of the first and second semiconductor elements; Forming a plurality of plated through holes penetrating the laminated structure and the first and second buildup structures and electrically connecting the plated through holes to the first and second buildup structures; Forming a first solder resist layer and a second solder resist layer on the outer surfaces of the first and second buildup structures, respectively.

By the manufacturing method of the laminated structure of the semiconductor element embedded support substrate, the stacked structure of the semiconductor element embedded support substrate according to the present invention can be formed. a first supporting substrate openings through the formed at least one, a second supporting substrate openings through the formed at least one, a plurality of electrode pads with is provided in an opening of the first support substrate At least one first semiconductor element that may have an active surface and an inactive surface opposite to the active surface, and an active surface that is provided in the opening of the second support substrate and includes a plurality of electrode pads. at least one second semiconductor device may have an active surface, it is sandwiched between the first and second supporting substrate, and filling the first and in the second opening of the support substrate Respectively first by the second semiconductor element includes a dielectric layer to be secured to the opening, the.

The laminated structure of the semiconductor element embedded support substrate according to the present invention is further formed on the outer surfaces of the first and second support substrates, respectively, and at least one dielectric layer and a circuit laminated on the dielectric layer. A first build-up structure and a second build-up structure including a layer and a conductive structure formed in the dielectric layer so that the circuit layer is electrically connected to the electrode pad of the semiconductor element; A plurality of for penetrating the second support substrate, the first and second build-up structures and the dielectric layer, thereby being electrically connected to the circuit layers of the first and second build-up structures; The plating through hole, and a first solder resist layer and a second solder resist layer formed on the outer surfaces of the first and second buildup structures, respectively, may be included.

  Compared with the prior art, the present invention embeds a semiconductor element in a supporting substrate, forms a protective layer on the surface of the supporting substrate and the active surface of the semiconductor element, and then on the surface of the supporting substrate where the protective layer is not formed. Since a modular structure is formed by crimping the dielectric layer between them, it is possible to reduce the size of the module by effectively using the space of the support substrate, and it can also be applied to memory chips In the stacked structure, it is possible to configure the required storage capacity by freely changing the combination as necessary, thereby simplifying the semiconductor package manufacturing process and reducing the manufacturing cost Become. Furthermore, in the present invention, a plurality of plating throughs for electrically connecting the first and second buildup structures on the surface of the support substrate and the first and second buildup structures on the surface of the support substrate. A hole may be formed, thereby forming a stacked structure of a semiconductor element embedded support substrate, and the stacked structure may be electrically connected to another conductive element or an external electronic device such as a printed wiring board. Is possible.

  Hereinafter, embodiments of the present invention will be described by way of specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention based on the contents described in this specification. In addition, the present invention can be implemented and applied by other different specific embodiments, and the contents described in the present specification can be applied to different viewpoints and applications without departing from the gist of the present invention. Various modifications and changes can be made based on the above.

Hereinafter, a method for manufacturing a laminated structure of a semiconductor element embedded support substrate according to the present invention will be described in detail with reference to FIGS.
As shown in FIG. 2-A, first, a first support substrate 21a and a second support substrate 21b are prepared, and at least one through-hole is provided in each of the first support substrate 21a and the second support substrate 21b. 211a and 211b, and by forming the first protective layer 22a and the second protective layer 22b on the surfaces of the first support substrate 21a and the second support substrate 21b, respectively, the first protective layer 22a and One end of the openings 211a and 211b is sealed by the second protective layer 22b. Then, at least one first semiconductor element 23a and at least one second semiconductor element 23b are installed in the openings 211a and 211b of the first and second support substrates, and the first semiconductor element 23a and the second semiconductor element The element 23b is bonded to the first and second protective layers 22a and 22b, respectively.

The first and second support substrates are insulating substrates or circuit boards having a circuit, and the first and second protective layers 22a and 22b are, for example, tapes. The second semiconductor elements 23a and 23b are joined to the openings 211a and 211b of the first and second support substrates 21a and 21b. The first and second semiconductor elements 23a and 23b have active surfaces 231a and 231b and non-active surfaces 232a and 232b, respectively, and a plurality of electrode pads 233a and 233b are formed on the active surfaces 231a and 231b, respectively. ing. The active surfaces 231a and 231b of the first and second semiconductor elements 23a and 23b are joined to the first and second protective layers 22a and 22b, respectively. The active surfaces 231a and 231b of the first and second semiconductor elements 23a and 23b are respectively protected.

As shown in FIG. 2-B, the surface of the first support substrate 21a where the first protective layer 22a is not formed and the surface of the second support substrate 21b where the second protective layer 22b is not formed. The dielectric layer 24 is pressed between them, and the substrate is pressed in the direction indicated by the arrow in the figure, so that a part of the dielectric layer 24 is press-fitted into the openings 211a and 211b of the first and second support substrates 21a and 21b. Thus, the first and second semiconductor elements 23a and 23b are fixed to the openings 211a and 211b, thereby forming the structure shown in FIG.

As shown in FIG. 2-D, the first and second protective layers 22a and 22b are then removed, thereby forming the laminated structure 2 in which the first and second semiconductor elements 23a and 23b are embedded.
As shown in FIG. 2-E, the first buildup structure 25a and the second buildup structure 25b may be formed on both surfaces of the laminated structure 2, and the first buildup structure 25a is at least 1
Two dielectric layers 251a, a circuit layer 252a stacked on the dielectric layer 251a, and the circuit layer 252a are formed on the dielectric layer 251a to be electrically connected to the electrode pads 233a of the first semiconductor element 23a. The second build-up structure 25b includes a dielectric layer 251b, a circuit layer 252b stacked on the dielectric layer 251b, and the circuit layer 252b includes the second semiconductor element 23b. A conductive structure 253b formed in the dielectric layer 251b to be electrically connected to the electrode pad 233b. At the same time, the circuit layers 252a and 252b are electrically connected by forming a plurality of plated through holes (PTH) 26 penetrating the laminated structure 2, the first buildup structure 25a, and the second buildup structure 25b. Let

In addition, it should be noted that the first and second build-up structures 25a and 25b are not limited to one layer as shown in the drawings, and can be multilayered according to actual electrical requirements. It is.
As shown in FIG. 2-F, the first buildup structure 25a and the second buildup structure 25b
A first solder resist layer 27a and a second solder resist layer 27b may be formed on the outer surface of the first solder resist layer 27a.

The laminated structure of the semiconductor element embedded support substrate according to the present invention is formed by the manufacturing method described above. As shown in FIG. 2-D, this laminated structure mainly includes a first support substrate 21a and a second support substrate 21b, in which at least one through-opening 211a and 211b are respectively formed, and a first and a second support substrate, respectively. Active surfaces 231a and 231b that are bonded to the openings 211a and 211b of the support substrate and on which a plurality of electrode pads 233a and 233b are formed, and may have at least one first inactive surface 232a and 232b facing each other. The semiconductor elements 23a, the second semiconductor elements 23b, and the openings 211a, 211b of the first and second support substrates 21a, 21b that are sandwiched between the first support substrate 21a and the second support substrate 21b. And a dielectric layer 24 for fixing the first and second semiconductor elements 23a and 23b to the openings 211a and 211b.

As shown in FIG. 2-E, the laminated structure of the semiconductor element embedded support substrate is further formed on the outer surfaces of the first support substrate 21a and the second support substrate 21b, respectively, and at least one dielectric layer 251a, 251b, circuit layers 252a and 252b stacked on the dielectric layer, and circuit layers 252a and 252b are electrically connected to the electrode pads 233a and 233b of the first and second semiconductor elements 23a and 23b. First buildup structure 25a and second buildup structure 25b including conductive structures 253a and 253b formed on body layers 251a and 251b, first and second support substrates 21a and 21b, first and second It is also possible to include a plurality of plated through holes 26 that penetrate through the build-up structures 25a, 25b and the dielectric layer 24, thereby electrically connecting the circuit layers 252a, 252b.

Further, as shown in FIG. 2-F, the laminated structure of the semiconductor element embedded support substrate according to the present invention is further provided with a first solder formed on the outer surfaces of the first and second buildup structures 25a and 25b, respectively. It is also possible to include a resist layer 27a and a second solder resist layer 27b.

  Compared with the prior art, in the laminated structure of the semiconductor element embedded support substrate and the method for manufacturing the same according to the present invention, a plurality of semiconductor elements are embedded in the first and second support substrates 21a and 21b. It is possible to increase the number of semiconductor elements to be joined, thereby increasing the storage capacity. The first and second semiconductor elements 23a and 23b are bonded in advance to the openings 211a and 211b of the first and second support substrates 21a and 21b, and then the surfaces of the first and second support substrates 21a and 21b. After the first and second protective layers 22a and 22b are formed on the active surfaces of the first and second semiconductor elements 23a and 23b, respectively, the first support substrate 21a and the second support substrate 21b are stacked. As a result, a modular structure is formed, which makes it possible to reduce the size of the module by effectively using the space of the support substrate, and also varies as necessary. By performing combinations and changes, it is possible to meet different usage requirements and to have better freedom of product combination. Compared with the prior art, the laminated structure of the semiconductor element embedded support substrate and the manufacturing method thereof according to the present invention can simplify the semiconductor package manufacturing process and reduce the manufacturing cost.

  The above embodiment is merely an example for explaining the principle and effect of the present invention, and does not limit the content of the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the above-described embodiments without departing from the scope of the present invention. It goes without saying that such modifications and changes are included in the claims of the present invention.

FIG. 6 is a cross-sectional view of US Pat. No. 6,798,049. It is FIG. 1 of the flowchart of the manufacturing method of the laminated structure of the semiconductor element embedded support substrate concerning this invention. It is FIG. 2 of the flowchart of the manufacturing method of the laminated structure of the semiconductor element embedded support substrate concerning this invention. It is FIG. 3 of the flowchart of the manufacturing method of the laminated structure of the semiconductor element embedded support substrate concerning this invention. FIG. 6 is a fourth diagram of a flow chart of a method for manufacturing a laminated structure of a semiconductor element embedded support substrate according to the present invention. It is FIG. 5 of the flowchart of the manufacturing method of the laminated structure of the semiconductor element embedded support substrate concerning this invention. It is FIG. 6 of the flowchart of the manufacturing method of the laminated structure of the semiconductor element embedded support substrate concerning this invention.

Explanation of symbols

10 Wiring board
102, 16a, 211a, 211b Open
11, 252a, 252b Circuit layer
11a connection pad
11b Bonding pad
121, 122 semiconductor chip
13 Bonding layer
14 Conductive equipment
15 Sealing resin
16 Insulating protective layer
17 Conductive element
21a First support substrate
21b Second support substrate
22a First protective layer
22b Second protective layer
231a, 231b Active surface
232a, 232b inactive surface
233a, 233b electrode pad
23a First semiconductor element
23b Second semiconductor element
24, 251a, 251b Dielectric layer
253a, 253b Conductive structure
25a First build-up structure
25b Second build-up structure
26 Plating through hole
27a First solder resist layer
27b Second solder resist layer
2 Laminated structure

Claims (13)

A manufacturing method of a laminated structure of a semiconductor element embedded support substrate,
A first support substrate is prepared, at least one opening penetrating the first support substrate is formed , a second support substrate is prepared, and at least one opening penetrating the second support substrate is formed. and, wherein the first surface of the supporting substrate to seal the opening of the first support substrate to form a first protective layer, the second to seal the opening of the second support substrate A second protective layer is formed on the surface of the support substrate, and at least one first semiconductor element is placed in the opening of the first support substrate and bonded to the first protective layer, and at least one first Installing the second semiconductor element in the opening of the second support substrate and bonding the second semiconductor element to the second protective layer ;
A dielectric layer is pressure-bonded between surfaces of the first and second support substrates on which the first and second protective layers are not formed, and the dielectric is formed in the openings of the first and second support substrates. Filling the layer, thereby fixing the first and second semiconductor elements to the opening;
Removing the first and second protective layers to form a stacked structure in which the first and second semiconductor elements are embedded;
A method for manufacturing a laminated structure of a semiconductor element embedded support substrate, comprising:   2. The method for manufacturing a laminated structure of a semiconductor element embedded support substrate according to claim 1, wherein the first and second support substrates are any one of an insulating substrate and a wiring substrate having a circuit.   2. The method for manufacturing a laminated structure of a semiconductor element embedded support substrate according to claim 1, wherein the first and second protective layers are made of tape.   2. The semiconductor according to claim 1, wherein each of the first and second semiconductor elements has an active surface and an inactive surface opposite to the active surface, and a plurality of electrode pads are formed on each of the active surfaces. A method for manufacturing a laminated structure of an element-embedded support substrate.   At least one dielectric layer, a circuit layer laminated on the dielectric layer, and the circuit layer are electrically connected to electrode pads of the first and second semiconductor elements on both surfaces of the laminated structure. 5. The semiconductor device embedded support substrate according to claim 4, further comprising: forming a first build-up structure and a second build-up structure each including a conductive structure formed on the dielectric layer. The manufacturing method of the laminated structure.   Forming a plurality of plated through holes penetrating the laminated structure and the first and second buildup structures, and electrically connecting the plated through holes to the first and second buildup structures; 6. The method of manufacturing a laminated structure of a semiconductor element embedded support substrate according to claim 5, further comprising:   6. The laminated structure of a semiconductor element embedded support substrate according to claim 5, further comprising a step of forming first and second solder resist layers on outer surfaces of the first and second buildup structures, respectively. Production method. A laminated structure of a semiconductor element embedded support substrate,
A first support substrate in which at least one opening is formed ;
A second support substrate formed with at least one opening therethrough ;
At least one first semiconductor element provided in an opening of the first support substrate ;
At least one second semiconductor element provided in the opening of the second support substrate ;
A dielectric sandwiched between the first and second support substrates and filled in the openings of the first and second support substrates to fix the first and second semiconductor elements to the openings. Body layers,
A laminated structure of a semiconductor element embedded support substrate, comprising:   9. The laminated structure of a semiconductor element embedded support substrate according to claim 8, wherein the first and second support substrates are any one of an insulating substrate and a wiring substrate having a circuit.   The first and second semiconductor elements each have an active surface and an inactive surface opposite to the active surface, and a plurality of electrode pads are formed on each of the active surfaces. Laminated structure of semiconductor element embedded support substrate. At least one dielectric layer formed on the outer surface of each of the first and second support substrates, a circuit layer laminated on the dielectric layer, and the circuit layer comprising the first and second semiconductor elements And at least one first build-up structure and second build-up structure each including a conductive structure formed in the dielectric layer to be electrically connected to the electrode pad. 11. A laminated structure of a semiconductor element embedded support substrate according to claim 10.   The first and second support substrates, the first and second buildup structures, and the dielectric layer are penetrated, thereby electrically connecting the circuit layers of the first and second buildup structures. 12. The laminated structure of a semiconductor element embedded support substrate according to claim 11, further comprising a plurality of plated through holes to be connected to the semiconductor device.   The semiconductor device embedded support substrate according to claim 11, further comprising a first solder resist layer and a second solder resist layer formed on outer surfaces of the first and second buildup structures, respectively. Laminated structure.

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