JP5085159B2 - Isolation circuit - Google Patents

Description

  The present invention relates to an isolation circuit using a transformer that outputs a pulse signal input to a primary winding from a secondary winding.

  In general, a gate drive circuit that drives the gate of an FET with a high-frequency pulse signal is known, and this type of gate drive circuit includes an isolation circuit that electrically isolates the FET signal side from the pulse signal application side. There are many cases where it is used. Various types such as a type using a photocoupler and a type using a transformer are known as this type of isolation circuit, but each has advantages and disadvantages. In particular, the type using a transformer has a function of outputting a pulse signal input to the primary winding from the secondary winding by using a transformer having a primary winding and a secondary winding. Therefore, there is a problem that the circuit cannot be downsized and the operation speed cannot be increased.

On the other hand, as an isolation circuit that solves this problem, a gate drive device (isolation circuit) disclosed in Patent Document 1 is conventionally known. This gate drive device is a gate drive device that drives the gate of a MOSFET, receives and differentiates a pulse waveform having a variable width, and outputs a differential waveform that outputs a rising differential waveform and a falling differential waveform. A voltage that is connected to the circuit and the gate and holds the voltage of the rising differential waveform with respect to the input capacitance of the gate, and that holds the gate based on the rising differential waveform. Is provided with a discharge circuit for discharging the battery.
JP 2006-141177 A

  However, the above-described conventional isolation circuit (gate driving device) has the following problems.

  First, since differentiation is performed using the inductance of the transformer, a vibration waveform Sdw due to resonance is generated in the actual differential waveform Sd as shown by a virtual line in FIG. Therefore, when the unnecessary reverse voltage Vn of the vibration waveform Sdw is applied to the gate of the FET, the gate voltage fluctuates in an unstable manner, and the malfunction of the FET is likely to occur. There is.

  Secondly, the input capacitance at the gate of the FET is charged by the differential waveform Sd, and this charging is performed mainly in the vicinity of the peak voltage Vp having the top edge of the differential waveform Sd. However, the time before and after the peak voltage Vp is extremely short, and voltage drop due to transformer inductance and line resistance is taken into account, so that the gate voltage Vg of the FET tends to be low as shown by a virtual line in FIG. . Therefore, in order to increase the gate voltage Vg, it is necessary to increase the number of turns of the secondary winding of the transformer. This causes an increase in power loss, a decrease in efficiency based on this, and an increase in manufacturing cost.

  The object of the present invention is to provide an isolation circuit that solves the problems in the background art.

  In order to solve the above-described problems, the present invention includes a transformer 2 having at least a primary winding 2f and a secondary winding 2r, and receives a pulse signal Ps input to a primary circuit Cf including the primary winding 2f as a secondary winding. When the isolation circuit 1 that outputs from the secondary circuit Cr including 2r is configured, the transformer 2 having the primary winding 2f formed by the first winding 2fa and the second winding 2fb is provided, and the primary circuit Cf includes a pulse The pulse of the first short pulse signal Sa having a pulse width Tsa shorter than the pulse width Tp of the pulse signal Ps and the falling Psb of the pulse signal Ps in synchronization with the rising Psa of the signal Ps and the pulse signal Ps By generating a second short pulse signal Sb having a pulse width Tsb shorter than the width Tp, the first short pulse signal Sa is input to the first winding 2fa, and The short pulse generating means 3 for inputting the second short pulse signal Sb to the second winding 2fb, the reverse voltage Vpw of the energy stored in the transformer 2 by the first short pulse signal Sa is discharged, and the second short pulse signal Sb Discharging means 4 for discharging the reverse voltage Vnw of the stored energy of the transformer 2 due to the above is provided, and charging means 5 for charging the secondary current Iop flowing in the secondary winding 2r is provided in the secondary circuit Cr. Features.

  In this case, according to a preferred aspect of the invention, the short pulse generating means 3 includes a first switch circuit 11 connected to the primary winding 2f and a first variable circuit 12 for controlling ON / OFF of the first switch circuit 11. It can be prepared. Further, the discharging means 4 can be configured to include a second switch circuit 13 connected to the primary winding 2f and a second control circuit 14 for ON / OFF control of the second switch circuit 13. At this time, the discharging means 4 applies a reverse voltage component of the stored energy of the transformer 2 from the second winding 2fb to the first short pulse signal Sa over a predetermined period after the first short pulse signal Sa is applied to the first winding 2fa. Vpw is discharged and the second short pulse signal Sb is applied to the second winding 2fb, and the reverse voltage Vnw of the stored energy of the transformer 2 by the second short pulse signal Sb from the first winding 2fa over a predetermined period. A discharge circuit 15 for discharging can be used. Further, the charging means 5 can use a capacitor 16 connected to the secondary circuit Cr (and / or a floating capacitance generated at the gate 17g of the FET 17 connected to the secondary circuit Cr).

  According to the isolation circuit 1 according to the present invention having such a configuration, the following remarkable effects can be obtained.

  (1) The first short pulse signal Sa and the second short pulse signal Sb are used while using the first short pulse signal Sa and the second short pulse signal Sb having pulse widths Tsa and Tsb shorter than the pulse width Tp of the pulse signal Ps. Since the reverse voltage components Vpw and Vnw of the stored energy of the transformer 2 are discharged by the secondary circuit Cr, unnecessary reverse voltage components Vpw and Vnw are output from the secondary circuit Cr, thereby preventing malfunctions and causing stable operation. And reliability can be improved.

  (2) Synchronized with the first short pulse signal Sa having a pulse width Tsa shorter than the pulse width Tp of the pulse signal Ps and in synchronization with the rising Psa of the pulse signal Ps, and with the falling Psb of the pulse signal Ps Since the second short pulse signal Sb having a pulse width Tsb shorter than the pulse width Tp of the signal Ps is input to the primary winding 2f, the output voltage Vo of the secondary circuit Cr can be increased. As a result, the number of turns of the secondary winding 2r can be reduced. For example, the power loss can be reduced, the efficiency can be increased, and the manufacturing cost can be reduced.

  (3) The primary winding 2f is constituted by the first winding 2fa and the second winding 2fb, the first short pulse signal Sa is applied to the first winding 2fa, and the second short 2fb is applied to the second winding 2fb. Since the pulse signal Sb is applied, the use of the transformer 2 itself can facilitate the implementation of the isolation circuit 1 and ensure the operation.

  (4) According to a preferred embodiment, the short pulse generating means 3 is constituted by the first switch circuit 11 connected to the primary winding 2f and the first control circuit 12 for ON / OFF control of the first switch circuit 11. Since it can be implemented by a combination of a switch and a simple circuit, it can contribute to cost reduction and downsizing.

  (5) According to a preferred embodiment, if the discharge means 4 is constituted by the second switch circuit 13 connected to the primary winding 2f and the second control circuit 14 for ON / OFF control of the second switch circuit 13, the switch Can be implemented by a combination of a simple circuit and can contribute to cost reduction and downsizing.

  (6) According to a preferred aspect, the discharging means 4 causes the transformer 2 to accumulate by the first short pulse signal Sa from the second winding 2fb for a predetermined period after the first short pulse signal Sa is applied to the first winding 2fa. The reverse voltage Vpw of the energy is discharged and the second short pulse signal Sb is applied to the second winding 2fb, and then the accumulated energy of the transformer 2 by the second short pulse signal Sb from the first winding 2fa is given for a predetermined period. If the discharge circuit 15 is configured to discharge the reverse voltage Vnw, the energy stored in the transformer 2 can be reliably discharged by securing a sufficient discharge time.

  (7) According to a preferred embodiment, the charging means 5 may be the charging means 5 by using the capacitor 16 connected to the secondary circuit Cr and / or the floating capacitance generated at the gate 17g of the FET 17 connected to the secondary circuit Cr. 5 can be configured easily and at low cost.

  Next, the best embodiment according to the present invention will be given and described in detail with reference to the drawings.

  First, the basic principle of the isolation circuit 1 according to the present invention will be described with reference to FIGS.

  FIG. 3 shows the principle configuration of the isolation circuit 1. In the figure, reference numeral 2 denotes a transformer having a primary winding 2f and a secondary winding 2r. The primary winding 2f of the transformer 2 has a first winding 2fa and a second winding 2fb by providing an intermediate tap 2m. It consists of. In this case, the number of turns of the first winding 2fa and the second winding 2fb is not necessarily set to be the same. Thus, if the primary winding 2f is constituted by the first winding 2fa and the second winding 2fb, a first short pulse signal Sa described later is applied to the first winding 2fa, and the second winding 2fb. Since the second short pulse signal Sb, which will be described later, can be provided, there is an advantage that the use of the transformer 2 itself can facilitate the implementation of the isolation circuit 1 and ensure the operation. Reference numerals 21p and 21n denote input terminals to which direct current is input. 21p is a positive side and 21n is a negative side.

  On the other hand, a primary circuit Cf including a primary winding 2f is provided on the primary side of the transformer 2, and a secondary circuit Cr including a secondary winding 2r is provided on the secondary side of the transformer 2. The primary circuit Cf includes a first switch circuit 11 on the short pulse generating means 3 side connected to the primary winding 2f and a second switch circuit 13 on the discharge means 4 side connected to the primary winding 2f. The first switch circuit 11 includes a first switch unit 11a and a second switch unit 11b. In this case, the winding end terminal of the primary winding 2f (first winding 2fa) is connected to the input terminal 21p via the first switch portion 11a and the winding start of the primary winding 2f (second winding 2fb). The terminal is connected to the input terminal 21p via the second switch portion 11b. The second switch circuit 13 includes a first diode 22a, a second diode 22b, a third switch portion 13a, and a fourth switch portion 13b. In this case, the winding end terminal of the primary winding 2f (first winding 2fa) is connected to the intermediate tap 2m via a series circuit of the forward first diode 22a and the third switch portion 13a, and the primary winding. The winding start terminal of 2f (second winding 2fb) is connected to the intermediate tap 2m via a series circuit of the second diode 22b in the forward direction and the fourth switch portion 13b. The intermediate tap 2m of the transformer 2 is connected to the negative input terminal 21n.

  On the other hand, the winding end terminal of the secondary winding 2r constituting the secondary circuit Cr is connected to one (positive side) output terminal 24p via the forward diode 23, and the winding start of the secondary winding 2r. The terminal is connected to the other (negative side) output terminal 24n, and the capacitor 16 constituting the charging means 5 is connected between the output terminals 24p and 24n.

  The main operation of the isolation circuit 1 having such a principle configuration is as follows. Assume that a pulse signal Ps having a voltage Vi and a pulse width Tp is input to the primary circuit Cf. In the isolation circuit 1, the short pulse generation means 3 (not shown in FIG. 3) synchronizes with the rising Psa of the pulse signal Ps and has a pulse width Tsa that is sufficiently shorter than the pulse width Tp of the pulse signal Ps. A second short pulse signal Sb having a pulse width Tsb shorter than the pulse width Tp of the pulse signal Ps is generated in synchronization with the one short pulse signal Sa and the falling edge Psb of the pulse signal Ps. FIG. 4 shows the pulse signal Ps and the first short pulse signal Sa.

  Then, the first switch portion 11a is turned on by the first short pulse signal Sa, and the fourth switch portion 13b is turned on in synchronization with the rising Psa of the pulse signal Ps. That is, the first switch part 11a and the fourth switch part 13b are simultaneously turned on. In addition, the 2nd switch part 11b and the 3rd switch part 13a are OFF. The first switch portion 11a is turned off after the time corresponding to the pulse width Tsa has elapsed. As shown in FIG. 3, when the first switch section 11a is turned on, the primary current Ica based on the first short pulse signal Sa flows through the first switch section 11a and the first winding 2fa, and the two based on this. The secondary current Io flows through the secondary winding 2r. Thereby, the capacitor 16 is charged by the secondary current Io, and the terminal voltage of the capacitor 16, that is, the output voltage between the output terminals 24p and 24n is held as Vo. This output voltage Vo is shown in FIG. This output voltage Vo is maintained (held) until discharge is performed by the secondary-side discharge circuit 32 (not shown in FIG. 3).

  By the way, the first short pulse signal Sa has a rectangular waveform, and does not have an upper-pointed shape like the differential waveform Sd shown by a virtual line in FIG. 4 as a conventional example. That is, since the first short pulse signal Sa has a constant pulse width Tsa (area), the capacitor 16 connected to the secondary circuit Cr is charged with sufficient charge, and a high output voltage Vo can be obtained.

  On the other hand, even if the first switch portion 11a is turned off, the fourth switch portion 13b that is turned on simultaneously with the first switch portion 11a continues to be turned on. Therefore, when the first switch unit 11a is turned off and the first short pulse signal Sa is not applied, the reverse voltage Vpw of the energy stored in the transformer 2 by the first short pulse signal Sa is discharged from the transformer 2. That is, as shown in FIG. 3, the discharge current Ira flows from the second winding 2fb through the second diode 22b and the fourth switch portion 13b.

  By the way, if the discharge current Ira does not flow, as shown in FIG. 6, a vibration waveform by the first short pulse signal Sa is generated in the terminal voltage Vop of the secondary winding 2r. However, by causing the discharge current Ira to flow, the reverse voltage Vpw of the stored energy of the transformer 2 by the first short pulse signal Sa is discharged from the transformer 2, and no oscillation waveform is generated like the terminal voltage Vop shown in FIG. In this case, the second winding 2fb is substantially short-circuited by turning on the fourth switch portion 13b, but the accumulated energy of the reverse voltage Vpw based on the first short pulse signal Sa is small, and the line resistance and It is consumed by the inductance of the transformer 2. Therefore, actually, as shown in FIG. 5, a slight discharge voltage Vrp is generated, but it is not so large as to cause a malfunction (voltage). In FIG. 6, Von represents the terminal voltage of the secondary winding 2r based on the second short pulse signal Sb, and Vnw represents the inverse voltage of the stored energy of the transformer 2 based on the second short pulse signal Sb.

  The behavior (operation) when the first short pulse signal Sa is applied to the primary circuit Cf has been described above, but the positive side and the negative side are also inverted when the second short pulse signal Sb is applied to the primary circuit Cf. Except for this point, the behavior (operation) at that time is the same as the behavior (operation) when the first short pulse signal Sa is applied to the primary circuit Cf.

  Next, a circuit example of the isolation circuit 1 according to the present embodiment will be described with reference to FIGS. 1 and 2.

  First, the configuration of the isolation circuit 1 according to the circuit example will be described with reference to FIG. FIG. 1 includes the principle configuration shown in FIG. Therefore, in FIG. 1, the same parts as those in FIG. 3 are denoted by the same reference numerals to clarify the configuration, and detailed description thereof is omitted. The illustrated isolation circuit 1 is used in a gate drive circuit M that drives the gate 17g of the FET 17 by a high-frequency pulse signal Ps.

  In FIG. 1, 51 is a main control circuit, and the main control circuit 51 includes a second control circuit 14. The main control circuit 51 is connected to input terminals 21p and 21n to which direct current is input. The main control circuit 51 has a function of generating a pulse signal Ps shown in FIG. 2C, and this pulse signal Ps is a pulse signal that is input / output by the isolation circuit 1 according to the present embodiment. Become. The frequency of the pulse signal Ps is normally assumed to be several tens to several hundreds [kHz]. The second control circuit 14 included in the main control circuit 51 also outputs a non-inverted output unit 14p that outputs a pulse signal Ps and an inverted pulse signal Psn that is obtained by inverting the pulse signal Ps and that is shown in FIG. An output unit 14n is provided. Then, the fourth switch portion 13b is ON / OFF controlled by the pulse signal Ps, and the third switch portion 13a is ON / OFF controlled by the inverted pulse signal Psn. In addition, switching elements, such as FET, can be used for the 3rd switch part 13a and the 4th switch part 13b.

  Accordingly, the third switch portion 13a and the fourth switch portion 13b constitute a second switch circuit 13 connected to the primary winding 2f, and the second switch circuit 13 and the second control circuit 14 are connected to the discharge circuit 15 ( Discharging means 4) is configured. If the discharge circuit 15 (discharge means 4) configured as described above is used, the discharge circuit 15 (discharge means 4) can be implemented by a combination of a switch and a simple circuit.

  Reference numeral 52 denotes a sub-control circuit that constitutes the first control circuit 12. The first control circuit 12 is connected to input terminals 21p and 21n. The first control circuit 12 includes input units 12pi and 12ni. The input unit 12pi is connected to the non-inverting output unit 14p of the second control circuit 14, and the input unit 12ni is an inverting output of the second control circuit 14. Connected to the unit 14n. The first control circuit 12 generates the first short pulse signal Sa shown in FIG. 2 (a) in synchronization with the rising Psa of the pulse signal Ps and having a pulse width Tsa sufficiently shorter than the pulse width Tp of the pulse signal Ps. And a function of generating the second short pulse signal Sb shown in FIG. 2B having a pulse width Tsb that is synchronized with the falling Psb of the pulse signal Ps and sufficiently shorter than the pulse width Tp of the pulse signal Ps. Prepare. The first control circuit 12 includes a pre-pulse output unit 12po that outputs the generated first short pulse signal Sa and a post-pulse output unit 12no that outputs the generated second short pulse signal Sb. The first switch unit 11a is ON / OFF controlled by the short pulse signal Sa, and the second switch unit 11b is ON / OFF controlled by the second short pulse signal Sb. In addition, switching elements, such as FET, can be used for the 1st switch part 11a and the 2nd switch part 11b.

  Therefore, the first switch unit 11a and the second switch unit 11b constitute the first switch circuit 11 connected to the primary winding 2f, and the first switch circuit 11 and the first control circuit 12 The short pulse generating means 3 is configured to generate the signal Sa and the second short pulse signal Sb and input them to the primary winding 2f. If the short pulse generating means 3 configured in this way is used, the short pulse generating means 3 can be implemented by a combination of a switch and a simple circuit.

  On the other hand, the winding end terminal of the secondary winding 2r of the transformer 2 is connected to one (positive side) output terminal 24p via a forward diode 23, and the winding start terminal of the secondary winding 2r is reverse. To the other (negative side) output terminal 24n. The capacitor 16 constituting the charging means 5 and the FET 27 constituting the switch means are connected between the output terminals 24p and 24n, and the forward terminal of the secondary winding 2r is connected in the forward direction from the output terminal 24n. A diode 26 is connected. In this case, the diode 23 and the capacitor 16 constitute a holding circuit 31 that holds the output voltage Vo, and the diodes 25 and 26 and the FET 27 constitute a secondary discharge circuit 32. When the second short pulse signal Sb is applied, the secondary side discharge circuit 32 generates a bias voltage by the diodes 25 and 26, and turns on the FET 27 by the bias voltage. As a result, both ends of the capacitor 16 are short-circuited, and the charge charged (held) in the capacitor 16 is discharged. Thus, if the capacitor 16 connected between the output terminals 24p and 24n is used as the charging unit 5, there is an advantage that the charging unit 5 can be configured easily and at low cost. Since the isolation circuit 1 shown in the figure connects the FET 17 to the output terminals 24p and 24n, the stray capacitance generated at the gate 17g of the FET 17 can also be used as the charging means 5.

  Next, the operation of the isolation circuit 1 according to the present embodiment will be described with reference to FIG.

  First, the second control circuit 14 generates a pulse signal Ps shown in FIG. The pulse signal Ps has a pulse with a voltage Vi and a pulse width Tp (duty ratio: 50 [%]), and the frequency is assumed to be several tens to several hundreds [kHz]. Psa indicates the rise of the pulse signal Ps, and Psb indicates the fall of the pulse signal Ps.

  Now, it is assumed that the pulse signal Ps is output from the non-inverting output unit 14p of the second control circuit 14, and this pulse signal Ps is at the timing of the rising Psa. As a result, the first control circuit 12 generates the first short pulse signal Sa shown in FIG. Then, the first switch section 11a is turned on by the pulse width Tsa by the first short pulse signal Sa. Further, the fourth switch portion 13b is turned ON for the pulse width Tp shown in FIG. During the ON period of the first switch unit 11a, the primary current Ica flows through the first winding 2fa and the secondary current Iop in the positive direction flows through the secondary winding 2r. As a result, a positive secondary voltage Vop shown in FIG. 2E is induced in the secondary winding 2r. As a result, the capacitor 16 is charged by the secondary current Iop, the terminal voltage of the capacitor 16 becomes Vo, and this Vo is held as an output voltage. FIG. 2F shows the output voltage Vo.

  On the other hand, with the elapse of the ON period of the first switch unit 11a, the first switch unit 11a is turned off and only the fourth switch unit 13b is turned on. Thereby, the discharge current Ira flows from the second winding 2fb. That is, the reverse voltage Vpw (negative side) of the energy stored in the transformer 2 by the first short pulse signal Sa is discharged from the second winding 2fb. The period during which this discharge is allowed is a period corresponding to the pulse width Tp. In this case, as described above, a slight discharge voltage Vrp (see FIG. 2E) is generated, but it is not so large as to cause a malfunction (voltage). In this way, if the reverse voltage Vpw of the stored energy is discharged from the second winding 2fb for a predetermined period corresponding to the pulse width Tp after the first short pulse signal Sa is applied to the first winding 2fa, the transformer There is an advantage that the stored energy stored in 2 can be reliably discharged.

  Further, when the pulse signal Ps output from the non-inverting output unit 14p of the second control circuit 14 reaches the falling Psb, the rising Psa of the inverted pulse signal Psn output from the inverting output unit 14n is given to the first control circuit 12. The As a result, the first control circuit 12 generates the second short pulse signal Sb shown in FIG. Then, the second switch section 11b is turned ON by the pulse width Tsb by the second short pulse signal Sb. Further, the third switch section 13a is turned on for the pulse width Tp shown in FIG. During the ON period of the second switch portion 11b, the primary current Icb flows through the second winding 2fb and the secondary current Ion in the negative direction flows through the secondary winding 2r. As a result, a negative secondary voltage Von shown in FIG. 2E is induced in the secondary winding 2r, and a bias voltage is generated by the diodes 25 and 26. Therefore, the FET 27 is turned on by this bias voltage. . As a result, both ends of the capacitor 16 are short-circuited, and the charge charged (held) in the capacitor 16 is discharged. That is, the terminal voltage (output voltage Vo) of the capacitor 16 becomes zero level (see FIG. 2F).

  On the other hand, with the passage of the ON period of the second switch unit 11b, the second switch unit 11b is turned off and only the third switch unit 13a is turned on. Thereby, the discharge current Irb flows from the first winding 2fa. That is, the reverse voltage Vnw (positive side) of the energy stored in the transformer 2 by the second short pulse signal Sb is discharged from the first winding 2fa. The period during which this discharge is allowed is a period corresponding to the pulse width Tp. In this case, as described above, a slight discharge voltage Vrn (see FIG. 2E) is generated, but it is not so large as to cause a malfunction (voltage). In this way, if the reverse voltage Vnw of the stored energy is discharged from the first winding 2fa for a predetermined period corresponding to the pulse width Tp after the second short pulse signal Sb is applied to the second winding 2fb, the transformer There is an advantage that the stored energy stored in 2 can be reliably discharged. Thereafter, the same operation (cycle) is repeated.

  Therefore, according to the isolation circuit 1 according to the present embodiment, the first short pulse signal Sa having a pulse width Tsa that is synchronized with the rising Psa of the pulse signal Ps and shorter than the pulse width Tp of the pulse signal Ps. And the second short pulse signal Sb having a pulse width Tsb shorter than the pulse width Tp of the pulse signal Ps in synchronization with the falling Psb of the pulse signal Ps is input to the primary winding 2f. The output voltage Vo from the line 2r can be increased. As a result, the number of turns of the secondary winding 2r can be reduced. For example, the power loss can be reduced, the efficiency can be increased, and the manufacturing cost can be reduced. Further, the first short pulse signal Sa and the second short pulse signal Sb having the pulse widths Tsa and Tsb shorter than the pulse width Tp of the pulse signal Ps are used, and the first short pulse signal Sa and the second short pulse signal Sb are used. Since the reverse voltage components Vpw and Vnw of the stored energy of the transformer 2 are discharged, it is possible to avoid a malfunction in which the unnecessary reverse voltage components Vpw and Vnw are output from the secondary circuit Cr, thereby causing malfunction. And can improve the reliability.

  FIG. 7 shows a modified embodiment of the isolation circuit 1. In particular, the isolation circuit 1 shown in FIG. 7 is obtained by changing the secondary circuit Cr provided on the secondary side of the transformer 2. That is, the secondary winding 2r of the transformer 2 is configured by the original secondary winding 2ro and the auxiliary winding 2rs by providing an intermediate tap 2rm. The auxiliary winding 2rs, the diode 41, the resistor 42, and the transistor 43 constitute a secondary discharge circuit 44. The secondary side discharge circuit 44 can exhibit the same function as the secondary side discharge circuit 32 constituted by the diodes 25 and 26 and the FET 27 shown in FIG. In FIG. 7, the same components as those in FIG.

  Although the best embodiment (modified embodiment) has been described in detail above, the present invention is not limited to such an embodiment, and detailed circuit configuration, shape, parts, quantity, numerical value, and control method In this manner, any change, addition, or deletion can be made without departing from the spirit of the present invention.

  For example, the case where the first winding 2fa and the second winding 2fb are configured by providing the primary winding 2f of the transformer 2 with the intermediate tap 2m is shown, but the first winding 2fa and the second winding 2fb are You may comprise by each independent separate winding. Further, although an example in which the pulse signal Ps is generated by the main control circuit 51 has been described, the pulse signal Ps may be input from a separate external circuit. Furthermore, the predetermined period during which the stored energy is discharged in the discharge means 4 corresponds to the pulse width Tp from when the first short pulse signal Sa is applied to the first winding 2fa to when the second short pulse signal Sb is applied. The period or period corresponding to the pulse width Tp from when the second short pulse signal Sb is applied to the second winding 2fb until the first short pulse signal Sa is applied is shown. Can be set to length. On the other hand, the capacitor 16 is shown as the charging means 5, but when the FET 17 is connected to the output terminals 24p and 24n, the floating capacitance generated at the gate 17g of the FET 17 may be used, or both of them may be used. May be used. In addition, although the case where it used for the gate drive circuit M of FET as the isolation circuit 1 was shown, it can utilize for the various circuits and various apparatuses which require the same isolation function.

A circuit diagram of an isolation circuit according to the best embodiment of the present invention, Timing chart of signals in each part of the isolation circuit, The principle block diagram for demonstrating the basic principle (main operation | movement) of the isolation circuit which concerns on this invention, Signal timing chart for explaining the basic principle of the isolation circuit, A timing chart showing actual signals for explaining the basic principle of the isolation circuit; A timing chart showing actual signals for explaining the basic principle of the isolation circuit; A partial circuit diagram of an isolation circuit according to a modified embodiment of the present invention,

Explanation of symbols

  1: isolation circuit, 2: transformer, 2f: primary winding, 2fa: first winding, 2fb: second winding, 2r: secondary winding, 3: short pulse generating means, 4: discharging means, 5 : Charging means, 11: first switch circuit, 12: first control circuit, 13: second switch circuit, 14: second control circuit, 15: discharge circuit, 16: capacitor, 17: FET, 17g: gate, Ps : Pulse signal, Psa: rise of pulse signal, Psb: fall of pulse signal, Sa: first short pulse signal, Sb: second short pulse signal, Tp: pulse width of pulse signal (predetermined period), Tsa: first Pulse width of one short pulse signal, Tsb: Pulse width of second short pulse signal, Vpw: reverse voltage, Vnw: reverse voltage

Claims (5)

  An isolation circuit comprising a transformer having at least a primary winding and a secondary winding, and outputting a pulse signal input to a primary circuit including the primary winding from a secondary circuit including the secondary winding. A first short pulse having a transformer having a primary winding constituted by a line and a second winding, the primary circuit having a pulse width that is synchronized with a rise of the pulse signal and shorter than a pulse width of the pulse signal. Generating the second short pulse signal in synchronization with the signal and the falling edge of the pulse signal and having a pulse width shorter than the pulse width of the pulse signal, thereby causing the first short pulse signal to pass through the first winding. Short pulse generating means for inputting the second short pulse signal to the second winding, and a reverse voltage component of the stored energy of the transformer by the first short pulse signal. Charging means for charging and discharging a secondary current flowing through the secondary winding to the secondary circuit, and discharging means for discharging a reverse voltage of the stored energy of the transformer by the second short pulse signal An isolation circuit comprising:   2. The isolation circuit according to claim 1, wherein the short pulse generating means includes a first switch circuit connected to the primary winding and a first control circuit for ON / OFF controlling the first switch circuit. .   2. The isolation circuit according to claim 1, wherein the discharging means includes a second switch circuit connected to the primary winding and a second control circuit for ON / OFF controlling the second switch circuit.   The discharging means discharges a reverse voltage component of the accumulated energy of the transformer by the first short pulse signal from the second winding for a predetermined period after the first short pulse signal is applied to the first winding. And a discharge circuit for discharging a reverse voltage of the accumulated energy of the transformer by the second short pulse signal from the first winding over a predetermined period after the second short pulse signal is applied to the second winding. The isolation circuit according to claim 3, wherein the isolation circuit is provided.   2. The isolation circuit according to claim 1, wherein the charging means is a capacitor connected to the secondary circuit and / or a floating capacitance generated at a gate of the FET connected to the secondary circuit.

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