JP5057668B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device using a laser irradiation apparatus for irradiating a workpiece with laser light. Specifically, the present invention relates to a semiconductor device having a circuit composed of a field effect transistor (hereinafter referred to as FET). For example, parts include large-scale integrated circuits (LSIs), electro-optical devices represented by liquid crystal display panels, light-emitting display devices having organic light-emitting elements, sensor devices such as line sensors, and memory devices such as SRAM and DRAM. It is related with the electronic equipment carried as.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, the miniaturization and high integration of LSIs are becoming more and more advanced. For example, the gate length of a MOS transistor formed on a semiconductor substrate is being reduced to a submicron level. If the MOS transistor is simply miniaturized, the effective channel length is shortened, a short channel effect is generated between the source and the drain, and the threshold voltage of the MOS transistor is lowered. In addition, due to the short channel effect, frequent punch-throughs, an increase in leakage current, and the like become prominent.

In order to prevent the short channel effect, an LDD structure is employed, or a structure in which the junction depth of the diffusion layer formed in the transistor is reduced is employed. The structure in which the junction depth of the diffusion layer is shallow is called an ultra-shallow junction. Note that the ultra-shallow junction is also called an extension.

  Annealing techniques for activating doped impurities are being studied together with techniques for doping impurities in a desired region and depth.

As one of such conventional annealing techniques, the RTA method in which the entire semiconductor substrate to which impurities are added is heated to about 1000 ° C. using an infrared lamp or the like is known and widely used. However, the RTA method has a limit in miniaturization. In the annealing method using RTA, the heating time is several seconds, and the entire semiconductor substrate is heated to a high temperature, so that impurities may diffuse into the deep portion of the semiconductor substrate, so that it is difficult to cope with further miniaturization in the future. .

Therefore, the laser annealing method has attracted attention as a technology corresponding to further miniaturization in the future. As a conventional technique using a laser, a technique of recrystallizing silicon atoms after irradiating a 308 nm XeCl excimer laser to melt the surface of a silicon substrate is known as an annealing method.

The characteristics of the laser annealing method are that the processing time can be significantly shortened compared to the annealing method using radiant heating or conduction heating, and the semiconductor substrate is selectively heated to cause little thermal damage to the substrate. And so on.

Laser oscillators used in laser annealing are roughly classified into two types, pulse oscillation and continuous oscillation, depending on the oscillation method. In laser annealing, laser light (also referred to as a laser beam) emitted from a pulsed excimer laser is often used. The excimer laser has an advantage that it has a large output and can be repeatedly irradiated at a high repetition frequency.

Further, laser light oscillated from an excimer laser has an advantage of a high absorption coefficient for silicon often used as a semiconductor.

For example, when irradiating a laser beam, the laser beam is shaped with an optical system (such as a beam homogenizer) so that the shape of the laser beam on the irradiation surface is linear, and the irradiation position of the laser beam is relative to the irradiation surface. Move and irradiate. This method is industrially superior because it can anneal a large area of semiconductor at a time and has high productivity. (Hereinafter, laser light having a linear shape on the irradiated surface is referred to as a linear beam.)

  The main purpose of recrystallization of silicon by the laser annealing method is to bring the impurity region damaged by the implantation of impurity ions as close as possible to the single crystal and to electrically activate the impurity region.

The conventional laser annealing method using laser light oscillated from a pulsed excimer laser also has some problems to be solved, such as generation of crystal defects during melt recrystallization caused by laser annealing. I have a problem.

Therefore, as one of the methods for solving these problems, a continuous oscillation laser oscillator (hereinafter referred to as a CW laser) such as an Ar laser or a YVO ₄ laser, or a repetitive frequency of 10 MHz or more is very high. A method using a pulsed laser oscillator (hereinafter referred to as a pseudo CW laser) can be used.

However, when a CW laser or a pseudo CW laser whose laser medium is solid is applied, the wavelength range of the fundamental wave is from red to near infrared, and the laser light absorption efficiency in the semiconductor is extremely low. Incidentally, laser light with good absorption efficiency into a semiconductor is laser light having a visible or ultraviolet wavelength.

Accordingly, when a CW laser or a pseudo CW laser is used for the laser annealing method, the wavelength is converted into a harmonic wave below the visible range using a nonlinear optical element. For example, in a method of converting a near-infrared fundamental wave that easily obtains a large output into a green laser beam that is the second harmonic, it is considered that the conversion efficiency is the highest.

Harmonics are obtained by making a fundamental wave oscillated from a laser medium enter a nonlinear optical element. However, when the output of the laser increases, there is a problem that the nonlinear optical element is damaged due to nonlinear optical effects such as multiphoton absorption, leading to breakdown. Therefore, the CW laser in the visible range currently produced is about 15 W at the maximum due to the problem of nonlinear optical elements.

  Further, when laser annealing is performed using a CW laser or a pseudo CW laser, productivity is worse than when an excimer laser is used, and further improvement in productivity is necessary. For example, when laser annealing is performed by shaping a 10 W 532 nm CW laser into a linear shape having a longitudinal direction of about 300 μm and a short side direction of about 10 μm, the width of the region that can be annealed in one scan is about 200 μm. For this reason, in order to irradiate the entire surface of a semiconductor wafer having a diameter of 100 mm to 300 mm used in the mass production process, it is necessary to scan the beam spot innumerably. Note that in this specification, regardless of the shape of the laser beam on the irradiation surface, the long side of the laser beam on the irradiation surface is referred to as the longitudinal direction, and the short side is referred to as the short direction.

Therefore, the present invention is characterized in that laser annealing is performed by irradiating a semiconductor wafer with laser light having a high intensity and high repetition frequency while keeping the laser light as a fundamental wave without passing through the nonlinear optical element. To do.

High intensity means having a high peak output per unit area per unit time, and the range of the peak output of laser light in the present invention is 1 GW / cm ^{2 to 1} TW / cm ² . .

A fundamental wave having a wavelength of about 1 μm is not absorbed much even when irradiated on a semiconductor wafer, and the absorption efficiency is low. However, the present inventors have set the pulse width in the picosecond range or the femtosecond range ( ^10-15 seconds). It was found that a high-intensity laser beam can be obtained with the fundamental wave emitted from the pulse laser, and a non-linear optical effect (multiphoton absorption) occurs in the irradiated region, which can be absorbed by the semiconductor wafer.

Usually, when the energy per photon is smaller than the energy gap of the semiconductor, the photon is not absorbed by the semiconductor. For this reason, conventionally, as described above, the fundamental wave is converted into a harmonic using a nonlinear optical element to increase the energy per photon. When the n-th harmonic of the wavelength λ is used, the energy E per photon can be expressed by the following equation using the Planck constant and the speed of light c.

When a high-intensity laser beam is used, a high electromagnetic field is generated in the material irradiated with the laser beam, and a nonlinear optical effect (multiphoton absorption) occurs. With multiphoton absorption, even when the energy per photon is smaller than the energy band gap of the semiconductor, photons can be absorbed simultaneously in multiple stages and can be absorbed without passing light.

  Since the present invention does not use a nonlinear optical element and does not convert to a harmonic, a laser oscillator having an output larger than 15 W, for example, 40 W can be used for the laser annealing method. Therefore, since the width of the impurity region activated by one scan can be increased, productivity can be significantly improved.

The structure of the invention disclosed in this specification disclosed in this specification is as follows.
A step of selectively introducing impurities into a semiconductor substrate to form an impurity region; and processing a laser beam, which is a fundamental wave, into a long beam on the surface of the impurity region, and the surface of the impurity region with respect to the long beam. And a step of activating the impurity by scanning a laser beam while relatively moving the semiconductor device.

In each of the above structures, the semiconductor substrate is a single crystal silicon substrate or a compound semiconductor substrate. Typically, the semiconductor substrate is an N-type or P-type single crystal silicon substrate, a GaAs substrate, an InP substrate, a GaN substrate, or a SiC substrate. , Sapphire substrate, or ZnSe substrate. A semiconductor element in which an integrated circuit is formed using a semiconductor substrate typically includes a power supply circuit, a transmission / reception circuit, a memory, or an amplifier of a sound processing circuit.

In addition, an SOI substrate may be used, and other configurations include a step of forming a gate insulating film on a semiconductor layer of the SOI substrate, a step of forming a gate electrode on the gate insulating film, and a semiconductor of the SOI substrate. A step of selectively introducing an impurity into the layer to form an impurity region; and processing a laser beam, which is a fundamental wave, into a long beam on the surface of the impurity region, and the surface of the impurity region with respect to the long beam And a step of activating the impurity by scanning a laser beam while moving relatively.

  In each of the above structures, the impurity region is a source region or a drain region of a field effect transistor. The source region or the drain region has a low resistance by containing an impurity (As, P, etc.) imparting n-type conductivity to the semiconductor or an impurity (B) imparting p-type conductivity to the semiconductor at a high concentration. We are trying to make it. According to the present invention, by selectively irradiating laser light, only a desired portion can be activated and the resistance can be reduced.

  In each of the above structures, the impurity region is an extension region of a field effect transistor. The extension depth of the extension region is shallower than the junction depth of the source region and the drain region. In addition, the extension region contains an impurity that imparts n-type conductivity to the semiconductor or an impurity that imparts p-type conductivity to the semiconductor. In addition, both an impurity imparting n-type conductivity to the semiconductor and an impurity imparting p-type conductivity to the semiconductor may be included.

  In each of the above structures, the laser beam as the fundamental wave oscillates with a pulse width of 1 femtosecond or more and 10 picoseconds or less. By setting the pulse width in the range of 1 femtosecond or more and 10 picoseconds or less, high intensity sufficient to cause multiphoton absorption can be obtained. Multiphoton absorption does not occur in a laser beam having a pulse width of several tens of picoseconds longer than 10 picoseconds. In addition, when an experiment was performed in which a semiconductor was heated using a laser beam having a pulse width of 150 femtoseconds, it was confirmed that the semiconductor was heated. From this, it is considered that multiphoton absorption was caused.

As a laser capable of obtaining an intensity high enough to cause multiphoton absorption, there is a pulse laser having a pulse width of picosecond or femtosecond. As the pulse laser, Sapphire, YAG, ceramics YAG, ceramics Y ₂ O ₃ , KGW, KYW, Mg ₂ SiO ₄ , YLF, YVO ₄ , GdVO _4, etc. can be used for crystals such as Nd, Yb, Cr , Ti, Ho, Er and other dopants.

One feature of the present invention is that the repetition frequency of the laser used in the present invention is 10 MHz or more. The repetition frequency of the laser used in the present invention is a frequency band significantly higher than the frequency band of several tens to several hundreds of Hz used in the conventional pulse oscillation laser. It is said that the time from irradiation of a laser beam to a semiconductor by pulse oscillation until the semiconductor is completely solidified is several tens to several hundreds nsec. When a pulse laser oscillator of 10 MHz or more is used, the semiconductor is The laser light of the next pulse can be irradiated from the melting to the solidification.

If the laser beam is irradiated again at the same location within the time of several tens of nsec to several hundred nsec, the molten state can be maintained. Therefore, if it is a pulse laser with a repetition frequency of 10 MHz or more, a pseudo CW laser Such a laser is called a pseudo-CW laser.

Note that the laser annealing method in this specification refers to a technique for recrystallizing a damaged layer or an amorphous layer formed on a semiconductor substrate or a semiconductor film, or crystallizing an amorphous semiconductor film formed on a substrate. The technique and the technique which activates the dopant added to the semiconductor layer are pointed out. Moreover, the technique applied to planarization and surface modification of a semiconductor substrate or a semiconductor film is also included.

Further, in this specification, “multiphoton absorption” means simultaneous absorption of two or more photons, and reaches a reactive electronically excited state that cannot be reached energetically by absorption of only one photon of the same energy. Means something. “Simultaneous” means two events that occur within a time of 10 ⁻¹⁴ seconds or less. In addition, the “electronic excited state” is an electronic state of a molecule at an energy higher than the electronic ground state of the molecule, and means a state that is achieved by absorption of electromagnetic radiation and has a lifetime longer than 10 ⁻¹³ seconds.

  A device obtained by the above manufacturing method is also one embodiment of the present invention, and the structure thereof is a semiconductor device including an integrated circuit including a field effect transistor, and includes a gate insulating film provided over a semiconductor layer and the gate. A gate electrode provided on the insulating film; a channel formation region formed in a semiconductor layer located below the gate electrode through the gate insulating film; and an n-type or a p-type on both sides of the channel formation region An extension region into which an impurity element is introduced; and a source region or a drain region in contact with the extension region, wherein the extension region is formed with a shallower junction depth than the source region or the drain region, and the channel formation region The length (channel length) of the semiconductor device is 5 nm to 80 nm.

  According to the present invention, activation can be performed by selectively irradiating laser light with high precision, so that the length of the channel formation region of the field effect transistor can be freely set within a range of 5 nm to 80 nm. is there.

  In the above structure, the length of the channel formation region and the width of the gate electrode are the same. Since the channel formation region existing at the position overlapping with the gate electrode is not irradiated with laser light and hardly diffuses, the length of the channel formation region is the same as the width of the gate electrode.

  In the above structure, the integrated circuit includes at least one of a controller, a CPU, and a memory.

  According to the present invention, it is possible to obtain a laser beam having a very large output, for example, one having energy more than twice that of a harmonic without requiring a nonlinear optical element for wavelength conversion. Further, according to the present invention, it is possible to prevent the activated impurities from unnecessarily diffusing into the deep portion of the substrate. Therefore, at the time of recrystallization, the impurities in the irradiated region can be efficiently activated in a state where the semiconductor substrate is kept at a sufficiently low substrate temperature, which can be used for development of a higher performance device.

  In addition, according to the present invention, an ultra-shallow junction having a shallow junction depth can be formed. If an ultra-shallow junction can be formed, leakage current can be reduced and low power consumption can be realized. In addition, the semiconductor integrated circuit can be further miniaturized and highly integrated.

In addition, since nonlinear optical elements are easily altered, there is a drawback that the maintenance-free state, which is an advantage of solid-state lasers, cannot be maintained for a long time, but the present invention does not use nonlinear optical elements, so that the disadvantages are overcome. Can do. That is, the present invention improves the stability and reliability of the laser irradiation apparatus itself.

Embodiments of the present invention will be described below. However, the present invention can be implemented in many different modes, and various changes can be made in form and details without departing from the spirit and scope of the present invention.

(Embodiment 1)
FIG. 1 is a perspective view showing an example of a laser irradiation apparatus of the present invention.

As the laser oscillator 101 illustrated in FIG. 1, a laser oscillator of a laser (also referred to as a femtosecond laser) that oscillates in the femtosecond (10 ⁻¹⁵ second) range is used. As the laser oscillator, crystals such as Sapphire, YAG, ceramics YAG, ceramics Y ₂ O ₃ , KGW, KYW, Mg ₂ SiO ₄ , YLF, YVO ₄ , GdVO ₄ , Nd, Yb, Cr And a laser to which a dopant such as Ti, Ho, and Er is added. Note that the laser oscillator 101 does not incorporate a nonlinear optical element, and emits a fundamental wave of a laser beam. The laser oscillator 101 does not include a nonlinear optical element for converting light oscillated from a laser medium into a harmonic, but has a light intensity sufficient to cause a nonlinear optical effect (multiphoton absorption) in a semiconductor. It is.

First, the laser beam emitted from the laser oscillator 101 passes through the slit 102. The slit 102 can block a weak energy portion of the laser beam, and can adjust the length of the laser beam in the longitudinal direction on the irradiation surface. The slit 102 used in the present invention is not particularly limited, and a slit or a structure that can block a weak portion when passing through the slit can be used.

  Next, the direction of the laser beam that has passed through the slit 102 is changed by the mirror 103 and deflected in the direction of the semiconductor substrate 106. Note that the direction of the laser beam after changing the direction may be perpendicular or oblique to the semiconductor substrate.

  Next, the laser beam whose direction is changed by the mirror 103 projects an image of the slit 102 onto the semiconductor substrate 106 as an irradiation surface by the first cylindrical lens 104 that acts only in one direction. Further, the laser beam is condensed by the second cylindrical lens 105 acting only in one direction rotated by 90 degrees with the first cylindrical lens 104 and irradiated onto the semiconductor substrate 106. With the first cylindrical lens 104 and the second cylindrical lens 105, a linear, elliptical, or rectangular beam irradiation region 111 is obtained on the irradiation surface. The first cylindrical lens 104 performs beam shaping in the long direction of the beam irradiation region 111, and the second cylindrical lens 105 performs beam shaping in the short direction of the beam irradiation region 111. The cylindrical lens used in the present invention may have a convex surface on either the incident side or the exit side, or may have convex surfaces on both sides. It is preferable to use one having a convex surface.

  The optical system of the present invention will be described in detail with reference to FIG. Note that the reference numerals used in FIG. 2 are the same as those used in FIG. 2A shows the long direction of the beam irradiation region, and FIG. 2B shows the short direction. The laser beam emitted from the laser oscillator 101 is partially blocked by the slit 102, and only the portion where the intensity of the laser beam is strong passes through the slit. The laser beam that passes through the first cylindrical lens 104 projects an image formed by the slit 102 onto the semiconductor substrate 106. A laser beam 110 indicated by a solid line in FIG. 1 indicates a laser beam passing through the center of the beam irradiation region 111.

Here, the positional relationship among the first cylindrical lens 104, the slit 102, and the semiconductor substrate 106 serving as an irradiation surface, which is one of the features of the present invention, will be described in detail. The reason for using the slit 102 is to prevent the semiconductor substrate from being irradiated with a weak energy portion of the laser beam. When such a laser beam is irradiated onto a semiconductor substrate, a polycrystalline region (herein referred to as a poor crystallinity region) with relatively small crystal grains having a lot of irregularities on the surface is formed, which is not preferable. Therefore, the slit 102 is used so that such a region is not formed in the semiconductor substrate. Normally, when a part of the laser beam is shielded by a slit, a phenomenon called diffraction due to the coherence of the laser occurs. This causes diffraction fringes in the laser beam. The following describes a method in which such diffraction fringes do not occur on the irradiated surface.

In the following two formulas, the focal length of the first cylindrical lens 104 is set to f, and the opening width of the slit 102 is set to s. At this time, the interval between the slit 102 and the first cylindrical lens 104 is M1, and the interval between the first cylindrical lens 104 and the semiconductor substrate 106 is M2. Further, L is the length of the linear laser beam on the semiconductor substrate 106 serving as the irradiation surface in the longitudinal direction. At this time, the following two expressions hold.

From the above two formulas, the following two formulas hold.

By arranging the slit, the first cylindrical lens, and the irradiation surface at a position that satisfies these relationships, the fringes due to diffraction are not transmitted to the semiconductor substrate. As a result, it is possible to realize laser irradiation in which almost no poor crystallinity region is generated.

  Further, when the beam diameter, output, and beam shape of the emitted laser beam can be used as they are, it is not always necessary to use two cylindrical lenses. In addition, when focusing is performed while maintaining the ratio between the long and short lengths of the emitted laser beam, a spherical lens may be used instead of the cylindrical lens.

Then, laser irradiation is performed by moving the semiconductor substrate 106 at an appropriate speed. The semiconductor substrate 106 is fixed to the substrate fixing stage 107 by suction means or mechanical fixing means so that the substrate does not fall during laser irradiation. Further, the substrate fixing stage 107 can be moved in the X direction or the Y direction within the plane of the substrate fixing stage parallel to the surface of the semiconductor substrate using the X stage 108 and the Y stage 109. The X stage 108 and the Y stage 109 can move the semiconductor substrate fixed to the substrate fixing stage 107 at a speed of 100 to 1000 mm / sec. Here, a method in which a laser beam is scanned by moving a stage on which a semiconductor substrate is placed in an X direction (or Y direction) with respect to a fixed laser beam irradiation region. Note that the optimum scanning speed expected from the inventors' experience is around 400 mm / sec.

Further, the method is not limited to the method of moving the X stage 108 and the Y stage 109, and laser light may be scanned by a galvano mirror or a polygon mirror, and along the vertical direction (Y direction) of the substrate,
It is only necessary that the laser beam formed in a band shape is irradiated and the irradiation region is moved in the lateral direction (X direction) relative to the substrate to scan the laser light.

According to the present invention, laser irradiation is used for activation treatment, and a semiconductor element such as an FET can be appropriately manufactured, which can be used for development of a higher performance device.

  Further, the diffusion distance of impurities with respect to the pulse width of the laser can be obtained by the following equation.

Here, τ _L indicates time, that is, the pulse width of the laser. Further, _{D F} is the thermal diffusivity of the _material, a _{D F = K T / ρC P} . However, _{K T} is the thermal conductivity, [rho is the density, _{C P} is the specific heat capacity. The thermal conductivity _{K T} of the crystalline silicon is 148 W / m · K, the density ρ of crystalline silicon, was 2330kg / cm ^3, the specific heat capacity _{C P} of the crystalline silicon is the 700J / (kg · K) . Thus, the thermal diffusion coefficient _{D F} crystalline silicon becomes ^{9.074 × 10 -5 m 2 / s} .

For example, when the laser pulse width is 1 ps, the thermal diffusion length _{L D} of the crystalline silicon can be calculated as 9.525853Nm. When a laser beam emitted from a pulse laser with a pulse width in the picosecond or femtosecond ( ^10-15 seconds) range is used as described above, the thermal diffusion distance of crystalline silicon is extremely small, and the laser beam is irradiated with the laser beam. Only the part is in a high-temperature and high-density energy state, indicating that there is almost no heat-affected layer due to thermal diffusion. That is, when a laser beam emitted from a pulse laser with a pulse width on the order of picoseconds or femtoseconds ( ^10-15 seconds) is used to activate impurities added to the semiconductor, the junction depth is very shallow. A bond can be formed.

  In the present invention, the junction depth can be freely adjusted by appropriately setting the irradiation conditions such as the pulse width of the laser.

  Although an example used for activation is shown here, the present invention is not particularly limited, and can be applied to various laser annealing processes represented by a silicide formation process or the like.

(Embodiment 2)
A procedure for manufacturing an FET using the present invention will be briefly described below with reference to FIGS. 3 (A) and 3 (B). Here, a fundamental wave having a wavelength in the near-infrared region and a pulse width of about 10 ps or less is irradiated to the impurity region into which the impurity is introduced, and a nonlinear optical effect (multiphoton) is applied to the irradiation region. An example of performing activation by causing absorption) will be described.

  First, a silicon substrate 301 made of single crystal silicon is prepared. Then, the n-type well 302 and the p-type well 303 are selectively formed in the first element formation region and the second element formation region of the main surface (element formation surface or circuit formation surface) of the silicon substrate, respectively.

  Next, a field oxide film 306 serving as an element isolation region for partitioning the first element formation region and the second element formation region is formed. The field oxide film 306 is a thick thermal oxide film and may be formed using a known LOCOS method. The element isolation method is not limited to the LOCOS method. For example, the element isolation region may have a trench structure using the trench isolation method, or may be a combination of the LOCOS structure and the trench structure.

  Next, a gate insulating film is formed by thermally oxidizing the surface of the silicon substrate, for example. The gate insulating film may be formed by a CVD method, and a silicon oxynitride film, a silicon oxide film, a silicon nitride film, or a stacked film thereof can be used. For example, a stacked film of a silicon oxide film having a thickness of 5 nm obtained by thermal oxidation and a silicon oxynitride film having a thickness of 10 nm to 15 nm obtained by a CVD method is formed.

Next, a laminated film of polysilicon layers 311a and 317a and silicide layers 311b and 317b is formed on the entire surface, and the laminated film is patterned based on a lithography technique and a dry etching technique, thereby forming a gate electrode having a polycide structure on the gate insulating film. 311 and 317 are formed. The polysilicon layers 311a and 317a may be doped with phosphorus (P) at a concentration of about 10 ²¹ / cm ³ in advance in order to reduce the resistance, or after the polysilicon films 311a and 317a are formed. An n-type impurity may be diffused. The silicide layers 311b and 317b can be made of molybdenum silicide (MoSix), tungsten silicide (WSix), tantalum silicide (TaSix), titanium silicide (TiSix), or the like. Just do it.

Next, in order to form an extension region, ion implantation is performed on the silicon semiconductor substrate through the gate insulating film. In this embodiment mode, an impurity region formed between each source region and drain region and a channel formation region is referred to as an extension region. The impurity concentration of the extension regions 307 and 313 may be lower than that of the source region and the drain region, may be equal, or may be higher. That is, the impurity concentration in the extension region may be determined based on characteristics required for the semiconductor device.

  Since this embodiment is a case of manufacturing a CMOS, a first element formation region in which a p-channel FET is to be formed is covered with a resist material, and arsenic (As) or phosphorus (P) that are n-type impurities. Is injected into the silicon substrate. Further, the second element formation region in which the n-channel FET is to be formed is covered with a resist material, and boron (B) that is a p-type impurity is implanted into the silicon substrate.

  Next, a first activation process is performed in order to activate the ion-implanted impurities and recover crystal defects in the silicon substrate generated by the ion implantation. In the present embodiment, as shown in the first embodiment, activation is performed by irradiating a laser beam having a fundamental wave and a pulse width of 10 ps or less to generate a nonlinear optical effect (multiphoton absorption). Do. In order to perform this process efficiently, the repetition frequency of the laser may be 10 MHz or more. The semiconductor substrate is heated to a temperature about the melting point of Si, and the thin layer on the surface is locally heated to be activated. At this time, since the impurities in Si are heated in a very short time, the distance that can be moved during that time is extremely short. However, since the distance is sufficient to move to the lattice point of Si, the implanted impurity can be sufficiently activated by this process. In addition, as described in the previous discussion, the migration distance of impurities by this process is as short as about 1 nm or less, which can suppress the diffusion of impurities as much as possible.

  Next, sidewalls 312 and 318 are formed on the sidewalls of the gate electrode. For example, an insulating material layer made of silicon oxide may be made to have a volume by a CVD method over the entire surface, and the insulating material layer may be etched back to form a sidewall. The gate insulating film may be selectively removed in a self-aligned manner during the etch back. Further, the gate insulating film may be etched after the etch back. Thus, gate insulating films 310 and 316 having a total width of the width of the gate electrode and the widths of the sidewalls provided on both sides of the side wall of the gate electrode are formed.

  Next, ion implantation is performed on the exposed silicon substrate to form a source region and a drain region. Since the CMOS is manufactured, the first element formation region where the p-channel FET is to be formed is covered with a resist material, and n-type impurities such as arsenic (As) and phosphorus (P) are implanted into the silicon substrate. Thus, a source region 314 and a drain region 315 are formed. Further, the second element formation region where the n-channel FET is to be formed is covered with a resist material, and boron (B) which is a p-type impurity is implanted into the silicon substrate to form the source region 308 and the drain region 309.

  Next, a second activation process is performed in order to activate the ion-implanted impurities and recover crystal defects in the silicon substrate generated by the ion implantation. The second activation process is also a fundamental wave, and activation is performed by irradiating a laser beam having a pulse width of 10 ps or less to generate a nonlinear optical effect (multiphoton absorption). A cross-sectional view at this stage corresponds to FIG.

  Then, after activation, an interlayer insulating film, a plug electrode, a metal wiring, and the like are formed. The first interlayer insulating film 331 is formed to a thickness of 100 to 2000 nm using a silicon oxide film, a silicon oxynitride film, or the like by using a plasma CVD method or a low pressure CVD method. Further thereon, a second interlayer insulating film 332 of phosphorus glass (PSG), boron glass (BSG), or phosphorus boron glass (PBSG) is formed. The second interlayer insulating film 332 is formed by spin coating or atmospheric pressure CVD in order to improve flatness.

  The source electrodes 333 and 335 and the drain electrodes 334 and 336 are formed after forming contact holes reaching the source and drain regions of the respective FETs in the first interlayer insulating film 331 and the second interlayer insulating film 332. Therefore, it is preferable to use aluminum (Al) which is usually used as a low resistance material. Alternatively, a stacked structure of Al and titanium (Ti) may be used.

  Although not shown here, a contact hole reaching the gate electrode is provided in the first interlayer insulating film 331 and the second interlayer insulating film 332, and a wiring provided on the second interlayer insulating film and An electrode to be electrically connected is formed on a part of the first interlayer insulating film in the opening.

  Finally, a passivation film 341 and a third interlayer insulating film 342 are formed to obtain the state shown in FIG. In FIG. 3B, the left-side transistor is a p-channel FET 201, and the right-side transistor is an n-channel FET 202.

The passivation film 341 is formed of a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film by a plasma CVD method. Further, the third interlayer insulating film 342 is formed of an organic resin material with a thickness of 1 μm to 2 μm. As the organic resin material, polyimide, polyamide, acrylic, benzocyclobutene (BCB), or the like can be used. Advantages of using the organic resin film include that the film formation method is simple, that the parasitic capacitance can be reduced because the relative dielectric constant is low, and that it is suitable for planarization. Of course, organic resin films other than those described above may be used.

  According to the present invention, short channel effects such as punch-through and gate leakage can be suppressed, and further miniaturization of a semiconductor device can be promoted. Further, according to the present invention, it is possible to freely design the distance between the source region and the drain region of the FET and the width of the extension region. Therefore, according to the present invention, the FET channel length can be freely designed in the range of 5 nm to 80 nm.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1.

(Embodiment 3)
A method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings. This embodiment shows an example in which an SOI (silicon on insulator) substrate in which an insulating layer and a single crystal semiconductor layer are stacked is used.

As an SOI substrate, for example, a SIMOX (separation by implied oxygen) substrate can be cited. The SIMOX substrate 510 is a substrate in which a single crystal semiconductor layer is formed on an insulating layer and the insulating layer by embedding oxygen molecules in a portion slightly deep from the surface of the single crystal semiconductor layer and oxidizing it with high heat. A substrate in which a first single crystal semiconductor layer 511, an insulating layer 512, and a second single crystal semiconductor layer 513 are stacked (see FIG. 4A).

A method for manufacturing a semiconductor device of the present invention using the SIMOX substrate 510 will be described. First, a plurality of first elements such as a field effect transistor using the first single crystal semiconductor layer 511 on one surface of the SIMOX substrate 510 as an active layer are formed. Next, a layer 514 including a second element is formed over the first single crystal semiconductor layer 511 (see FIG. 4B). Next, the second single crystal semiconductor layer 513 on the surface opposite to the one surface of the SIMOX substrate 510 is removed by etching (see FIG. 4C). Then, the semiconductor device 516 in which the insulating layer 512, the first single crystal semiconductor layer 511, and the layer 514 including the second element are sequentially stacked is completed (see FIG. 4D).

Note that the removal of the second single crystal semiconductor layer 513 may be performed using a grinding and polishing apparatus 515 such as a grindstone, or may be performed using an etching agent, or the grinding and polishing apparatus 515 and the etching agent are used in combination. You may do it. Preferably, the second single crystal semiconductor layer 513 is ground and polished until the second single crystal semiconductor layer 513 becomes thin to some extent, and then the second single crystal semiconductor layer 513 is removed with an etchant until the insulating layer 512 is exposed. If the etching agent is wet etching, a mixture of hydrofluoric acid diluted with water or ammonium fluoride, a mixture of hydrofluoric acid and nitric acid, a mixture of hydrofluoric acid, nitric acid and acetic acid, a mixture of hydrogen peroxide and sulfuric acid, hydrogen peroxide And a mixed solution of ammonium water and water, a mixed solution of hydrogen peroxide, hydrochloric acid, and water. In the case of dry etching, a gas containing a halogen atom or molecule such as fluorine or a gas containing oxygen is used. Preferably, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, chlorine trifluoride (ClF ₃ ) may be used as a gas containing halogen fluoride.

The thickness of the second single crystal semiconductor layer 513 included in the SIMOX substrate 510 is several tens to several hundreds of μm, whereas the thickness of the first single crystal semiconductor layer 511 is 0.3 μm or less. Very thin. Accordingly, if a plurality of field effect transistors are formed using the first single crystal semiconductor layer 511 and then the second single crystal semiconductor layer 513 is removed, a semiconductor device that is small, thin, and lightweight, for example, an ultra-large scale A memory device such as an integrated circuit (ULSI), SRAM, or DRAM can be provided.

  In order to describe in more detail, a method for manufacturing a DRAM using a first element as a field effect transistor and a second element as a memory element will be described below with reference to FIGS.

First, as illustrated in FIG. 5A, an inorganic insulating film 614 is formed over a SIMOX substrate in which a first single crystal semiconductor layer 511, an insulating layer 512, and a second single crystal semiconductor layer 513 are stacked. To do.

Next, a gate electrode 616 made of a conductive material is formed, and the inorganic insulating film is etched in a self-aligning manner using the gate electrode 616 as a mask to form the gate insulating film 615. At this stage, the state of FIG. 5B is obtained.

Next, in order to form an extension region, an impurity is introduced by a plasma doping method to form a first impurity region 617a. Ultra shallow impurity implantation can be performed by using the plasma doping method. At this stage, the state of FIG. 5C is obtained.

Next, in order to activate the introduced impurity with a very shallow profile (distribution) at a high concentration, a laser beam having a fundamental wave and a pulse width of 10 ps or less is irradiated, and the irradiated region is nonlinearly applied. Laser annealing that produces an optical effect (multiphoton absorption) is performed. Thus, a first impurity region 617b that is electrically activated is formed. At this stage, the state of FIG. 5D is obtained.

  Next, a silicon nitride film is formed so as to cover the gate electrode 616, and anisotropically dry-etched by the thickness. Thus, as shown in FIG. 5E, a sidewall 618 is formed in which the silicon nitride film is partially left on the sidewall of the gate electrode 616. By forming the sidewall 618, an impurity concentration gradient is formed at the end of the gate electrode 616, thereby improving the reliability of the field effect transistor.

Next, in order to form a source region and a drain region, an impurity is introduced by an ion doping method to form a second impurity region 619. Impurity implantation is performed deeper than the first impurity region by using an ion doping method. At this stage, the state of FIG. 5F is obtained.

Next, the second impurity region 619 is activated. As activation here, laser annealing at an energy density of about 0.1 to 1 J / cm ² is performed using a YAG laser or a XeCl laser. Instead of this laser annealing, it is also possible to perform laser annealing using a laser beam having a fundamental wave and a pulse width of 10 ps or less.

Next, after a first silicon oxide film 620 is formed by a CVD method, it is planarized by CMP, and a contact hole is formed by a photolithography process. A contact hole formed by etching the first silicon oxide film 620 is filled with polysilicon, and an extraction terminal (also referred to as a plug) 621 in contact with the second impurity region 619 is formed. Capacitor plugs 624 and 625 are also formed at the same time. Next, after a second silicon oxide film 622 is formed on the entire surface, a portion for forming a bit line is opened. Next, a TiN film and a W film are stacked by sputtering and patterned to form a bit line 623. Note that the bit line 623 is common to two memory cells.

Next, in order to form a capacitor further above the bit line 623, a third silicon oxide film 626 and a silicon nitride film 627 are formed by a CVD method, and then planarized by CMP, and contact hole photolithography is performed. Contact holes formed by etching the third silicon oxide film 626 and the silicon nitride film 627 are filled with polysilicon, and the capacitor second plugs 628 and 629 in contact with the capacitor first plugs 624 and 625 are filled. Form.

Next, in order to form a cylindrical capacitor, a fourth silicon oxide film is formed by a CVD method with a film thickness corresponding to the height of the capacitor to be formed. The hole pattern of the capacitor is formed by photolithography and etched. The capacitor is designed to be as large as possible without touching the adjacent capacitor.

Next, a thin polysilicon film is formed on the entire surface including the inner surface of the hole of the fourth silicon oxide film by the CVD method. Next, when the polysilicon film is partially removed by performing etch back, the polysilicon film remains only on the inner surface of the hole, and a cylindrical electrode (lower electrode of the capacitor) 630 is formed.

Further, the present invention is not limited to the structure of the memory cell shown in FIG. 6, and may be, for example, a planar type, a stack type, or a trench type.

Next, a Ta ₂ O ₅ film and a TiN film are formed by a CVD method, and then patterned to form an upper electrode (also called a plate) 631 made of the TiN film. The memory cell is completed through the above steps. Note that BaSrTiO ₃ , SiO ₂ , Si ₃ N _4, or the like can be used as a dielectric instead of the Ta ₂ O ₅ film.

Then, a first interlayer insulating film 632 or a second interlayer insulating film 633 is formed, and a CMOS circuit (not shown) provided in the periphery is connected by the first wiring and the second wiring. The upper and lower wirings are electrically connected by forming contact holes and plugs.

The CMOS circuit is connected by the first wiring and the second wiring. As shown in FIG. 6, only the first wiring and the second wiring cross over the memory array. A total of three layers of wiring structures including a bit line, a first wiring, and a second wiring are assembled for the peripheral field effect transistor.

  The first wiring is formed by stacking a TiN film 634a and a film 634b containing Al as a main component. The second wiring is also formed by stacking a TiN film 635a and a film 635b containing Al as a main component.

Then, annealing is performed in a hydrogen atmosphere in order to recover damage after various processes. Then, a final protective film 636 made of a silicon oxide film or a silicon nitride film is formed, and an opening is made so that the second wiring is exposed at the bonding pad (connecting terminal portion to the package).

Finally, the second single crystal semiconductor layer 513 is cut and thinned. Thus, a DRAM whose structure is partially shown in FIG. 6 is completed.

Then, dicing is performed to separate the chips having DRAM from the wafer. Next, chips are picked up one by one from the wafer and mounted on the lead frame. Then, the electrode terminals of the chip and the inner leads of the lead frame are connected so as to be electrically connected by a gold wire having a diameter of about 20 to 30 μm. Then, it is sealed with a mold resin layer so as to facilitate handling. The leads are then solder plated to prevent rust. Next, the lead frame is cut into individual packages, and the leads are molded. Thus, packaging is performed.

FIG. 7 is a perspective view showing a cross-sectional structure of a device on which packaging is performed. In the structure shown in FIG. 7, a chip 702 is connected to a lead frame 701 by a wire bonding method. The chip 702 is sealed with a mold resin layer 703. The chip 702 is mounted on the lead frame 701 with a mounting adhesive 704.

  The lead frame 701 is a ball grid array type provided with solder balls 705. The solder ball 705 is provided on the surface opposite to the surface on which the chip 702 of the lead frame 701 is mounted. The wiring 706 provided in the lead frame 701 is electrically connected to the solder ball 705 through a contact hole provided in the lead frame.

  In this embodiment, the wiring 706 for electrical connection between the chip 702 and the solder ball 705 is provided on the surface of the lead frame 701 on which the chip is mounted. It is not limited to. For example, the wiring may be provided in multiple layers inside the lead frame.

  In FIG. 7, the chip 702 and the wiring 706 are electrically connected by a gold wire 707. The chip 702 is provided with a semiconductor element, and a pad is provided on the surface of the chip 702 opposite to the surface on which the lead frame 701 is provided. The pad is electrically connected to the semiconductor element. The pad is connected to a wiring 706 provided on the lead frame 701 by a gold wire 707.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

(Embodiment 4)
Various electronic devices can be completed by mounting an IC chip on which FETs manufactured using the laser annealing method of the present invention are integrated. Further, an FET manufactured by using the laser annealing method of the present invention was used as a switching element, and a reflective electrode connected to the switching element was provided to obtain a reflective active matrix substrate. By using the reflective active matrix substrate, a display portion of the electronic device can be formed, and various electronic devices can be completed.

Such electronic devices include personal computers, game devices, portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, etc.), video cameras, digital cameras, reflective projectors, navigation systems, sound playback devices. (Car audio, audio component, etc.), an image playback device (specifically, Digital Versatile Disc (DVD)) provided with a recording medium, etc., and a display and an IC chip that can display the image Apparatus).

A cellular phone which is one of the electronic devices of the present invention is taken as an example, and FIG. 8A shows a state where the package is actually mounted on the electronic device.

A cellular phone module illustrated in FIG. 8A includes a printed wiring board 816, a CPU 811 stacked on a memory 802, a power supply circuit 803, a controller 829 stacked on a sound processing circuit 801, a transmission / reception circuit 804, and the like. Elements such as resistors, buffers, and capacitive elements are mounted. Further, the panel 800 is mounted on the printed wiring board 816 by the FPC 808. The panel 800 is provided with a pixel portion 805, a scanning line driver circuit 806 that selects a pixel included in the pixel portion 805, and a signal line driver circuit 807 that supplies a video signal to the selected pixel.

  The power supply voltage to the printed wiring board 816 and various signals input from a keyboard or the like are supplied via a printed wiring board interface unit 809 on which a plurality of input terminals are arranged. Further, an antenna port 810 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 816.

  Note that in FIG. 8A, the printed wiring board 816 is mounted on the panel 800 using FPC; however, the structure is not necessarily limited thereto. The controller 829, the sound processing circuit 801, the memory 802, the CPU 811, or the power supply circuit 803 may be directly mounted on the panel 800 using a COG (Chip on Glass) method.

  Further, in the printed wiring board 816, noise may occur in the power supply voltage or the signal, or the rise of the signal may become dull due to the capacitance formed between the drawn wirings, the resistance of the wiring itself, or the like. Therefore, by providing various elements such as a capacitor and a buffer on the printed wiring board 816, it is possible to prevent noise from being applied to the power supply voltage and the signal and the rise of the signal from being slowed down.

  FIG. 8B illustrates an example of a module provided with an integrated circuit mounted on an FPC.

As shown in FIG. 8B, an integrated circuit (controller 901, CPU (Central Processing unit) 902, memory 903) is mounted on the FPC 908. The panel 900 is provided with a pixel portion 905 and a driving circuit (a signal line driving circuit 907 and a scanning line driving circuit 906), and these and an external power supply (not shown) provided outside are electrically connected. An FPC 908 for connection is attached to the panel 900 with an adhesive 909. By providing an integrated circuit (a controller 901, a CPU 902, and a memory 903) using a semiconductor substrate over the FPC 908, it is possible to prevent noise from being applied to a power supply voltage and a signal and a rise of a signal from being slowed down.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment Mode 3.

(Embodiment 5)
An IC chip on which an FET manufactured using the laser annealing method of the present invention is integrated is used as a thin film integrated circuit or a non-contact type thin film integrated circuit device (wireless IC tag, also referred to as RFID (Radio Frequency Identification)). You can also.

FIG. 9 shows an example of an ID card in which the IC chip 1516 of the present invention is attached to a card-like substrate 1518 provided with a conductive layer 1517 functioning as an antenna. As described above, the IC chip 1516 of the present invention is small, thin, and lightweight, realizes a wide variety of uses, and does not impair the design of the article even when attached to the article.

Note that the IC chip 1516 of the present invention is not limited to the form of being attached to the card-like substrate 1518, and can be attached to a curved surface or an article having various shapes. For example, IC chips are bills, coins, securities, bearer bonds, certificate documents (driver's license, resident's card, etc.), packaging containers (wrapping paper, bottles, etc.), recording media (DVD software, video tape, etc.) ), Vehicles (such as bicycles), personal items (such as bags and glasses), foods, clothing, daily necessities, and the like.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, or Embodiment Mode 4.

(Embodiment 6)
Various electronic devices can be completed by mounting as an IC chip using an FET manufactured by using the laser annealing method of the present invention. A specific example will be described with reference to FIG.

  FIG. 10A illustrates a display device, which includes a housing 1901, a support base 1902, a display portion 1903, a speaker portion 1904, a video input terminal 1905, and the like. This display device is manufactured by using a FET formed by the manufacturing method described in another embodiment for a driver IC. The display device includes a liquid crystal display device, a light emitting device, and the like, and specifically includes all information display devices such as a computer, a television receiver, and an advertisement display.

  FIG. 10B illustrates a computer, which includes a housing 1911, a display portion 1912, a keyboard 1913, an external connection port 1914, a pointing mouse 1915, and the like. By forming an FET using the manufacturing method described in the above embodiment mode, the formed FET can be applied to a driver IC for a display portion, a CPU in a main body, a memory, or the like.

FIG. 10C illustrates a mobile phone, which is a typical example of a portable information terminal. This mobile phone includes a housing 1921, a display portion 1922, a sensor portion 1924, operation keys 1923, and the like. The sensor unit 1924 includes an optical sensor element, and controls the luminance of the display unit 1922 according to the illuminance obtained by the sensor unit 1924 or controls illumination of the operation key 1923 according to the illuminance obtained by the sensor unit 1924. By doing so, the current consumption of the mobile phone can be suppressed. In the case of a mobile phone having an imaging function such as a CCD, it is detected whether or not the photographer has looked into the optical viewfinder by changing the amount of light received by the sensor unit 1924 provided near the optical viewfinder. When the photographer is looking into the optical viewfinder, power consumption can be suppressed by turning off the display portion 1922.

Since electronic devices such as PDAs (Personal Digital Assistants, information portable terminals), digital cameras, and small game machines are portable information terminals, the display screen is small. Therefore, functional circuits such as a CPU, a memory, and a sensor can be formed using the FET shown in the above-described embodiment, so that the size and weight can be reduced.

In addition, by attaching the IC tag to various electronic devices, the distribution route of the electronic devices can be clarified. FIG. 10D illustrates a state where the wireless IC tag 1942 is attached to the passport 1941. A wireless IC tag may be embedded in the passport 1941. Similarly, you can attach or embed a wireless IC tag to a driver's license, credit card, banknote, coin, securities, gift certificate, ticket, traveler's check (T / C), health insurance card, resident card, family register copy, etc. it can. In this case, only information indicating authenticity is input to the wireless IC tag, and an access right is set so that information cannot be read or written illegally. This can be realized by using the memory shown in another embodiment. Thus, by using such a tag, it becomes possible to distinguish it from a forged one.

In addition, a wireless IC tag can be used as a memory. FIG. 10E illustrates an example in which the wireless IC tag 1951 is used as a label attached to a vegetable package. Further, a wireless IC tag may be attached or embedded in the package itself. The wireless IC tag 1951 includes a production stage process such as production place, producer, date of manufacture, processing method, product distribution process, price, quantity, usage, shape, weight, expiration date, various authentication information, etc. Can be recorded. Information from the wireless IC tag 1951 is received and read by the antenna unit 1953 of the reader 1952 and displayed on the display unit 1954 of the reader 1952, so that it is easy for the wholesaler, retailer, and consumer to grasp. In addition, by setting access rights for each of producers, traders, and consumers, a system is incapable of reading, writing, rewriting, and erasing without access rights.

The wireless IC tag can be used as follows. At the time of accounting, the fact that accounting has been completed is entered in the wireless IC tag, and a check means is provided at the exit to check whether accounting has been written on the wireless IC tag. If you try to leave the store without checking out, an alarm will sound. This method can prevent forgetting to pay and shoplifting.

Further, in consideration of customer privacy protection, the following method can be used. At the stage of accounting at the cash register, (1) lock the data input to the wireless IC tag with a password, (2) encrypt the data itself input to the wireless IC tag, (3) wireless Either the data input to the IC tag is deleted, or (4) the data input to the wireless IC tag is destroyed. These can be realized by using the memory described in the other embodiments. Then, by providing a check means at the exit, it is checked whether any of the processes (1) to (4) has been performed, or whether the wireless IC tag data has not been processed. Check for accounting. In this way, it is possible to check whether or not there is a transaction in the store, and it is possible to prevent information on the wireless IC tag from being read outside the store against the will of the owner.

By using the present invention, further miniaturization can be achieved while suppressing the short channel effect, and the miniaturization of the IC chip provided in the wireless IC tag can be realized. The smaller the size of the IC chip, the higher the impact resistance, so that the reliability is improved. Further, by the laser annealing method of the present invention, any wireless IC tag can be manufactured with high quality and no variation in performance.

  As described above, the applicable range of the semiconductor device manufactured according to the present invention is so wide that the semiconductor device manufactured according to the present invention can be used for electronic devices in various fields.

  This embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, Embodiment Mode 4, or Embodiment Mode 5.

According to the present invention, activation can be performed with a laser beam having a very high output without requiring a nonlinear optical element for wavelength conversion. Accordingly, since the width of the region that can be activated by one scan can be increased, productivity can be significantly improved.

  Further, according to the present invention, further miniaturization of the semiconductor integrated circuit can be promoted, and the degree of integration of the IC can be enhanced. In addition, according to the present invention, the number of chips per wafer can be increased.

The perspective view which shows an example of a laser irradiation apparatus. It is a figure which shows the optical system of a laser irradiation apparatus. It is sectional drawing of the manufacturing process of FET of this invention. The figure which shows the preparation process of a SIMOX board | substrate. The figure which shows the preparation process of FET using a SIMOX board | substrate. The cross-section figure of DRAM which used the SIMOX substrate. The perspective view showing the cross-section of the device in which the package was performed. The top view which shows the example which mounted the IC chip of this invention in the panel module. The top view which shows the example which mounted the IC chip of this invention on the card | curd. FIG. 14 illustrates an example of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Laser oscillator 102 Slit 103 Mirror 104 1st cylindrical lens 105 2nd cylindrical lens 106 Semiconductor substrate 107 Substrate fixed stage 108 X stage 109 Y stage 110 Laser beam 111 Beam irradiation area 201 p channel type FET
202 n-channel FET
301 substrate 302 n-type well 303 p-type well 306 field oxide film 307 extension region 308 source region 309 drain region 310 gate insulating film 311 gate electrode 311a polysilicon layer 311b silicide layer 312 sidewall 313 extension region 314 source region 315 drain region 316 Gate insulating film 317 Gate electrode 317a Polysilicon layer 317b Silicide layer 318 Side wall 331 First interlayer insulating film 332 Second interlayer insulating film 333 Source electrode 334 Drain electrode 335 Source electrode 336 Drain electrode 341 Passivation film 342 Third interlayer Insulating film 510 SIMOX substrate 511 First single crystal semiconductor layer 512 Insulating layer 513 Second single crystal semiconductor layer 514 Layer 5 including second element DESCRIPTION OF SYMBOLS 5 Grinding polisher 516 Semiconductor device 614 Inorganic insulating film 615 Gate insulating film 616 Gate electrode 617a First impurity region 617b First impurity region 618 Side wall 619 Second impurity region 620 First silicon oxide film 621 Lead terminal 622 Second silicon oxide film 623 Bit line 624 Plug 625 Plug 626 Third silicon oxide film 627 Silicon nitride film 628 Plug 629 Plug 630 Electrode 631 Upper electrode 632 First interlayer insulating film 633 Second interlayer insulating film 634a TiN film 634b Film mainly containing Al 635a TiN film 635b Film mainly containing Al 636 Final protective film 701 Lead frame 702 Chip 703 Mold resin layer 704 Adhesive 705 Solder ball 706 Wiring 707 Gold wire 800 Panel 801 Audio processing circuit 802 Mori 803 Power supply circuit 804 Transmission / reception circuit 805 Pixel portion 806 Scan line driving circuit 807 Signal line driving circuit 808 FPC
809 Interface unit 810 Antenna port 811 CPU
816 Printed wiring board 829 Controller 900 Panel 901 Controller 902 CPU
903 Memory 905 Pixel portion 906 Scanning line driving circuit 907 Signal line driving circuit 908 FPC
909 Adhesive 1516 IC chip 1517 Conductive layer 1518 Card-like substrate 1901 Case 1902 Support 1903 Display 1904 Speaker 1905 Video input terminal 1911 Case 1912 Display 1913 Keyboard 1914 External connection port 1915 Pointing mouse 1921 Case 1922 Display 1923 Operation Key 1924 Sensor Unit 1941 Passport 1942 Wireless IC Tag 1951 Wireless IC Tag 1952 Reader 1953 Antenna Unit 1954 Display Unit

Claims (9)

Forming a gate electrode on the semiconductor substrate;
Selectively introducing a first impurity into the semiconductor substrate to form a first impurity region in the semiconductor substrate;
Irradiating the first impurity region with a linear, elliptical, or rectangular first laser beam to activate the first impurity contained in the first impurity region;
Forming a sidewall on a side surface of the gate electrode after activating the first impurity;
Forming a second impurity region in the semiconductor substrate by selectively introducing a second impurity into the semiconductor substrate after forming the sidewall;
Irradiating the second impurity region with a second laser beam having a linear, elliptical or rectangular shape, and activating the second impurity contained in the second impurity region. ,
The second impurity is introduced into the semiconductor substrate deeper than the first impurity region;
The first laser beam is a fundamental wave;
The pulse width of the first laser beam is 1 femtosecond or more and 10 picoseconds or less,
Range of peak output of the first laser beam, Ri 1 GW / cm ² or more 1 TW / cm ² or less der,
The first laser beam is applied to the first impurity region which is an irradiation surface through a slit and a cylindrical lens,
The cylindrical lens is disposed between the slit and the irradiation surface,
The width of the opening of the slit is s, the focal length of the cylindrical lens is f, the distance between the slit and the cylindrical lens is M1, the distance between the cylindrical lens and the irradiation surface is M2, and the first on the irradiation surface is When the length of the laser beam in the longitudinal direction is L, the slit, the cylindrical lens, and the irradiation surface are arranged so as to satisfy M1 = f (s + L) / L and M2 = f (s + L) / s. A method for manufacturing a semiconductor device. Forming a gate insulating film on the semiconductor layer of the SOI substrate;
Forming a gate electrode on the gate insulating film;
Selectively introducing a first impurity into the semiconductor layer to form a first impurity region in the semiconductor layer;
Irradiating the first impurity region with a linear, elliptical, or rectangular first laser beam to activate the first impurity contained in the first impurity region;
Forming a sidewall on a side surface of the gate electrode after activating the first impurity;
Forming a second impurity region in the semiconductor layer by selectively introducing a second impurity into the semiconductor layer after forming the sidewall;
Irradiating the second impurity region with a second laser beam having a linear, elliptical or rectangular shape, and activating the second impurity contained in the second impurity region. ,
The second impurity is introduced into the semiconductor layer deeper than the first impurity region;
The first laser beam is a fundamental wave;
The pulse width of the first laser beam is 1 femtosecond or more and 10 picoseconds or less,
Range of peak output of the first laser beam, Ri 1 GW / cm ² or more 1 TW / cm ² or less der,
The first laser beam is applied to the first impurity region which is an irradiation surface through a slit and a cylindrical lens,
The cylindrical lens is disposed between the slit and the irradiation surface,
The width of the opening of the slit is s, the focal length of the cylindrical lens is f, the distance between the slit and the cylindrical lens is M1, the distance between the cylindrical lens and the irradiation surface is M2, and the first on the irradiation surface is When the length of the laser beam in the longitudinal direction is L, the slit, the cylindrical lens, and the irradiation surface are arranged so as to satisfy M1 = f (s + L) / L and M2 = f (s + L) / s. A method for manufacturing a semiconductor device. In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the second impurity region is a source region or a drain region of a field effect transistor. In any one of Claim 1 thru | or 3,
The method for manufacturing a semiconductor device, wherein the first impurity region is an extension region of a field effect transistor. In any one of Claims 1 thru | or 4,
The method of manufacturing a semiconductor device, wherein the first laser beam is emitted from a laser oscillator having a laser repetition frequency of 10 MHz or more. In claim 5,
The laser oscillator is composed of Sapphire, YAG, ceramics YAG, ceramics Y ₂ O ₃ , KGW, KYW, Mg ₂ SiO ₄ , YLF, YVO ₄ , or GdVO ₄ crystal, Nd, Yb, Cr, Ti, Ho, Er. A method for manufacturing a semiconductor device, wherein the semiconductor device is one selected from lasers to which any one or a plurality of dopants are added. In any one of Claims 1 thru | or 6,
The method for manufacturing a semiconductor device, wherein the first laser beam has a wavelength in a near infrared region. In any one of Claims 1 thru | or 7,
The energy density of the second laser beam, a method for manufacturing a semiconductor device, characterized in that at 0.1 J / cm ² or more 1 J / cm ² or less. In any one of Claims 1 thru | or 7,
The method for manufacturing a semiconductor device, wherein the second laser beam is a fundamental wave and has a pulse width of 10 picoseconds or less.

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