JP5055722B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a vertical power device such as a MOSFET (MOS gate field effect transistor) or IGBT (insulated gate bipolar transistor) and a low-voltage lateral device used in its control circuit are integrated on a single chip, and a manufacturing method thereof. .

Conventionally, as an in-vehicle semiconductor device mounted in an automobile or the like, a partial SOI (Silicon on Insulator) type power IC (a power IC formed on a partial SOI substrate) in which a Si—Si junction and a SiO ₂ —Si junction are mixed. Has been developed. For example, Patent Document 1 discloses a technique in which a vertical IGBT is formed in a Si—Si junction, and a CMOS or the like is provided on the insulating film of the SiO ₂ —Si junction to control it. .
In a partial SOI type power IC including such a vertical power device, a high-voltage junction termination structure (hereinafter simply referred to as an edge structure) that holds the breakdown voltage with the vertical power device is provided on the outer periphery surrounding the formation region of the power device and the control circuit. Need to be formed). However, the edge structure formed on the partial SOI substrate has hardly been disclosed so far.
The edge structure is provided on the outer periphery of the element so as to surround the active region of a vertical power device such as a vertical MOSFET or IGBT, and this is necessary for the following reason.

When a pn junction that should maintain a withstand voltage in a vertical power device extends to a scribe line that is an end of a semiconductor chip, a leakage current is generated due to crystal defects formed at the end of the semiconductor chip cut along the scribe line. It is generated and the breakdown voltage cannot be maintained. For this reason, a region for holding a breakdown voltage, that is, an edge structure is provided on the outer periphery of the element.
FIG. 30 is a cross-sectional view of a main part of a conventional semiconductor device having a general edge structure. This semiconductor device is a vertical diode. The n ⁻ drift layer 2 is formed on the n ⁺ layer 1, the p ⁻ anode region 6 is formed on the surface layer of the n ⁻ drift layer 2, and the p ⁻ guard ring region 17 and the n ⁺ stopper constituting the edge structure 28 on the outer periphery thereof. The region 8 is formed, the p ⁺ anode region 10 is formed on the surface layer of the p ⁻ anode region 6, the thermal oxide film 9 and the CVD (Chemical Vapor Deposition) oxide film 11 are formed on the surface, and the p ⁺ anode After opening thermal oxide film 9 and CVD oxide film 11 on region 10 and n ⁺ stopper region 8, anode electrode 12 and electrode 13 are formed. The edge structure 28 is formed so as to surround the active region 27. The anode electrode 12 is extended to the CVD oxide film 11 to function as a field plate.

On the other hand, for example, Patent Document 2 discloses an edge structure 28 as shown in FIG. In FIG. 31, 1 is an n ⁺ layer, 2 is an n ⁻ drift layer, 4 is a Box layer, and 5 is an n ⁻ layer. , 7 is a p ^- resurf region, 8 is an n ⁺ stopper region, 9 is a thermal oxide film, 10 is a p ⁺ anode region, 11 is a CVD oxide film, 12 is an anode electrode, 13 is an electrode, 14 is a cathode electrode, and 27 is An active region, 28 is an edge structure, A is an anode terminal, and K is a cathode terminal.
In FIG. 31, a Box (Buried Oxide) layer 4 is formed of an oxide film in the edge structure 28, a part of the breakdown voltage is borne by the Box layer 4, and the breakdown voltage burden in the n ⁻ drift layer 2 is reduced. The aim is to increase the pressure resistance. When the power IC is formed on the partial SOI substrate, such an edge structure 28 is easy to form. Therefore, it is considered useful if the effect of increasing the breakdown voltage by the Box layer 4 can be obtained.
Japanese Patent No. 3424146 JP 2004-111467 A

In practice, even in the structure of FIG. 30 without the Box layer 4, by optimizing the p ⁻ guard ring region 17 and the field plate (extension portion of the anode electrode 12), the RESURF type FIG. A breakdown voltage close to that of the structure can be obtained. FIG. 22B shows the potential distribution when 500 V is applied to the structure of FIG. As shown in FIG. 22B, when the Box layer 4 is not present, the maximum impact ionization location (location where the equipotential lines are dense) occurs in the surface layer.
FIG. 32 shows the relationship between the breakdown voltage in the edge structure 28 having the p ⁻ guard ring region 17 in FIG. 30 or the p ⁻ resurf region 7 in FIG. 31 and the boron dose in the p ⁻ guard ring region 17 or the p ⁻ resurf region 7. FIG. In the figure, (2) is a withstand voltage when the RESURF structure has the box layer 4, (4) is a guard ring structure with the box layer 4, and (5) is a guard ring structure without the box layer 4. Of withstand pressure. 32 that (2), (4), and (5) have the same peak withstand voltage. That is, even if the Box layer 4 is provided, the breakdown voltage cannot be increased as compared with the case where the Box layer 4 is not provided.

Further, although it is desirable for manufacturing that the variation in breakdown voltage is small with respect to the dose amount of the p ⁻ guard ring region 17 and the p ⁻ resurf region 7, the breakdown voltage (2) of the edge structure 28 having the Box layer 4 as can be seen from FIG. 32. , (4) has a large upward slope of the withstand voltage curve with respect to the dose (inclination in a range where the normalized withstand voltage increases with respect to the dose) compared to the withstand voltage (5) of the edge structure 28 not including the Box layer 4; For this reason, the variation in the withstand voltage with respect to the dose becomes large, which is not desirable in manufacturing. Further, the withstand voltage (4) is almost the same as the withstand voltage (5), and the effect of forming the Box layer 4 is not seen.
From the above, it is difficult to manufacture a semiconductor device having a high withstand voltage edge structure with a small withstand voltage variation only by providing the Box layer 4.
An object of the present invention is to solve the above-described problems and provide a semiconductor device having a high withstand voltage edge structure with a small withstand voltage variation using a partial SOI substrate and a manufacturing method thereof.

To achieve the above object, a first conductivity type semiconductor substrate, a first main electrode formed on the surface of the semiconductor substrate, a second main electrode formed on the back surface of the semiconductor substrate, The first power-type first power device is formed on the surface layer of the semiconductor substrate in the active region of the vertical power device and is electrically connected to the first main electrode . A first conductivity type stopper region formed on the surface layer of the semiconductor substrate having an edge structure surrounding the active region of the vertical power device and spaced apart from the first semiconductor region ; An oxide film selectively formed inside the semiconductor substrate between the first semiconductor region and the stopper region at a deeper position than the semiconductor region, and a second conductivity type buried formed in contact with the oxide film vertical power with and a region A semiconductor device having a device.
The oxide film may be formed from the lower part of the end portion of the first semiconductor region on the stopper region side to the vicinity of the end portion of the semiconductor substrate.
The buried region may be formed at or near the end on the first semiconductor region side.

Moreover, it is good to provide the 2nd conductivity type 2nd semiconductor region formed in the surface layer of the said semiconductor substrate between the said 1st semiconductor region and the said stopper area | region.
A plurality of the second semiconductor regions may be formed.
The second semiconductor region may be in contact with the first semiconductor region.
The oxide film extends from a lower portion of the end portion of the first semiconductor region on the second semiconductor region side to a lower portion of the end portion of the second semiconductor region on the stopper region side. It is good to be formed.
A first trench formed to reach the oxide film from a surface of the semiconductor substrate between the first semiconductor region and the stopper region; and second trenches formed on both side walls of the first trench. a first sidewall insulating film and the first of the first and the semiconductor region of the second conductivity type formed in the surface layer of the semiconductor substrate opposite the third semiconductor region of the trench, the first A fourth semiconductor region of the first conductivity type formed in the surface layer of the semiconductor region, and a gate insulating film on the surface of the first semiconductor region between the semiconductor substrate and the fourth semiconductor region And the gate electrode formed in such a manner that the first main electrode is electrically connected to the third semiconductor region and the fourth semiconductor region.

The oxide film may be formed so as to cover a lower portion of the first semiconductor region.
The oxide film may include a first opening for allowing a main current to flow and a second opening formed at an end of the semiconductor substrate.
Also, the semiconductor substrate is made of a second semiconductor layer formed thereon with the first semiconductor layer formed on the supporting substrate and the supporting substrate, the oxide film is the first semiconductor layer and the second It is good to form between these semiconductor layers.
Further, the inside of the semiconductor substrate is made of a second semiconductor layer formed thereon with the first semiconductor layer formed on the supporting substrate and the supporting substrate, the oxide film is the first semiconductor layer It may be formed.
The support substrate may be of a second conductivity type.

In addition, a first conductivity type buffer layer having a lower resistivity than the first semiconductor layer may be provided between the support substrate and the first semiconductor layer.
Further, it is preferable that a fifth semiconductor region of a second conductivity type formed in the end surface layer of the first semiconductor layer is provided.
The semiconductor substrate includes a first semiconductor layer and a second semiconductor layer formed thereon, and the oxide film is formed between the first semiconductor layer and the second semiconductor layer. Good.
The semiconductor substrate may be composed of a first semiconductor layer and a second semiconductor layer formed thereon, and the oxide film is formed inside the first semiconductor layer.
Further, it is preferable that a third semiconductor layer of the second conductivity type formed on the surface layer on the back surface of the first semiconductor layer is provided.

In addition, the first conductivity type buffer layer may be provided on the third semiconductor layer.
Also, an isolation oxide film formed simultaneously with the oxide film, a second trench reaching the isolation oxide film from the surface of the semiconductor substrate, and a second sidewall formed on the sidewall of the second trench An insulating isolation region having at least an oxide film may be provided.
A step of selectively forming a first diffusion region of the second conductivity type in the first semiconductor layer of the first conductivity type; and the first region including at least a part of the first diffusion region. Forming an oxide film having first and second openings selectively on the semiconductor layer; and epitaxially growing from the first and second openings on the first semiconductor layer and on the oxide film. Forming a second semiconductor layer.

  A step of selectively forming a first diffusion region of the second conductivity type in the first semiconductor layer of the first conductivity type; and the first semiconductor layer including at least a part of the first diffusion region Selectively forming oxygen inside the first semiconductor layer by ion implantation and heat treatment; and forming a second semiconductor layer by epitaxial growth on the first semiconductor layer. A manufacturing method is provided.

According to the present invention, a semiconductor layer (embedded region) having a conductivity type opposite to that of the semiconductor layer (for example, n ⁻ drift layer 2) below the partial SOI substrate is formed at the end of the oxide film of the partial SOI substrate on the active region side. Thus, the electric field strength at the end of the oxide film can be reduced, and a high breakdown voltage can be ensured and the peak of the breakdown voltage with respect to the dose can be increased.
In addition, since the electric field strength is reduced, a high breakdown voltage can be secured with a short edge structure, and the chip size can be reduced.
As a result, it is possible to manufacture a semiconductor device (for example, a partial SOI power IC) using a partial SOI having a higher breakdown voltage at a lower cost than conventional ones.

  Embodiments will be described in the following examples. Here, the first conductivity type is n-type and the second conductivity type is p-type. In the following description, the same parts as those shown in the background art are denoted by the same reference numerals.

FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. This semiconductor device is a vertical diode, and its edge structure 28 has a p ⁻ buried region 3 and a box layer 4. The edge structure 28 of the present invention is not limited to a vertical diode, but is also used for a vertical power device having a control electrode such as a vertical IGBT and a vertical MOSFET.
An n ⁻ drift layer 2 is formed in contact with an n ⁺ layer 1 which is a support substrate (n ⁺ semiconductor substrate). the n ^- have Box layer 4 is formed in contact drift layer 2, further the n ^- is the layer 5 is formed ^- on the drift layer 2 and the Box layer 4 is n. The Box layer 4 is opened near the active region 27 and the n ⁺ stopper region 8. A p ⁻ buried region 3 is formed in contact with the Box layer 4 at the end of the Box layer 4 on the active region 27 side. A p ⁻ anode region 6 and a p ⁺ anode region 10 are formed on the surface layer of the n ⁻ layer 5 in the active region 27, and the p ⁻ resurf region 7 is formed on the surface layer of the n ⁻ layer 5 on the Box layer 4. Is formed.

An n ⁺ stopper region 8 is formed at the end of the n ⁻ layer 5 on the scribe line side (the end of the semiconductor chip at the right end in the figure). A thermal oxide film 9 and a CVD oxide film 11 are formed on the n ⁻ layer 5 of the edge structure 28 and formed in contact with the anode electrode 12 formed in contact with the p ⁺ anode region 10 and the n ⁺ stopper region 8. The electrodes 13 to be formed are formed so as to overhang the CVD oxide film 11 and have a function as a field plate. The anode electrode 12 is preferably formed so as to protrude above the p ⁻ RESURF region 7. The electrode 13 may be formed so as to extend over the Box layer 4. A cathode electrode 14 is formed in contact with the n ⁺ layer 1 which is a semiconductor substrate. In the figure, A is an anode terminal and K is a cathode terminal.
The Box layer 4 is a region for promoting the spread of the depletion layer when the device is turned off. Also, the Box layer 4 is formed in a part of the edge structure 28, so that the depletion layer spreads more than the formed layer. Can be bigger. Further, the electric field tends to concentrate on the boundary between the p ⁻ anode region 6 and the resurf region 7 at the boundary between the RESURF region 7 and the n ⁻ layer 5 and the boundary between the p ⁺ anode region 10 and the p ⁻ anode region 6. It is desirable to form the Box layer 4 in a region including the lower part of the substrate.

An example of specifications (parameters) of the vertical diode will be described. Using this parameter, a breakdown voltage simulation described later was performed.
The n ⁺ layer 1 has an impurity concentration of 2 × 10 ²⁰ cm ⁻³ and a thickness of 200 μm, the n ⁻ drift layer 2 has an impurity concentration of 2 × 10 ¹⁴ cm ⁻³ and a thickness of 60 μm, and the Box layer 4 has a thickness of 1 μm. The length of the box layer 4 on the scribe line side is 3 μm, the impurity concentration of the n ⁻ layer 5 is 2 × 10 ¹⁴ cm ⁻³ , the thickness is 5 μm, and is in contact with the end of the box layer 4. The dose of the p ⁻ buried region 3 is 1.5 × 10 ¹² cm ⁻² , the width is 10 μm, the dose of the p ⁻ anode region 6 is 1.5 × 10 ¹³ cm ⁻² , the depth is 1 μm, and the p ⁺ anode dose 3 × 10 ¹⁵ cm ^-2 in the region 10, depth 0.3 [mu] m, p ^- RESURF region 7 a dose of 2 × 10 ¹² cm ^-2, depth 1 [mu] m, the dose of the n ⁺ stopper region 8 amount 1 × 10 ¹⁵ cm ^-2, is 4μm deep, the thickness of the thermal oxide film 9 is 0.6 .mu.m, the thickness of the CVD oxide film 11 0. [mu] m, 1 [mu] m film thickness of the anode electrode 12, projecting distance 15μm to CVD oxide film 11 on a film thickness of the electrode 13 is 1 [mu] m, p ⁺ anode region 10 ends and the n ⁺ stopper region 8 end distance (Box The length of the layer 4) is 60 μm.

When the breakdown voltage between the anode and cathode of this vertical diode is calculated by simulation, 615 V is obtained. As described above, this is about 1.1 times the breakdown voltage of the edge structure of FIG. 31 that does not include the p ⁻ buried region 3.
2A and 2B are simulation diagrams performed using the above-described specifications. FIG. 2A is a potential distribution diagram of the structure of FIG. 1, and FIG. 2B is a diagram illustrating the p ⁻ buried region 3 shown in FIG. It is a potential distribution diagram of a conventional structure not including. The application condition is when 500 V is applied between the anode and the cathode. Further, the structure of FIG. 31 is a structure in which the p ⁻ buried region 3 is removed from the structure of FIG. 1, and each specification used in the simulation is the same as the structure of FIG.
In the potential distribution of FIG. 31 shown in FIG. 2B, the isobars of the potential distribution are dense near the end of the Box layer 4 and the electric field becomes high, whereas the p ⁻ buried shown in FIG. In the potential distribution of the structure of the present invention including the region 3, the electric field concentration is relaxed by the effect of the p ⁻ buried region 3.

FIG. 3 is a diagram showing the relationship between the dose of boron in the p ⁻ resurf region 7 and the breakdown voltage in the RESURF structure. In the figure, (1) is the breakdown voltage in the case of the present invention having the p ⁻ buried region 3, and (2) is the breakdown voltage in the conventional case without the p ⁻ buried region 3.
The peak of the breakdown voltage (1) in the product of the present invention having the p ⁻ buried region 3 is higher than the breakdown voltage (2) due to the effect of electric field relaxation by the p ⁻ buried region 3 at the end of the Box layer 4. In the case of the withstand voltage (1), the dose dependency of the withstand voltage is smaller in the vicinity of the peak, and the withstand voltage variation with respect to the dose is smaller.
By providing the p ⁻ buried region 3 in this way, the electric field concentration is alleviated and a high breakdown voltage can be secured.
Further, since the electric field concentration is alleviated, the withstand voltage can be ensured even when the length of the edge structure 28 is shortened, so that the chip size can be reduced.

Further, by projecting the anode electrode 12 of the diode over the p ⁻ RESURF region 7 and acting as a field plate, the electric field concentration on the anode side is alleviated and the breakdown voltage can be improved.
Further, by providing the n ⁺ stopper region 8, the depletion layer extending from the pn junction between the p ⁻ anode region 6 and the n ⁻ layer 5 is formed on the scribe line (end of the semiconductor chip) by the voltage applied between the cathode and anode. The leakage current can be suppressed to be small.
Next, a method for manufacturing the semiconductor device of FIG. 1 will be described.
4 to 11 are views for explaining a method of manufacturing the semiconductor device of FIG. 1, and are cross-sectional views of main part manufacturing steps shown in the order of steps. Here, a case where a partial SOI substrate formed by lateral epitaxial growth is used will be described.

First, the n ⁻ drift layer 2 is formed by epitaxial growth in the vertical direction in contact with the n ⁺ layer 1 which is a support substrate (n ⁺ semiconductor substrate). The concentration and thickness of each region are 2 × 10 ²⁰ cm ⁻³ and 200 μm for the n ⁺ layer 1 and 2 × 10 ¹⁴ cm ⁻³ and 60 μm for the n ⁻ drift layer 2 (FIG. 4). When manufacturing an IGBT, a p ⁺ type support substrate is used. In addition to this method, the n ⁺ layer 1 can also be formed by ion implantation of n-type impurities into a semiconductor substrate such as an FZ wafer and heat treatment. In this case, when manufacturing an IGBT, a p ⁺ layer is formed by ion implantation of p-type impurities and heat treatment.
Next, the p ⁻ buried region 3 is formed in the surface layer of the n ⁻ drift layer 2 by selective ion implantation and heat treatment. For example, the dose is 1.5 × 10 ¹² cm ² in boron (FIG. 5).
Next, an oxide film (thermal oxide film) is grown by 1 μm on the surfaces of the n ⁻ drift layer 2 and the p ⁻ buried region 3, and the oxide film is opened by selective etching (FIG. 6).

Next, an n ⁻ layer 5 is grown on the Box layer 4 by lateral epitaxial growth from the opening (FIG. 7).
Next, after continuous lateral epitaxial growth, the surface is polished and flattened to form an n ⁻ layer 5 which is an SOI layer with good crystallinity. The doping concentration of the n ⁻ layer 5 is 2 × 10 ¹⁴ cm ⁻³ (FIG. 8).
Next, the p ⁻ anode region 6, the p ⁻ resurf region 7 and the n ⁺ stopper region 8 are formed on the surface layer of the n ⁻ layer 5 by selective ion implantation and heat treatment. The ion implantation is performed, for example, when the p ⁻ anode region 6 is boron and the dose is 1.5 × 10 ¹³ cm ⁻² , the p ⁻ resurf region 7 is boron and 1.6 × 10 ¹² cm ⁻² and the n ⁺ stopper region 8 is phosphorus. At a dose of 1 × 10 ¹⁵ cm ⁻² (FIG. 9).

Next, a thermal oxide film 9 having a thickness of 0.6 μm is formed, and then selectively etched to form contact holes. Subsequently, BF ₂ is ion-implanted into the p ⁻ anode region 6 at a dose of about 3 × 10 ¹⁵ cm ⁻² to form the p ⁺ anode region 10 (FIG. 10).
Next, a CVD oxide film 11 is formed as an interlayer insulating film by an HTO (High Temperature Oxide) film, which is formed at about 800 ° C., for example, by 0.2 μm, and a BPSG (Boro-Phospho Silicate Glass) film is 0.7 μm. After the growth, reflow treatment is performed, and then contact holes are formed. Finally, the cathode electrode 14 is formed in contact with the anode electrode 12, the electrode 13 and the n ⁺ layer 1 (FIG. 11).
Incidentally, the above p ^- buried layer 3 is formed in contact with the end portion of the Box layer 4, apart from the end portion, it is formed below the Box layer 4 p ^- the breakdown voltage compared with the case where there is no buried layer 3 Will improve. Further, although not shown, as a partial SOI substrate, a bonded SOI substrate is used and penetrates the bonded oxide film from one semiconductor substrate (SOI layer) of the bonded SOI substrate to the other semiconductor substrate (lower). It is also possible to use an opening that reaches the opening and is filled with an epitaxial layer.

FIG. 12 is a fragmentary cross-sectional view of the semiconductor device according to the second embodiment of the present invention. This is a cross-sectional view corresponding to FIG. The main difference from FIG. 1 is that the oxide film of the partial SOI substrate is formed by a SIMOX (Separation by IMplanted Oxygen) method in which oxygen is ion-implanted into the semiconductor substrate. Next, a method for manufacturing the semiconductor device of FIG. 12 will be described.
13 to 20 are views for explaining a method of manufacturing the semiconductor device of FIG. 12, and are cross-sectional views of main part manufacturing steps shown in the order of steps.
As in FIG. 4, an n ⁺ layer 1 and an n ⁻ drift layer 2 are formed (FIG. 13).
Next, boron is selectively ion-implanted using the resist mask 15 to form the p ⁻ buried region 3. Here, the ion implantation conditions are, for example, 80 keV and a dose amount of 1.5 × 10 ¹² cm ⁻² (FIG. 14).

Next, after the heat treatment is performed to form the p ⁻ buried region 3, the resist mask 15 is removed. A patterned mask oxide film 16 is formed again. Using this mask oxide film 16, oxygen ion implantation with an acceleration energy of 180 keV and a dose of 2 × 10 ¹⁸ cm ⁻² is applied to the p ⁻ buried layer 3 and the n ⁻ drift layer 2, and heat treatment is performed at about 1300 ° C. A Box layer 4 having a thickness of 5 μm is formed (FIG. 15).
Next, the mask oxide film 16 is removed (FIG. 16).
Next, the n ⁻ layer 5 is formed by longitudinal epitaxial growth (FIG. 17).
The subsequent manufacturing steps shown in FIGS. 18 to 20 are the same as those shown in FIGS.
In the semiconductor device of FIG. 12 manufactured in this way, the shape of the p ⁻ buried region 3 and the thickness of the Box layer 4 of the semiconductor device of FIG. 1 are different, but the breakdown voltage is almost the same as the breakdown voltage of the semiconductor device of FIG. was gotten.

FIG. 21 is a fragmentary cross-sectional view of the semiconductor device according to the third embodiment of the present invention. This is a cross-sectional view corresponding to FIG.
Figure 1 is different from, p ^- p instead of RESURF region 7 ^- in that to form the guard ring region 17.
FIG. 22 is a simulation diagram in the case where the p ⁻ guard ring region 17 is present. FIG. 22A is a potential distribution diagram of the structure of FIG. 21, and FIG. 22B is a potential diagram of the conventional structure of FIG. It is a distribution map. FIG. 5B shows a case where the p ⁻ buried region 3 and the box layer 4 having the structure shown in FIG. The application condition is when 500 V is applied between the anode and the cathode. The boron dose in the p ⁻ guard ring region 17 is 1.8 × 10 ¹² cm ⁻² .
In FIG. 22 (b), the isobaric lines of the potential distribution become dense at the portion corresponding to the p ⁻ buried layer 3 in FIG. 21, the maximum portion of impact ionization occurs in the surface layer, and the electric field concentration increases. In FIG. 22A, the electric field concentration is alleviated by the effect of the p ⁻ buried region 3.

FIG. 23 is a diagram showing the relationship between the boron dose in the p ⁻ guard ring region 17 and the breakdown voltage in the guard ring structure. In the figure, (3) is a breakdown voltage in the case of the present invention having the Box layer 4 and the p ⁻ buried region 3, (4) is a breakdown voltage in the conventional case having the Box layer 4 and no p ⁻ buried region 3, (5) Is the breakdown voltage in the conventional case without the Box layer 4 and the p ⁻ buried region 3.
In addition, the withstand voltage peak in (3) is 0.99 times the withstand voltage peak in (1) of FIG. 3, and the withstand voltage peak shows the same value. As for the dose dependency of the withstand voltage, the upward slope of the withstand voltage curve is about the same as (1) in FIG. 3, and the withstand voltage variation with respect to the dose is small and good. In addition, the boron dose at which the breakdown voltage peaks is higher in the p ⁻ guard ring region 17 than in the p ⁻ resurf region 7. Therefore, even when the dose amount at the time of ion implantation varies, the guard ring structure can reduce the breakdown voltage variation smaller than the RESURF structure.

24A and 24B are configuration diagrams of a semiconductor device according to a fourth embodiment of the present invention, in which FIG. 24A is a plan view of an essential part, and FIG. 24B is cut along line XX in FIG. It is principal part sectional drawing. This semiconductor device is a vertical IGBT, which is an example in which an edge structure 78 having a Box layer 55 is applied to a partial SOI IGBT.
In FIG. 2A, the active region 77 and the control circuit region 83 are surrounded by a trench 71, and an edge structure 78 is formed outside the trench 71. Reference numeral 79 in the figure denotes a scribe line.
In FIG. 2B, an n-type buffer layer 52 is formed on a p-type semiconductor support substrate 51 by epitaxial growth. In order to show that the semiconductor support substrate 51 is particularly thicker than the other layers, the semiconductor support substrate 51 is divided into two parts in the vertical direction. An n-type drift layer 53 having a higher resistivity than the buffer layer 52 is formed on the n-type buffer layer 52 by epitaxial growth. In addition, the buffer layer 5 may be formed on one surface of an n-type semiconductor substrate by ion implantation and heat treatment.

A Box layer 55 is formed in contact with the drift layer 53, and an n-type semiconductor layer 57 is formed on the Box layer 55. The Box layer 55 is opened at a part of the active region 77 and a portion of the edge region 78 near the scribe line 79. N-type connection regions 56 and 75 are formed in the opening so as to connect the drift layer 53 and the semiconductor layer 57. The impurity concentration in the connection regions 56 and 75 can be controlled by controlling the supply amount of impurities during epitaxial growth.
A p-type semiconductor region 54 is formed on the surface of the drift layer 53 between the connection regions 56 and 75 so as to be in contact with a part of the Box layer 55. An n-type stopper region 74 is formed in the surface layer of the drift layer 53 at the end of the edge structure 78 on the scribe line 79 side.
An n-type stopper region 76 is formed at the end of the edge structure 78 on the scribe line 79 side of the surface layer of the semiconductor layer 57. By connecting the stopper region 74 and the stopper region 76 via the connection region 75, it is possible to prevent a depletion layer (not shown) formed in the semiconductor layer 57 and the drift layer 53 from reaching the scribe line 79.

A p-type body region 58 is formed in the surface layer of the semiconductor layer 57 between the connection region 56 and the stopper region 76, and a high-concentration p-type body contact region is formed in the surface layer of the body region 58. 64 is formed. Body region 58 and body contact region 64 are separated by isolation trench 71 into body region 58 and body contact region 64 in active region 77 and edge structure 78, respectively.
The layers up to the semiconductor layer 57 can be formed in the same manner as in the first embodiment except that the stopper region 74 is formed either before or after the formation of the buried region 54.
After forming the semiconductor layer 57, the isolation trench 71 is formed, and the sidewall insulating film 69 and the polysilicon 70 are formed. After forming the HTO film 80, the body region 58, the RESURF region 73, and the stopper region 76 are formed.

A high-concentration n-type emitter region 63 is formed on the surface of the body region 58 in the active region 77. A polysilicon gate electrode 61 is formed on the body region 58 sandwiched between the emitter region 63 and the semiconductor layer 57 via a gate insulating film 60. A spacer oxide film 62 is formed on the side wall of the gate electrode 61, and p-type impurity ions enter the channel region (surface layer of the body region 58) under the gate electrode 61 when the body contact region 64 is formed by ion implantation. It has a unique structure. The body contact region 64 is formed so as to cover a part of the bottom of the emitter region 63.
A p-type semiconductor region 73 (corresponding to a p ⁻ RESURF region) is formed in the surface layer of the semiconductor layer 57 between the body region 58 and the stopper region 76 in the edge structure 78. FIG. 24B shows an example in which the body region 58 and the semiconductor region 73 are connected. A LOCOS (Local Oxidation of Silicon) oxide film 59 is formed on the semiconductor layer 57, the p-type semiconductor region 73, the body region 58, and the stopper region 76, and a CVD oxide film 67 is formed thereon. ing.

A barrier metal layer 66 made of Ti / Ni is formed in contact with the emitter region 63 and the body contact region 64. An emitter electrode 65 made of an aluminum alloy is formed on the barrier metal layer 66. Further, a collector electrode 68 is formed in contact with the semiconductor support substrate 51 which is a collector layer.
A Box layer 55 is formed so as to cover the lower portion of the body region 58 in the active region 77. Thereby, since the holes injected from the collector electrode are controlled to flow from the drift layer 53 to the semiconductor layer 57 when the device is in the ON state, the latch-up resistance and avalanche resistance of the element are improved.
As described above, the Box layer 55 extending from the active region 77 is provided in the edge structure 78, and the p-type semiconductor region 54 is formed so as to be in contact with the Box layer 55 across the active region 77 and the edge structure 78. And a high breakdown voltage can be secured even if the length of the edge structure 78 is shortened.

An example of specifications of the vertical IGBT will be described. The semiconductor support substrate 51 has a doping concentration of 2 × 10 ²⁰ cm ⁻³ , a thickness of 200 μm, the buffer layer 52 has a doping concentration of 5 × 10 ¹⁶ cm ⁻³ , a thickness of 4 μm, and the drift layer 53 has a doping concentration of 2 ×. 10 ¹⁴ cm ⁻³ , thickness 60 μm, semiconductor region 54 surface doping concentration 1 × 10 ¹⁷ cm ⁻³ , depth 1 μm, connection regions 56 and 75 doping 2 × 10 ¹⁴ cm ⁻³ , opening width Both are 3 μm, the thickness of the Box layer 55 is 1 μm, the doping concentration of the semiconductor layer 57 is 2 × 10 ¹⁴ cm ⁻³ , the thickness is 55 μm, the doping concentration of the surface of the body region 58 is 2 × 10 ¹⁶ cm ⁻³ , the gate 20nm film thickness of the insulating film 60, the interval 1μm connection region 56 and the semiconductor region 54, both surface doping concentration channel stopper layer 74, 76 is 1 × 10 ¹⁹ cm ^-3, the diffusion depth is 55 .mu.m, semiconducting Region 23 surface doping concentration of 2 × 10 ¹⁶ cm ^-3, is 1μm deep, LOCOS oxide film 59 has a thickness 0.5 [mu] m, CVD oxide film 67 is a film thickness 1.0 .mu.m. The distance between the body contact region 64 in the edge region 78 and the scribe line 79 is 60 μm.

When the breakdown voltage between the emitter and the collector of the partial SOI type IGBT was calculated, a breakdown voltage of 627 V was obtained in the structure of the present invention in FIG. 24, and a breakdown voltage of 530 V was obtained in the conventional structure in FIG. 33 without the box layer 55 in the edge structure 78. The structure of FIG. 33 is different from the structure of FIG. 24 in that the p-type semiconductor regions 73 are discrete and have a guard ring structure, and there is no box layer 55 in the edge structure 78. 25 is a simulation diagram, FIG. 25A is a potential distribution diagram of the structure of the present invention in FIG. 24, and FIG. 25B is a potential distribution of the conventional structure in FIG. FIG. The application condition is when 500 V is applied between the emitter electrode 65 and the collector electrode 68.
In FIG. 6B, the electric field increases at a position indicated by an arrow near the end of the Box layer 55 in the active region 77, whereas in FIG. Are continuously formed in the edge structure 78, the potential distribution is kept relatively uniform, and a higher breakdown voltage can be obtained.

FIG. 26 is a diagram showing the relationship between the emitter-collector breakdown voltage and the dose amount of the p-type semiconductor region 73. The vertical axis represents the breakdown voltage normalized based on the maximum breakdown voltage of the structure of FIG. (6) in the figure is the breakdown voltage in the case of the structure of the present invention in FIG. 24, (7) is the breakdown voltage in the case where the p-type semiconductor region 54 in contact with the box layer 55 is removed from the structure in FIG. ) Shows the breakdown voltage in the case of the conventional structure of FIG.
As shown in FIG. 26, the breakdown voltage peak of (6) is higher than the breakdown voltage peaks of (7) and (8).
However, in the breakdown voltage curve of (6), optimization of the dose amount is important for manufacturing because the breakdown voltage sharply decreases at a dose amount higher than the dose amount of the p-type semiconductor region 73 showing the peak of the breakdown voltage.

The reason why the breakdown voltage peak of (6) is higher than the breakdown voltage peak of (7) is that the electric field is relaxed by the effect of the p-type semiconductor region 54.
Since the electric field is relaxed, the edge structure 78 can be shortened, and the chip size can be reduced.

FIG. 27 is a fragmentary cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention. The plan view is the same as FIG.
The difference from FIG. 24 is that the end portion on the active region 77 side of the Box layer 55 is formed so as to be covered with the p-type semiconductor region 54.
FIG. 28 is a diagram showing the relationship between the boron dose in the p-type semiconductor region 73 and the breakdown voltage in the structure of FIG. (9) in the figure is the breakdown voltage of the structure of FIG. 27. The breakdown voltage peak of (9) is about the same as the breakdown voltage peak of (6) of FIG. It has been eased. Comparing the withstand voltage curve with respect to the dose amount of (9) in FIG. 28 and the withstand voltage curve with respect to the dose amount of FIG. 26 (6), the withstand voltage of (9) is the withstand voltage of FIG. It can be seen that it can be higher. Further, since the upward slope of the withstand voltage curve with respect to the dose amount can be made gentler in (9) than in (6), variation in withstand voltage due to variation in dose amount can be suppressed from the structure of FIG.

  The structure of FIG. 27 can be formed by expanding the range of the connection region 56 to the scribe line 79 side and expanding the range of the p-type semiconductor region 54 to the connection region 56 in the structure of FIG.

FIG. 29 is a fragmentary cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention. The plan view is almost the same as FIG. The difference from FIG. 24 is that the edge structure 78 is divided by the trench 81.
This is the structure of FIG. 24, and when a lateral epitaxial growth layer is formed, even if a crystal defect occurs at the central location where the epitaxial layer (semiconductor layer 57) growing from the left and right meets, the location is excavated by the trench 81. By removing the defective portion and using the trench 81 as an insulating isolation region, the defect in the edge structure 78 is removed, and a high breakdown voltage can be secured.
In the above embodiment, the case where the RESURF regions 7 and 73 or the guard ring region 17 are formed in the edge structures 28 and 78 has been described. However, even when the RESURF regions 7 and 73 or the guard ring region 17 is not formed, the Box 4 55 and the buried regions 3 and 53 are formed, the above-described effects can be obtained.

Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. FIG. 3 is a diagram showing a potential distribution when 500 V is applied between an anode and a cathode, (a) is a diagram in the case of the structure of the present invention of FIG. 1, and (b) is a conventional one not including the p ⁻ buried layer of FIG. Illustration for structure Diagram showing the relationship between breakdown voltage and borondose amount in RESURF structure Cross-sectional view of the main part manufacturing process of the semiconductor device of the first embodiment FIG. 4 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the first embodiment, following FIG. FIG. 5 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the first embodiment, following FIG. FIG. 6 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the first embodiment, following FIG. FIG. 7 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the first embodiment, following FIG. FIG. 8 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the first embodiment, following FIG. FIG. 9 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the first embodiment, following FIG. FIG. 10 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the first embodiment, following FIG. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional view of manufacturing process of main part of semiconductor device of second embodiment FIG. 13 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the second embodiment, following FIG. FIG. 14 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the second embodiment, following FIG. FIG. 15 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the second embodiment, following FIG. FIG. 16 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the second embodiment, following FIG. FIG. 17 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the second embodiment, following FIG. FIG. 18 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the second embodiment, following FIG. FIG. 19 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the second embodiment, following FIG. Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. FIG. 22 is a diagram showing a potential distribution when 500 V is applied between the anode and the cathode, (a) is a diagram in the case of the structure of the present invention of FIG. 21, and (b) is a conventional structure without a p ⁻ buried layer and a Box layer. Figure of the case Diagram showing the relationship between breakdown voltage and borondose amount in a guard ring structure It is a block diagram of the semiconductor device of 4th Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). It is a figure which shows electric potential distribution when 500V is applied between an emitter electrode and a collector electrode, (a) is a figure in the case of the structure of this invention of FIG. 24, (b) is in the case of the conventional structure of FIG. Figure Diagram showing the relationship between breakdown voltage and borondose amount Sectional drawing of the principal part of the semiconductor device of 5th Example of this invention FIG. 27 is a diagram showing the relationship between breakdown voltage and borondose amount in the structure of FIG. Sectional drawing of the principal part of the semiconductor device of 6th Example of this invention Cross-sectional view of the main part of a semiconductor device having a conventional edge structure with a guard ring structure and no box layer Cross-sectional view of a principal part of a semiconductor device having a conventional edge structure with a RESURF structure and a box layer The figure which shows the relationship between the withstand voltage and the boron dose in a semiconductor device having a conventional edge structure Sectional view of a main part of a conventional semiconductor device in the case of a guard ring structure with a box layer at the end of the active region and no box layer in the edge structure

Explanation of symbols

1 n ⁺ layer 2 n ^- drift layer 3 p ^- buried region 4 Box layer 5 n ^- layer 6 p ^- anode region 7 p ^- RESURF region 8 n ⁺ stopper region 9 72 thermal oxide film 10 p ⁺ anode region 11,67 CVD oxide film 12 anode electrode 13 electrode 14 cathode electrode 15 resist mask 16 mask oxide film 17 p ^- guard ring region 27,77 the active region 28, 78 edge structure 51 semiconductor support substrate 52 the buffer layer 53 drift layer 54 and 73 semiconductor region 55 Box Layers 56 and 75 Connection region 57 Semiconductor layer 58 Body region 59 LOCOS oxide film 60 Gate oxide film 61 Gate electrode 62 Spacer oxide film 63 Emitter region 64 Body contact region 65 Emitter electrode 66 Barrier metal layer 68 Collector electrode 69 Side wall oxide film 70 Poly Silicon 71, 81 Trench 74 76 stopper region 79 scribe line (the edge of the semiconductor chip)
80 HTO layer 83 Control circuit area

Claims (22)

A first conductivity type semiconductor substrate;
A first main electrode formed on the surface of the semiconductor substrate;
A second main electrode formed on the back surface of the semiconductor substrate;
A vertical power device comprising:
A first semiconductor region of a second conductivity type formed in a surface layer of the semiconductor substrate in the active region of the vertical power device and electrically connected to the first main electrode ;
A first conductivity type stopper region formed on the surface layer of the semiconductor substrate having an edge structure surrounding the active region of the vertical power device, separated from the first semiconductor region ;
An oxide film selectively formed inside the semiconductor substrate between the first semiconductor region and the stopper region at a deeper position than the first semiconductor region;
A buried region of a second conductivity type formed in contact with the oxide film;
A vertical power device provided with a semiconductor device. 2. The semiconductor device according to claim 1, wherein the oxide film is formed from a lower portion of an end portion of the first semiconductor region on the stopper region side to a vicinity of the end portion of the semiconductor substrate. The semiconductor device according to claim 1, wherein the buried region is formed at or near an end portion on the first semiconductor region side. Claim 1, characterized in that a second semiconductor region of a second conductivity type formed in the surface layer of said semiconductor substrate between said first semiconductor region and the stopper region The semiconductor device according to one item. The semiconductor device according to claim 4, wherein a plurality of the second semiconductor regions are formed. The semiconductor device according to claim 4, wherein the second semiconductor region is in contact with the first semiconductor region. The oxide film is formed in the semiconductor substrate from a lower portion of the end portion of the first semiconductor region on the second semiconductor region side to a lower portion of the end portion of the second semiconductor region on the stopper region side. The semiconductor device according to claim 4, wherein the semiconductor device is formed. A first trench formed to reach the oxide film from a surface of the semiconductor substrate between the first semiconductor region and the stopper region; and a first trench formed on both side walls of the first trench. and the sidewall insulating films, and the first of the first and the semiconductor region of the second conductivity type formed in the surface layer of the semiconductor substrate opposite the third semiconductor region of the trench, the first semiconductor region a fourth semiconductor region of the first conductivity type formed in the surface layer, is formed through a gate insulating film on a surface of the first semiconductor region between the semiconductor substrate and the fourth semiconductor region A gate electrode,
The semiconductor device according to claim 1, wherein the first main electrode is electrically connected to the third semiconductor region and the fourth semiconductor region. 9. The semiconductor device according to claim 8, wherein the oxide film is formed so as to cover a lower portion of the first semiconductor region. 9. The semiconductor device according to claim 8, wherein the oxide film includes a first opening for flowing a main current and a second opening formed at an end of the semiconductor substrate. It said semiconductor substrate is made of a second semiconductor layer formed thereon with the first semiconductor layer formed on the supporting substrate and the supporting substrate, the oxide film of the first semiconductor layer and the second semiconductor The semiconductor device according to claim 1, wherein the semiconductor device is formed between the layers. Made from a second semiconductor layer in which the semiconductor substrate is a first semiconductor layer formed on the support substrate and the support substrate formed thereon, the oxide film is formed inside the first semiconductor layer The semiconductor device according to claim 1, wherein: The semiconductor device according to claim 11, wherein the support substrate is of a second conductivity type. 13. The semiconductor according to claim 11, further comprising a first conductivity type buffer layer having a lower resistivity than the first semiconductor layer between the support substrate and the first semiconductor layer. apparatus. The semiconductor device according to any one of claims 1 1 to 14, characterized in that it comprises a fifth semiconductor region of the second conductivity type formed on the end surface layer of the first semiconductor layer. The semiconductor substrate comprises a first semiconductor layer and a second semiconductor layer formed thereon, and the oxide film is formed between the first semiconductor layer and the second semiconductor layer. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that: 11. The semiconductor substrate includes a first semiconductor layer and a second semiconductor layer formed thereon, and the oxide film is formed inside the first semiconductor layer. The semiconductor device according to any one of the above. 18. The semiconductor device according to claim 16, further comprising a third semiconductor layer of a second conductivity type formed on a front surface layer of the first semiconductor layer. 18. The semiconductor device according to claim 17, further comprising a buffer layer of the first conductivity type formed on the third semiconductor layer. An isolation oxide film formed simultaneously with the oxide film, a second trench reaching the isolation oxide film from the surface of the semiconductor substrate, and a second sidewall oxide film formed on a sidewall of the second trench The semiconductor device according to claim 8, further comprising an insulating isolation region having at least A method of manufacturing a semiconductor device according to claim 11 or 16,
Selectively forming a second conductivity type first diffusion region in the first conductivity type first semiconductor layer;
Forming an oxide film having first and second openings selectively on the first semiconductor layer including at least part of the first diffusion region;
Forming a second semiconductor layer on the first semiconductor layer and on the oxide film by epitaxial growth from the first and second openings, and a method for manufacturing a semiconductor device . A method of manufacturing a semiconductor device according to claim 12 or 17,
Selectively forming a second conductivity type first diffusion region in the first conductivity type first semiconductor layer;
Forming an oxide film inside the first semiconductor layer by ion implantation and heat treatment selectively in the first semiconductor layer including at least a part of the first diffusion region; and
Forming a second semiconductor layer by epitaxial growth on the first semiconductor layer;
A method for manufacturing a semiconductor device, comprising:

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