JP5051293B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor substrate that is generally used for semiconductor devices including composite ICs and LSIs.

An SOI (silicon on insulator) semiconductor device in which a semiconductor layer is disposed on a semiconductor substrate through an intermediate insulating film is a device in which a plurality of types of elements such as bipolar, MOS, and power elements are mounted on one chip, for example, a composite It is suitable for use in ICs, high voltage ICs, and LSIs for portable devices that require high speed and low power consumption. In order to manufacture an SOI semiconductor device, a so-called SOI substrate in which a high-quality crystalline semiconductor layer is formed on a very high resistance layer made of an insulator such as SiO ₂ is required as a substrate. Conventionally known methods for manufacturing such an SOI substrate include a bonding method, a SIMOX method, a method using a combination of hydrogen embrittlement and bonding and ion implantation, and the like.

  However, the SOI substrate manufactured by the conventional technique is several to several tens of times more expensive than any ordinary bulk substrate. This has been the biggest factor hindering the practical application of SOI semiconductor devices, despite the high performance and high function in principle.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor substrate suitable for use in a high-quality and inexpensive SOI semiconductor device, instead of a conventional SOI substrate.

In order to achieve the above object, in the invention according to claim 1, a base wafer (61) having at least one main surface mirror-polished and a semiconductor substrate containing a high concentration of oxygen or high resistance and semi-insulating And a step of preparing a bond wafer (62) having at least one main surface thereof mirror-polished, and a step of forming an oxide film (63) on at least one main surface of the base wafer and the bond wafer. When the base wafer and the bond wafer so that each major surface facing, via the oxide film, and forming a bond wafer by bonding the base wafer and the bond wafer (64), the surface of the surface of the bond wafer side of the bonded wafer a step of grinding and mirror polishing to the bond wafer to a predetermined thickness SOI layer, further, heat-treated at a high temperature in a hydrogen atmosphere The Rukoto, oxygen on the surface of the SOI layer is out-diffused, is characterized in that it includes the steps of forming a gettering site leaving oxygen at the interface between the SOI layer and the oxide film (63), the.

In this way, it is possible to use a high resistance or semi-insulating substrate for the bond wafer. In this case, it is possible to obtain an SOI substrate in which a gettering site is formed at the interface between the SOI layer and the oxide film (63) by forming an SOI layer with a bond wafer and diffusing oxygen on the surface of the SOI layer outwardly. it can.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

It is a figure which shows the manufacturing process of the semiconductor substrate for SOI semiconductor devices in 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor substrate for SOI semiconductor devices in 2nd Embodiment of this invention. It is a figure which shows the relationship between hFE of a parasitic transistor, and the lifetime of a minority carrier. It is a figure which shows the manufacturing process of the semiconductor substrate for SOI semiconductor devices in 3rd Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor substrate for SOI semiconductor devices in 4th Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor substrate for SOI semiconductor devices in 5th Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor substrate for SOI semiconductor devices in 6th Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor substrate for SOI semiconductor devices in 7th Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor substrate for SOI semiconductor devices in 8th Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor substrate for SOI semiconductor devices in 9th Embodiment of this invention. It is sectional drawing which shows the example of preparation of the device using the SOI substrate manufactured by the process shown in FIG. It is sectional drawing which shows the case where various insulation isolation | separation structures are formed using the board | substrate manufactured by each embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A method of manufacturing a semiconductor substrate for an SOI semiconductor device to which the first embodiment of the present invention is applied will be described. FIG. 1 shows a manufacturing process of a semiconductor substrate for an SOI semiconductor device according to this embodiment, which will be described below with reference to FIG.

In this embodiment, a high-resistance semiconductor substrate 1 containing a high concentration of interstitial oxygen whose surface is mirror-polished is used as an epitaxial growth substrate. In the silicon single crystal grown by the CZ method, oxygen of about 10 ¹⁸ atoms / cm 3 exists between the lattices. In the present embodiment, however, the interstitial gas having a higher concentration than 2 × 10 ¹⁸ atoms / cm 3, for example. A mirror wafer containing oxygen is used as a starting material. The mirror wafer can be manufactured by the CZ method in the same manner as a normal mirror wafer. In this semiconductor substrate 1, for example, an immersion treatment in SC-1 solution (mixed solution consisting of NH ₄ OH, H ₂ O ₂ , H ₂ O, APM solution), SC-2 solution (HCl, H ₂ O ₂ , After performing a series of pre-cleaning treatments including immersion treatment in a mixed solution of H ₂ O and HPM solution, immersion treatment in dilute HF solution, ultrapure water replacement, and drying, HCl etching, H _The epitaxial layer (semiconductor active layer) 2 is grown as an active layer in accordance with the required thickness by normal epitaxial growth consisting of _two gas replacements.

Thereafter, the semiconductor substrate 1 on which the epitaxial layer 2 is formed is heat-treated in an oxidizing atmosphere at a high temperature of, for example, 1150 ° C. or higher, so that the high-resistance semiconductor substrate 1 containing a high concentration of interstitial oxygen is contained. Oxygen is deposited using a strained layer at the interface of the epitaxial layer 2 / semiconductor substrate 1 as a nucleus. As a result, a layered region (oxide film) 3 of SiO ₂ is formed at the interface between the epitaxial layer 2 and the semiconductor substrate 1 to form an SOI structure. The layered region 3 of SiO ₂ formed at the interface is about several hundred nm, but since the semiconductor substrate 1 used has a high resistance, the elements are electrically insulated and separated by using it together with trench isolation or the like. Therefore, performance equivalent to that of a normal SOI substrate can be realized.

According to the method for manufacturing a semiconductor substrate for an SOI semiconductor shown in this embodiment, compared to a conventional bonding method, two mirror wafers for bonding are prepared, two mirror wafers are bonded, and a bonding heat treatment is performed. In addition, it is possible to eliminate the need for many inspection processes such as edge processing, surface grinding, re-mirror polishing, and voids, SOI thickness, etc. to obtain the required SOI thickness, and a significant cost reduction can be achieved. . Compared with the SIMOX method, the SIMOX method requires oxygen to be implanted into the semiconductor substrate at a high concentration (1 × 10 ¹⁸ cm ⁻³ ) with high energy, so that an expensive apparatus is required and throughput is increased. In contrast to this, in this embodiment, a semiconductor substrate containing a high concentration of interstitial oxygen is used, a normal epitaxial growth is performed for forming an active layer, and a layered state of SiO ₂ is obtained only by heat treatment in an oxidizing atmosphere. Since the region 3 can be formed, significant cost reduction can be achieved.

(Second Embodiment)
FIG. 2 shows a second embodiment of the present invention. In this embodiment, a semi-insulating semiconductor substrate 11 is used instead of the semiconductor substrate 1 used in the first embodiment. As described above, the semi-insulating semiconductor substrate 11 may be used, and the epitaxial layer 12 may be formed on the semiconductor substrate 11 as in the first embodiment. In this way, a pseudo SOI structure can be formed without performing high-temperature oxygen precipitation heat treatment in an oxidizing atmosphere after the epitaxial layer 12 is formed.

As the semi-insulating semiconductor substrate 11 shown here, for example, a substrate having a minority carrier lifetime of 1 × 10 ⁻⁸ sec or less can be used. This is because, when elements are formed on the semiconductor substrate 11 and the epitaxial layer 12 having the structure shown in the present embodiment, the hFE of the parasitic transistor formed by the impurity layer provided in adjacent cells and the semiconductor substrate 11 This is because the relationship with the minority carrier lifetime is shown in FIG. That is, as shown in FIG. 3, it can be said that hFE of the parasitic transistor is preferably 10 ⁻¹ or less in order to make the influence of the parasitic transistor sufficiently small, but τg which is the lifetime of minority carriers is 10 When it becomes ^-8 or less, hFE of the parasitic transistor becomes 10 ^-1 or less. For this reason, it sets so that the lifetime of a minority carrier may become the said value.

The carrier concentration of the semiconductor substrate 11 is not particularly limited, and may be 1 × 10 ¹⁴ cm ⁻³ or less, for example.

  As the semi-insulating semiconductor substrate 11, for example, a substrate containing an impurity that forms a deep trap level in a band gap such as high-concentration interstitial oxygen or carbon can be used.

(Third embodiment)
FIG. 4 shows a third embodiment of the present invention. In this embodiment, instead of the semiconductor substrate 11 used in the second embodiment, a semi-insulating substrate 21 to which a dopant having a conductivity type opposite to that of the epitaxial layer 22 is added is used. That is, as shown in the figure, when the epitaxial layer 22 is n-type, a p-type substrate is used as the semiconductor substrate 21, and when the epitaxial layer 22 is p-type, the semiconductor substrate 21 is n-type. A substrate is used. By doing so, a PN junction is formed between the formed epitaxial layer 22 and the semiconductor substrate 21, so that more reliable electrical separation can be achieved than in the second embodiment.

  In the case of forming a PN junction as in this embodiment, a high breakdown voltage can be achieved by setting the carrier concentration low as described above.

(Fourth embodiment)
FIG. 5 shows a fourth embodiment of the present invention. In the present embodiment, as in the first to third embodiments, a high-resistance semiconductor substrate or semi-insulating substrate containing a high concentration of interstitial oxygen is used as the semiconductor substrate 31 (FIG. 5A). The substrate 31 is subjected to high-temperature heat treatment at 1000 ° C. or higher in hydrogen before epitaxial growth. By doing so, either or both of interstitial oxygen atoms contained in the substrate diffuse out and escape from the substrate top surface, or atoms on the substrate top surface rearrange. As a result, a layer 32 is formed on the substrate surface by oxygen outward diffusion or atomic rearrangement (FIG. 5B), and the crystal quality of the substrate surface is improved. Therefore, the crystallinity of the epitaxial layer 33 (FIG. 5C) to be formed can be further improved thereafter.

(Fifth embodiment)
FIG. 6 shows a fifth embodiment of the present invention. Of the steps shown in FIG. 6, the steps shown in FIGS. 6A to 6C are the same as the steps shown in FIGS. 5A to 5C, respectively. In the present embodiment, the epitaxially grown substrate prepared by the method shown in the fourth embodiment is heat-treated in an oxidizing atmosphere at a high temperature of, for example, 1150 ° C. or higher (FIG. 6D), so that high interstitial oxygen can be produced. A layered region 34 of SiO ₂ is deposited with oxygen contained in the high-resistance semiconductor substrate 31 containing the strained layer at the epitaxial growth layer / substrate interface as a nucleus to form an SOI structure.

As described above, the SiO ₂ layered region 3 can be formed as in the first embodiment by further performing heat treatment in an oxidizing atmosphere on the fourth embodiment.

(Sixth embodiment)
FIG. 7 shows a sixth embodiment of the present invention. In the present embodiment, as in the first to third embodiments, a high-resistance semiconductor substrate or semi-insulating substrate containing a high concentration of interstitial oxygen is used as the semiconductor substrate 41 (FIG. 7A). A thin semiconductor layer 42 having a conductivity type opposite to that of the epitaxial layer 43 as an active layer formed in the process is epitaxially grown (FIG. 7B), and then the epitaxial layer 43 is epitaxially grown (FIG. 7C). For example, if the active layer (epitaxial layer 43) is an n ⁻ type layer, the semiconductor layer 42 is a p ⁻ type layer.

  According to such a manufacturing method, the semiconductor layer 42 having a conductivity type opposite to that of the active layer formed at the interface between the semiconductor substrate 41 and the epitaxial layer 43 is completely depleted together with the underlying high-resistance semiconductor substrate 41. As a result of acting as a voltage support and isolation, it acts as a pseudo SOI structure. Of course, as in the first embodiment, the oxide layer may be deposited by performing a heat treatment in a high-temperature oxidizing atmosphere.

(Seventh embodiment)
FIG. 8 shows a seventh embodiment of the present invention. In the present embodiment, before the epitaxial growth in the middle of the sixth embodiment, the process shown in FIG. 5B is performed on the semiconductor substrate 41 to be used, as in the fourth and fifth embodiments. That is, high temperature heat treatment at 1000 ° C. or higher is performed in hydrogen. By doing so, either interstitial oxygen atoms contained in the semiconductor substrate 41 are diffused outward and escape from the outermost surface of the substrate, or atoms on the outermost surface of the substrate cause rearrangement. Alternatively, both occur, and a layer 44 is formed on the substrate surface by oxygen out-diffusion or atomic rearrangement (FIG. 8B), and the crystal quality of the substrate surface is improved.

  After that, as shown in FIGS. 8C and 8D, the pseudo SOI structure is configured by performing the same processes as those shown in FIGS. 7B and 7C. Also in this embodiment, heat treatment in a high-temperature oxidizing atmosphere may be performed, and the oxide layer may be deposited as in the fifth embodiment.

(Eighth embodiment)
FIG. 9 shows an eighth embodiment of the present invention. In this embodiment, a high-resistance semiconductor substrate or semi-insulating substrate containing a high concentration of interstitial oxygen as shown in the first to third embodiments is used as a base wafer 51, and a normal mirror wafer is used as a bond wafer 52. (FIG. 9A). Then, an oxide film 53 is formed on the mirror-polished main surface of at least one of the base wafer 51 and the bond wafer 52 (FIG. 9B), and the main surfaces of both wafers are formed using a normal wafer bonding method. They are bonded together in a clean atmosphere and subjected to high-temperature bonding heat treatment to produce a bonded wafer 54 (FIG. 9C).

  Thereafter, the back surface on the bond wafer 52 side of the bonded wafer 54 is made to have a predetermined SOI layer thickness by surface grinding and mirror polishing (FIG. 9D).

  In this embodiment, unlike a conventional bonded wafer manufacturing method, a high-resistance substrate or semi-insulating substrate containing a high concentration of interstitial oxygen is used for the base wafer. A high breakdown voltage SOI substrate having a buried oxide film thickness of about 1/10, for example, of 200 V or more can be realized.

(Ninth embodiment)
FIG. 10 shows a ninth embodiment of the present invention. In this embodiment, a high-resistance semiconductor substrate or semi-insulating substrate containing a high concentration of interstitial oxygen as shown in the first to third embodiments is used as a bond wafer 61, and a normal mirror wafer is used as a base wafer 62. (FIG. 10A). Then, an oxide film 63 is formed on the mirror-polished main surface of at least one of the bond wafer 61 and the base wafer 62 (FIG. 10B), and the main surfaces of both wafers using a normal wafer bonding method. They are bonded together in a clean atmosphere and subjected to high-temperature bonding heat treatment to produce a bonded wafer 64 (FIG. 10C).

  Thereafter, the back surface of the bonded wafer 64 on the bond wafer 61 side is made to have a predetermined SOI layer thickness by surface grinding and mirror polishing (FIG. 10D).

  Further, oxygen on the surface of the SOI layer is diffused outward by heat treatment at a high temperature in a hydrogen atmosphere. As a result, oxygen remains at the bonding interface, and a gettering site is formed in this portion (FIG. 10E).

  Thus, when the gettering site is formed in the SOI layer, when the oxide film is formed on the SOI layer, heavy metal contaminants are taken into the gettering site, so that the lifetime of the oxide film is improved. Can do.

  The SOI substrate formed according to the present embodiment is used for forming the device shown in FIG. 11, for example. In this device, an LDMOS 70, a bipolar transistor 80, a CMOS 90, and a diode 100 are formed.

The LDMOS 70 includes a p-type base region 71 formed in the surface layer portion of an n ⁻ -type SOI layer (bond wafer 61), an n ⁺ -type source region 72 formed in the surface layer portion of the p-type base region 71, and a p-type base. An n ⁺ -type drain region 73 formed in the surface layer portion of the SOI layer so as to be separated from the region 71, a gate insulating film 74 formed on at least the p-type base region 71, and formed on the gate insulating film 74. The gate electrode 75, the source electrode 76 electrically connected to the n ⁺ -type source region 72, and the drain electrode 77 connected to the n ⁺ -type drain region 73 are configured.

Bipolar transistor 80 is spaced apart from p-type base region 81, p-type base region 81 formed in the surface layer portion of the SOI layer, n ⁺ -type emitter region 82 formed in the surface layer portion of p-type base region 81. And an n ⁺ -type collector region 83 formed in the surface layer portion of the SOI layer, and a base electrode 84, an emitter electrode 85, and a collector electrode 86 connected to these regions.

The CMOS 90 includes an n-type well layer 91 and a p-type well layer 92 formed on the surface layer portion of the SOI layer, a p ⁺ -type source 93 a and a drain 94 a disposed so as to be separated from each other in the n-type well layer 91, In the p-type well layer 92, n ⁺ -type sources 93b and drains 94b arranged so as to be separated from each other, and gates formed on channel regions formed between the sources 93a, 93b and drains 94a and 94b. Insulating films 95a and 95b, gate electrodes 96a and 96b, and source electrodes 97a and 97b and drain electrodes 98a and 98b connected to the sources 93a and 93b and drains 94a and 94b, respectively.

The diode 100 is connected to the p-type region 101 and the p ⁺ -type contact region 102 formed in the surface layer portion of the SOI layer, the n ⁺ -type region 103 formed so as to be separated from the p-type region 101, and each region. An anode electrode 104 and a cathode electrode 105 are provided.

  Since a gettering site is formed in the SOI layer of the SOI substrate according to this embodiment, the use of the SOI substrate according to this embodiment for forming the LDMOS 70, the CMOS 90, or the diode 100 among the above-described elements has the following effects. Is obtained.

  That is, in the case of an element including the gate insulating films 74, 95a, and 95b such as the LDMOS 70 and the CMOS 90, heavy metal contaminants are taken into the gettering site, so that the lifetime of the gate insulating films 74, 95a, and 95b is increased. Improvement can be achieved and the reliability of the element can be improved.

  Further, when the n-type well layer 91 and the p-type well layer 92 are formed together as in the CMOS 90, it is preferable to separate the layers from the viewpoint of latch-up prevention. In some cases, wrench separation is not performed. Even in such a case, since a gettering site is formed, a latch-up prevention function can be achieved.

In addition, when switching from on to off as in the diode 100, holes injected into the n ⁻ -type SOI layer from the anode return to the anode again, and a reverse current is generated. Becomes a trap site and captures holes, which are recombined with electrons and annihilated, thereby preventing reverse current from being generated. Thereby, the recovery characteristic of the diode 100 can be improved. Although not shown in FIG. 11, a reverse current is also generated in the IGBT due to the same factors as in the diode. Therefore, if the SOI substrate shown in this embodiment is used for forming the IGBT, the recovery characteristics of the IGBT are improved. Improvements can also be made.

(Other embodiments)
In each of the above embodiments, oxygen arranged between the lattices is illustrated. However, since oxygen similar to that described above can be generated by oxygen arranged in other portions, the semiconductor substrates 1 and 21 are particularly preferable. , 31, 41, 51 need not be interstitial oxygen.

  Moreover, in each said embodiment, although the thing with high resistance is used as the semiconductor substrate 1,21,31,41,51, the effect in said each embodiment can be acquired even if it is not restricted to high resistance.

  In the first and fifth embodiments, the case where the oxide layer is deposited by heat treatment in an oxidizing atmosphere has been described. However, other insulating layers can be deposited. For example, a nitride layer or the like can be propagated by using nitrogen or the like partially existing therein as a nucleus, and such an insulating layer can be used instead of an SOI substrate. Therefore, in such a case, it is not essential that the semiconductor substrate contains oxygen.

  Various insulating separation structures can be formed using the substrate formed according to each of the above embodiments. An example of this is shown in FIGS. In this figure, the case where the substrate constituting the PN junction in the third embodiment is used is described as an example, but the same applies to substrates formed in other embodiments.

  For example, as shown in FIG. 12A, a well isolation structure can be formed in which a well layer 110 having a conductivity type opposite to the epitaxial layer 22 is formed in contact with the semi-insulating substrate 21. In addition, as shown in FIG. 12B, a trench 111 reaching the semi-insulating substrate 21 with respect to the epitaxial layer 22 is formed, and a trench isolation structure is formed by embedding the trench 111 with an insulating film 112. it can. As shown in FIG. 12C, a well trench isolation structure combining FIGS. 12A and 12B can be formed. Further, as shown in FIG. 12D, a double trench isolation structure in which two trenches shown in FIG. 12B are adjacent to each other can be formed. Furthermore, as shown in FIG. 12 (e), the region sandwiched between the trenches of the double trench isolation structure is made the well layer 113 of the same conductivity type as the semi-insulating substrate 21, and the well layer 113 is grounded. Thus, it is possible to form a double trench isolation structure capable of parasitic extraction.

1 ... a high-resistance semiconductor substrate, 2 ... epitaxial layer, 3 ... SiO ₂ layered region,
11 ... Semi-insulating semiconductor substrate, 12 ... Epitaxial layer,
21 ... Semiconductor substrate with opposite conductivity type, 22 ... Epitaxial layer.

Claims (1)

A base wafer (61) having at least one main surface mirror-polished and a semiconductor substrate containing high-concentration oxygen or a high-resistance semi-insulating semiconductor substrate, at least one main surface of which is mirror-polished Preparing a bond wafer (62);
Forming an oxide film (63) on at least one main surface of the base wafer and the bond wafer;
Forming the bonded wafer (64) by bonding the base wafer and the bond wafer via the oxide film so that the main surfaces of the base wafer and the bond wafer face each other;
A step of the SOI layer using the bond wafer of a predetermined thickness of the surface of the bond wafer side surface grinding and mirror polishing of the bond wafer,
Furthermore, by heat treatment at a high temperature in a hydrogen atmosphere, the oxygen of the surface of the SOI layer outward by diffusing, forming an interface leaving an oxygen gettering site and the SOI layer and the oxide film (63) A process for producing a semiconductor substrate, comprising:

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