JP5049400B2 - On-glass single-chip LCD - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device liquid crystal having an on-glass single chip that can reduce the defect rate and further reduce the overall size.

  Recently, information processing devices have been rapidly developed to have various forms, various functions, and higher information processing speed. Information processed by such an information processing apparatus has a form of an electric signal. In order for the user to visually confirm the information processed by the information processing device, a display device having an interface function is required.

  Recently, information processing devices have been rapidly developed to have various forms, various functions, and higher information processing speed. Information processed by such an information processing apparatus has a form of an electric signal. In order for the user to visually confirm the information processed by the information processing device, a display device having an interface function is required.

  Recently, development of a liquid crystal display device having functions such as full-color and high resolution while being lighter and smaller than a CRT display device has been progressing.

  Of these liquid crystal display devices, a device having electrodes formed on two substrates and having a thin film transistor for switching a voltage applied to each electrode is mainly used. Thus, a liquid crystal display device using a thin film transistor is classified into an amorphous form and a polycrystalline form.

  The polycrystalline liquid crystal display device has the advantages that the device operation can be speeded up and the device can be driven with low power, while the thin film transistor manufacturing process is complicated. Accordingly, the polycrystalline liquid crystal display device is mainly applied to a small display device, and the amorphous liquid crystal display device is mainly applied to a large screen display device such as a notebook, a PC, an LCD monitor, and an HDTV.

  FIG. 1 is a plan view showing a conventional amorphous liquid crystal display device.

  As shown in FIG. 1, an amorphous liquid crystal display device 50 includes a liquid crystal display panel 10 having a pixel array, driving printed circuit boards 36 and 42 for providing a driving signal to the liquid crystal display panel 10, and the liquid crystal display panel 10. And a tape carrier package (hereinafter referred to as TCP) 32 and 38 for electrically connecting the driving printed circuit boards 36 and 42 to each other.

  The driving printed circuit boards 36 and 42 are a data printing circuit board 36 for driving a plurality of data lines formed on the liquid crystal display panel 10 and a gate printing for driving a plurality of gate lines formed on the liquid crystal display panel 10. A circuit board 42 is included. On the other hand, the data printed circuit board 36 is connected to the plurality of data line terminal portions by the data side TCP 32, and the gate printed circuit board 42 is connected to the plurality of gate line terminal portions by the gate side TCP 38.

  At this time, the data driving chip 34 is formed on the data side TCP 32 in a chip-on-film (hereinafter referred to as COF) system, and the gate driving chip 40 is formed on the gate side flexible circuit board 38 in the COF system. It is formed.

  Recently, even in the case of non-crystalline liquid crystal display devices, there has been a technology development aimed at reducing the number of assembly processes by forming a data driving circuit and a gate driving circuit on a glass substrate of a liquid crystal display panel like a polycrystalline liquid crystal display device. Progressing.

  FIG. 2 is a plan view showing an amorphous liquid crystal display device in which a gate and a data driving circuit are built in a panel.

  As shown in FIG. 2, the amorphous liquid crystal display device 90 includes a glass substrate 60 having a display area 60a on which a pixel array is formed and a peripheral area 60b of the display area. A plurality of data driving chips 61 and gate driving chips 62 are formed in the peripheral region 60b. At this time, output terminals of the plurality of data driving chips 61 are connected to a plurality of data lines, and output terminals of the plurality of gate driving chips 62 are connected to a plurality of gate lines. Input terminals of the data driving chip 61 and the gate driving chip 62 are connected to an integrated printed circuit board (not shown) through the flexible printed circuit board 70.

  On the other hand, a control driving chip 71 for providing a timing signal and a video data signal to the data driving chip 61 and the gate driving chip 62 and a common voltage generating chip 72 for generating a common voltage are mounted on the flexible circuit board 70. .

  As described above, the structure in which the data driving chip 61 and the gate driving chip 62 are mounted in the glass substrate 60 can reduce the manufacturing cost and minimize the power loss by integrating the driving circuit.

  However, when various driving chips are mounted on the glass substrate 60, the following problems occur.

  First, when a large number of chips are mounted on a glass substrate, the defect rate is increased by the number of chips. That is, even if a defect occurs in only one chip, the entire liquid crystal display module is processed as a defect, resulting in a decrease in yield, an increase in the defect rate, and a longer process time. Is lowered.

  Second, when a large number of chips are mounted on a glass substrate from a mechanical side, the overall size of the liquid crystal display panel is increased. That is, as the number of chips increases, the number of patterns formed on the glass substrate increases, and the size of the liquid crystal display panel can only be increased in order to secure a pattern formation space. Accordingly, it is impossible to realize high resolution with a liquid crystal display panel with a limited size.

  Third, since the chip is mounted only in a partial region of the liquid crystal display panel, the structure of the liquid crystal display panel is not symmetrical and is biased to one side. Therefore, the size of the liquid crystal display device is further increased.

  Fourth, in terms of screen characteristics, the uniformity of image quality is degraded by the contact resistance of the chip mounted on the glass substrate.

  SUMMARY OF THE INVENTION A first object of the present invention is to provide an on-glass single-chip liquid crystal display device capable of reducing the process time and defect rate required for mounting a chip, and further reducing the overall size. It is in.

  A second object of the present invention is to provide an on-glass single-chip liquid crystal display device that can ensure compatibility with the channel terminals and data lines of an integrated driving chip.

  The third object of the present invention is that the display area can be symmetrically arranged and a sufficient space for forming the gate driving circuit on the substrate can be secured. It is an object to provide an on-glass single-chip liquid crystal display device that can be applied.

  A fourth object of the present invention is to provide an on-glass single-chip liquid crystal display device in which the liquid crystal display device can be symmetric and can increase the effective display area.

A first substrate including a display region and a peripheral region of the display region;
In a liquid crystal display device including a second substrate facing the first substrate and a liquid crystal sealed between the first and second substrates,
The first substrate is
A plurality of switching elements provided in a matrix in the display area;
A plurality of pixel electrodes provided in a matrix in the display region and connected to a first current electrode of a corresponding switching element among the plurality of switching elements;
A plurality of gate lines commonly connected to a control electrode of each row direction switching element among the plurality of switching elements;
A plurality of data lines commonly connected to the second current electrodes of the switching elements in the column direction among the plurality of switching elements;
The plurality of data lines are integrated in a peripheral region where one end of the plurality of data lines extends, and an analog drive signal is input in block units, each line block of the plurality of data lines is selected, and the block is added to the data line of the selected line block. A line block selection circuit for switching the analog drive signal of the unit;
The line block selection circuit is attached to a peripheral region, and external video data and an external control signal are input to provide a first gate driving signal to odd-numbered lines of the plurality of gate lines, An integrated driving chip for providing a second gate driving signal to even-numbered lines of the gate lines and outputting a line block selection signal and an analog driving signal in units of blocks to the line block selection circuit;
The integrated drive chip is
A first gate driver for providing the first gate drive signal to the odd-numbered lines;
An on-glass single-chip liquid crystal display device comprising: a second gate driving unit that provides the second gate driving signal to the even-numbered lines.

Here, the integrated driving chip is
An interface unit for interfacing the input of the external video data and the external control signal;
A memory unit for storing the external video data;
A source driver for inputting block-unit video data read from the memory unit and outputting a block-unit analog drive signal;
A level shift unit for shifting and outputting levels of the first drive control signal, the second drive control signal, and the line block selection signal;
In response to the external control signal input through the interface unit, the external video data is stored in the memory unit, and the first and second drive control signals and the line block selection signal are generated to the level shift unit. And a controller for reading the video data stored in the memory unit in units of blocks and providing the read data to the source driver.

  Here, the first gate driving signal output terminal of the integrated driving chip is connected to an odd-numbered gate line of the plurality of gate lines in the peripheral region where one ends of the plurality of gate lines extend.

  Here, the second gate driving signal output terminal of the integrated driving chip is connected to an even-numbered gate line of the plurality of gate lines in the peripheral region where the other ends of the plurality of gate lines extend.

Here, the integrated driving chip is
A common voltage generator for generating a common voltage and providing it to a common electrode line formed on the liquid crystal display panel;
It further includes a DC / DC converter for receiving a voltage supply from the outside to increase or decrease the level of the external voltage and provide the controller unit, the level shift unit, the source driving unit, and the common voltage generating unit.

  Here, two switching elements adjacent in the horizontal direction among the plurality of switching elements share one data line.

  Here, the drive control signal includes a start signal, a first clock signal, and a second clock signal.

  According to the above-described on-glass single-chip liquid crystal display device, an integrated driving chip is mounted on the liquid crystal display panel and displays an image by controlling the overall driving of the liquid crystal display panel. Therefore, defects of the liquid crystal display device can be minimized and the overall size can be reduced.

FIG. 6 is a plan view illustrating a liquid crystal display panel of a conventional amorphous liquid crystal display device. FIG. 6 is a plan view showing a structure in which data and a gate driving chip are mounted on a liquid crystal display panel of a conventional amorphous liquid crystal display device. 1 is an exploded perspective view illustrating a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 4 is a plan view illustrating an embodiment of the thin film transistor substrate illustrated in FIG. 3. FIG. 5 is a plan view illustrating still another embodiment of the thin film transistor substrate illustrated in FIG. 3. FIG. 6 is a block diagram illustrating an internal configuration of an integrated drive chip illustrated in FIG. 5. FIG. 6 is a block diagram illustrating an internal configuration of an integrated driving chip according to another embodiment of the present invention. FIG. 5 is a circuit diagram specifically illustrating a first line block selection circuit that selectively drives a plurality of data lines divided into two blocks. FIG. 9 is an output waveform diagram of the first data line line block selection circuit illustrated in FIG. 8. FIG. 5 is a circuit diagram specifically illustrating a second line block selection circuit that selectively drives a plurality of data lines divided into three blocks. FIG. 11 is an output waveform diagram of the second line block selection circuit illustrated in FIG. 10. FIG. 6 is a plan view specifically showing a third line block selection circuit that selectively drives a plurality of data lines divided into four blocks. FIG. 13 is an output waveform diagram of the third line block selection circuit illustrated in FIG. 12. FIG. 6 is a configuration diagram of a first shift register according to the first embodiment of the present invention that constitutes the gate driving circuit shown in FIG. 5. FIG. 15 is a circuit diagram of the shift register illustrated in FIG. 14. FIG. 15 is an output waveform diagram of the shift register illustrated in FIG. 14. FIG. 6 is a configuration diagram of a second shift register according to a second embodiment of the present invention that constitutes the gate driving circuit shown in FIG. 5. FIG. 6 is a configuration diagram of a third shift register according to a third embodiment of the present invention that constitutes the gate driving circuit shown in FIG. 5. FIG. 19 is a circuit diagram specifically illustrating a third shift register illustrated in FIG. 18. FIG. 4 is a perspective view specifically illustrating a structure of a flexible printed circuit board illustrated in FIG. 3. It is a top view which shows the liquid crystal display panel by other embodiment of this invention. FIG. 22 is a configuration diagram of fourth and fifth shift registers constituting the first and second gate driving circuits shown in FIG. 21. FIG. 23 is an output waveform diagram of the fourth and fifth shift registers illustrated in FIG. 22. FIG. 6 is a plan view showing a liquid crystal display panel according to another embodiment of the present invention. FIG. 25 is a block diagram specifically illustrating an internal configuration of the integrated driving chip illustrated in FIG. 24.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 3 is an exploded perspective view of a liquid crystal display device according to an exemplary embodiment of the present invention.

  As shown in FIG. 3, the liquid crystal display device 500 includes a liquid crystal display panel assembly 100, a backlight assembly 200, a chassis 300, and a cover 400.

  The liquid crystal display panel assembly 100 includes a liquid crystal display panel 110, a flexible printed circuit board (hereinafter referred to as FPC) 190, and an integrated driving chip 180.

  The liquid crystal display panel 110 includes a thin film transistor substrate 120 as a lower substrate, a color filter substrate 130 as an upper substrate, and a liquid crystal layer (not shown) provided therebetween. A display cell array circuit and a gate driving circuit are formed on the thin film transistor substrate 120 by an a-Si thin film process. An integrated driving chip 180 is attached on the thin film transistor substrate 120. The integrated driving chip 180 is electrically connected to an external circuit board (not shown) by the FPC 190.

  Meanwhile, the RGB filter and the transparent common electrode are formed on the color filter substrate 130.

  The backlight assembly 200 includes a lamp assembly 220, a light guide plate 240, an optical sheet 260, a reflection plate 280 and a mold frame 290.

  FIG. 4 is a plan view showing an embodiment of the thin film transistor substrate shown in FIG.

  As shown in FIG. 4, the thin film transistor substrate 120 is divided into a first region corresponding to the color filter substrate 130 and a second region not corresponding to the color filter substrate 130. The first area includes a display area and a peripheral area. The display area includes a plurality of switching elements provided in a matrix, a plurality of data lines DL extending in the row direction, and a plurality of gates extending in the column direction. A line GL is formed. The pixel electrode is connected to the first current electrode of the switching element, the gate line GL is commonly connected to the control electrode of the switching element in the row direction, and the data line DL is commonly connected to the second current electrode of the switching element in the column direction. Is done. Meanwhile, a gate driving circuit 140 connected to a plurality of gate lines GL is integrated in the peripheral region on the left side of the display region, and the gate driving circuit 140 scans the plurality of gate lines in order.

  An integrated driving chip 180 for controlling general driving of the liquid crystal display panel 110 is mounted on the second region of the thin film transistor substrate 120. An external video data signal 181 a and an external control signal 181 b are input to the integrated drive chip 180 from a circuit board disposed outside the liquid crystal display panel 110. The integrated driving chip 180 outputs a driving control signal GC to the gate driving circuit 140, and provides analog pixel data to the plurality of data lines DL.

  At this time, the external connection terminal of the integrated driving chip 180 is connected to the FPC 190 for electrically connecting the circuit board and the integrated driving chip 180.

  Of the plurality of output terminals of the integrated driving chip 180, a driving control signal output terminal is connected to an input terminal of the gate driving circuit 140, and a plurality of channel terminals CH are connected to a plurality of data lines DL, respectively. Specifically, the drive control signal output terminal includes five terminals: a disclosed signal output terminal, a first clock signal output terminal, a second clock signal output terminal, a first power supply voltage terminal, and a second power supply voltage terminal.

  FIG. 5 is a plan view showing another embodiment of the thin film transistor substrate shown in FIG.

  As shown in FIG. 5, the thin film transistor substrate 120 is divided into a first region corresponding to the color filter substrate 130 and a second region not corresponding to the color filter substrate 130. The first area includes a display area and a peripheral area. In the display area, a plurality of data lines DL are formed extending in the row direction, and a plurality of gate lines GL are formed extending in the column direction. Meanwhile, a gate driving circuit 140 connected to a plurality of gate lines GL is integrated in the left peripheral region of the display region, and a line block selection circuit 150 connected to a plurality of data lines DL is integrated in the upper peripheral region of the display region. Accumulated.

  At this time, an integrated driving chip 180 for controlling the overall driving of the liquid crystal display panel 110 is mounted on the second region of the thin film transistor substrate 120. An external video data signal 181 a and an external control signal 181 b are input to the integrated drive chip 180 from a circuit board disposed outside the liquid crystal display panel 110. The integrated driving chip 180 outputs a driving control signal GC to the gate driving circuit 140, and provides analog pixel data to the plurality of data lines DL.

  At this time, the external connection terminal of the integrated driving chip 180 is connected to the FPC 190 for electrically connecting the circuit board and the integrated driving chip 180.

  The drive control signal output terminal of the plurality of output terminals of the integrated drive chip 180 is connected to the input terminal of the gate drive circuit 140, and the line block selection signal output terminal is connected to the control terminal of the line block selection circuit 150. On the other hand, the plurality of channel terminals CH are connected to the input terminal of the line block selection circuit 150. Each output terminal of the line block selection circuit 150 is connected to a plurality of data lines DL. At this time, the number of the plurality of data lines DL is a positive constant multiple of the number of channel terminals CH of the integrated driving chip 180.

  Here, the line block selection circuit 150 selects each line block of the plurality of data lines DL, and switches an analog drive signal in units of blocks to the data lines DL of the selected line block. Further, a drive control signal is output to the gate drive circuit 140, and a line block selection signal and an analog drive signal in units of blocks are output to the line block selection circuit 150.

  FIG. 6 is a block diagram illustrating an internal configuration of the integrated driving chip illustrated in FIGS. 4 and 5.

  As shown in FIG. 6, the integrated driving chip 180 includes an interface unit 181, a memory unit 183, a source driving unit 185, a level shift unit 184, a common voltage (Vcom) generation unit 186, and a controller unit 182.

  The interface unit 181 receives an external video data signal 181a and an external control signal 181b from the outside, and interfaces the controller unit 182 with an external device. The interface unit 181 is compatible with a CPU interface, a video graphic board (VGD) interface, and a media-Q (Media-Q) interface.

  The controller unit 182 receives the external video data signal 181 a and the external control signal 181 b from the interface unit 181 and stores the external video data signal 181 a in the memory unit 183. The external control signal 181b includes a horizontal and vertical synchronization signal, a main clock signal, a data enable signal, and a mode selection signal. At this time, the controller unit 182 generates a line block selection signal TG in response to the mode selection signal. Here, the external video data signal 181a is, for example, parallel data of 6 bits for each of RGB and a total of 18 bits. The mode selection signal is a signal that selectively applies a high signal to a TG signal that is simply connected in blocks in order to drive the data lines in units of blocks. That is, when the data line is divided into two blocks, TG1 and TG2 are output as signals of opposite phases by the mode selection signal.

  The controller unit 182 provides the level shift 184 with a drive control signal GC and a line block selection signal TG. At this time, the drive control signal GC includes a disclosure signal ST, a first clock signal CK, a second clock signal CKB, a first power supply voltage VSS, and a second power supply voltage VDD.

  The controller unit 182 provides a digital video data signal to the source driver 185. That is, the controller unit 182 outputs the external video data signal 181 a stored in the memory unit 183 in units of blocks and provides it to the source driver 185.

  The memory unit 183 temporarily stores the external video data signal 181a provided from the controller unit 182. At this time, the memory unit 183 stores the external video data signal 181a in units of frames or lines. If a line memory is used, if the output is 360 channels, a 360 × 3 × 6 × 2 = 12,960 bit memory corresponding to two lines is built in. As described above, the memory unit 183 stores the external video data signal 181a in a frame unit or a line unit. However, when storing the external video data signal 181a in a frame unit, a sufficient capacity of the memory unit 183 must be ensured. Therefore, to reduce the capacity of the memory unit 183, the external video data signal 181a is stored in line units. Here, when storing in units of two lines, generation of standby time can be suppressed as compared with the case of storing in units of one line.

  The source driver 185 receives input of digital video data in units of blocks read from the memory unit 183 and outputs block unit analog pixel data. At this time, the output terminal of the source driver 185, that is, the channel terminal CH is connected to the plurality of data lines DL.

  The level shift unit 184 level-shifts and outputs the drive control signal GC and the line block selection signal TG from the controller unit 182. At this time, the level-shifted drive control signal GC includes a level-shifted disclosure signal ST, a first clock signal CK, a second clock signal CKB, a first power supply voltage VSS, a second power supply voltage VDD, and the like.

  The common voltage generator 186 applies a common voltage (Vcom) to a common electrode line formed in parallel with the liquid crystal layer in order to increase the voltage maintenance rate of the liquid crystal layer.

  FIG. 7 is a block diagram showing an internal configuration of an integrated driving chip according to another embodiment of the present invention. Further, in FIG. 7, the same reference numerals are used for the same components as those in FIG. 6, and descriptions of the components are omitted.

  As shown in FIG. 7, the integrated driving chip 180 includes an interface unit 181, a memory unit 183, a level shift unit 184, a source driving unit 185, a common voltage generating unit 186, a DC / DC converter 187, and a controller unit 182.

  The DC / DC converter 187 receives the supply of the first DC power supply voltage 187a provided from the outside, and integrates the second DC power supply voltages AVDD, VSS, VDD, VCC whose level is increased or decreased from the first DC power supply voltage 187a. 180 parts are provided. In general, the DC / DC converter 187 is provided with a first DC power supply voltage 187a of 7 to 12V and raises or lowers the level to a second DC power supply voltage AVDD, VSS, VDD, VCC of 5V.

  The second DC power supply voltages AVDD, VSS, VDD, and VCC that are lowered by the DC / DC converter 187 are provided to the level shift unit 184, the source driver 185, the common voltage generator 186, and the controller unit 182. Specifically, the DC / DC converter 187 provides the analog driving power AVDD of the second DC power supply voltages AVDD, VSS, VDD, and VCC to the source driving unit 185 and the common voltage generating unit 186, and the image driving power supply VSS, VDD is provided to the level shift unit 184. Also, the digital drive power supply VCC is provided to the controller unit 182. As described above, the DC / DC converter 187 applies an appropriate voltage to each part provided in the integrated drive chip 180. By providing the DC / DC converter 187 in the integrated drive chip 180, various types of electrical connection between the integrated drive chip 180 and the DC / DC converter 187 are possible as compared with the case where the DC / DC converter 187 is provided outside the integrated drive chip 180. Wiring becomes unnecessary. Therefore, the size of the liquid crystal display device can be reduced, and a decrease in the yield of the liquid crystal display device due to defects generated during wiring formation can be reduced.

  A line for selectively applying pixel data from the integrated driving chip 180 to the plurality of data lines DL connected between the channel terminal from the integrated driving chip 180 and the data line DL with reference to the drawings. The block selection circuit 150 will be specifically described.

  FIG. 8 is a plan view specifically showing a first line block selection circuit for selectively driving a plurality of data lines divided into two blocks, and FIG. 9 is a waveform of the first line block selection circuit. FIG.

  As shown in FIG. 8, the first line block selection circuit 151 is formed in the upper peripheral region of the thin film transistor substrate 120, and the block-unit analog pixel data provided from the integrated driving chip 180 is converted into the plurality of data lines ( DL1 to DL2m) are applied with a time difference.

  Specifically, the first line block selection circuit 151 divides the 2m data lines (DL1 to DL2m) into two and includes each of the first block (BL1) and the second block (BL2) including m data lines. Become. Specifically, the first block (BL1) includes m odd-numbered data lines (DL1 to DL2m-1), and the second block (BL2) includes m even-numbered data lines (DL2 to DL2m). .

  At this time, the channel terminals (CH1 to CHm) of the integrated driving chip 180 are commonly connected to two data lines. That is, the first channel terminal CH of the integrated driving chip 180 is commonly connected to the first and second data lines DL1 and DL2.

  The first block (BL1) of the first line block selection circuit 151 is connected to the channel terminal CH of the integrated driving chip 180 and the odd-numbered data lines (DL1 to DL2m-1). A first selection transistor SW1 driven by a one-line block selection circuit (hereinafter referred to as TG1) is included. The second block (BL2) is connected to the channel terminal CH of the integrated driving chip 180 and the even-numbered data lines (DL2 to DL2m), and a second line block selection circuit (hereinafter referred to as TG2) from the integrated driving chip 180. The second selection transistor SW2 is driven. At this time, the TG1 signal and the TG2 signal alternately have high periods.

  Specifically, when a high signal is applied to the TG1 signal, the first selection transistor SW1 is driven by the TG1 signal, and analog pixel data from the channel terminal CH is transferred to the odd-numbered data lines (DL1 to DL2m−). Applied to 1). On the other hand, when a high signal is applied to the TG2 signal, the second selection transistor SW2 is driven by the TG2 signal, and analog pixel data from the channel terminal CH is applied to the even-numbered data lines (DL2 to DL2m). Is done.

  As shown in FIG. 9, when the plurality of gate lines GL1 to GLn are sequentially driven by the gate driving circuit 140, the TG1 and TG2 signals are generated in an active period of the plurality of gate lines GL1 to GLn. Alternately have high level intervals.

  That is, the TG1 signal is maintained at a high level for about 1/2 of the active period of the plurality of gate lines (GL1 to GLn), and the TG2 signal is the active period of the plurality of gate lines (GL1 to GLn). The high level is maintained for about 1/2 section.

  Accordingly, when the TG1 signal becomes high level in the active period of the first gate line GL1, the first selection transistor SW1 is driven and the analog pixel data is transferred to the data line (DL2m-1) of the first block (BL1). Applied. When the TG2 signal becomes high level, the second selection transistor SW2 is driven and the analog drive signal is applied to the data line (DL2m) of the second block (BL2).

  In addition, when the TG1 signal becomes a high level in the second gate line GL2 active period, the first selection transistor SW1 is driven and the analog pixel data is transferred to the data line (DL2m-1) of the first block (BL1). Applied. When the TG2 signal becomes high level, the second selection transistor SW2 is driven and the analog pixel data is applied to the data line (DL2m) of the second block (BL2).

  FIG. 10 is a plan view specifically showing a second line block selection circuit for selectively driving a plurality of data lines divided into three blocks, and FIG. 11 shows a second line block selection circuit shown in FIG. It is a wave form diagram of a line block selection circuit.

  Referring to FIG. 10, the second line block selection circuit 152 is formed in an upper peripheral region of the thin film transistor substrate 120, and the block-unit analog pixel data provided from the integrated driving chip 180 is converted into the plurality of data lines. A block made of (DL1 to DL3m) is applied with a time difference.

  Specifically, the second line block selection circuit 152 divides the 3m data lines (DL1 to DL3m) into three blocks including m data lines, that is, first, second and second blocks. It consists of 3 blocks (BL1, BL2, BL3). At this time, the first block (BL1) has m 1, 4, 7,. . . Th data line (DL3m-2), and the second block (BL2) includes m 2, 5, 8,. . . The third block (BL3) includes m number of 3, 6, 9,. . . The second data line (DL3m) is included.

  The channel terminals CH of the integrated driving chip 180 are commonly connected to three data lines. That is, the first channel terminal CH1 of the integrated driving chip 180 is commonly connected to the first, second, and third data lines DL1, DL2, and DL3.

  At this time, the first block (BL1) of the second line block selection circuit unit 152 is connected to the channel terminal CH of the integrated driving chip 180 and 1, 4, 7,. . . The first selection transistor SW1 is connected to the first data line DL3m-2 and is driven by a first line block selection signal (hereinafter referred to as TG1) from the integrated driving chip 180. The second block (BL2) includes the channel terminal CH of the integrated driving chip 180 and the 2, 5, 8,. . . The second selection transistor SW2 is connected to the second data line DL3m-1, and is driven by a second line block selection signal (hereinafter, TG2) from the integrated driving chip 180. The third block (BL3) includes the channel terminal CH of the integrated driving chip 180 and the 3, 6, 9,. . . A third selection transistor SW3 is connected to the third data line DL3m and is driven by a third line block selection signal (hereinafter referred to as TG3) from the integrated driving chip 180. At this time, the TG1, TG2, and TG3 signals alternately have high intervals.

  Specifically, when a high signal is applied to the TG1 signal, the first selection transistor SW1 is driven by the TG1 signal, and analog pixel data from the channel terminal CH is 1, 4, 7. . . Applied to the second data line (DL3m-2). On the other hand, when a high signal is applied to the TG2 signal, the second selection transistor SW2 is driven by the TG2 signal, and the analog pixel data from the channel terminal CH becomes the 2, 5, 8,. . . Applied to the second data line (DL3m-1). When a high signal is applied to the TG3 signal, the third selection transistor SW3 is driven by the TG3 signal, and the analog pixel data from the channel terminal CH is stored in the 3, 6, 9,. . . Applied to the second data line (DL3m).

  As shown in FIG. 11, when the gate lines GL1 to GLn are sequentially driven by the gate line driving circuit 140, the TG1, TG2, and The TG3 signal has high level sections alternately. That is, the TG1, TG2, and TG3 signals divide the active period of the plurality of gate lines (GL1 to GLn) into 1/3, and the divided period is maintained at a high level.

  Accordingly, when the TG1 signal becomes high level during the active period of the first gate line GL1, the first selection transistor SW1 is driven, and the analog pixel data is transferred to the data line (DL3m-2) of the first block (BL1). Is applied. When the TG2 signal becomes high level, the second selection transistor SW2 is driven, and the analog pixel data is applied to the data line (DL3m-1) of the second block (BL2). Further, when the TG3 signal becomes high level, the third selection transistor SW3 is driven, and the analog pixel data is applied to the data line (DL3m) of the third block (BL3).

  When the TG1 signal becomes a high level in the active period of the second gate line GLn, the first selection transistor SW1 is driven, and the analog pixel data is transferred to the data line (DL3m-2) of the first block (BL1). Applied. Further, when the TG2 signal becomes high level, the second selection transistor SW2 is driven, and the analog pixel data is applied to the data line (DL3m-1) of the second block (BL2). Further, when the TG3 signal becomes high level, the third selection transistor SW3 is driven, and the analog pixel data is applied to the data line (DL3m) of the third block (BL3).

  FIG. 12 is a plan view specifically showing a third line block selection circuit for selectively driving a plurality of data lines divided into four blocks, and FIG. 13 shows a third line block shown in FIG. It is a waveform diagram of a line block selection circuit.

  Referring to FIG. 12, the third line block selection circuit 153 is formed in the upper peripheral region of the thin film transistor substrate 120, and the block-unit analog pixel data provided from the integrated driving chip 180 is converted into the plurality of data lines. A block made of (DL1 to DL4m) is applied with a time difference.

  Specifically, the third line block selection circuit 153 divides the 4m data lines (DL1 to DL4m) into four blocks, and includes four blocks including m data lines, ie, first, second, and second. 3 and fourth blocks BL1, BL2, BL3, BL4. At this time, the first block (BL1) has m 1, 5, 9,. . . Second data line (DL4m-3), and the second block (BL2) includes m 2, 6, 10,. . . Th data line (DL4m-2), and the third block (BL3) includes m 3, 7, 11,. . . The fourth block (BL4) includes the m number of 4, 8, 12. . . The second data line (DL4m) is included.

  The channel terminals CH of the integrated driving chip 180 are commonly connected to four data lines. That is, the first channel terminal CH1 of the integrated driving chip 180 is commonly connected to the first, second, third, and fourth data lines DL1, DL2, DL3, and DL4.

  At this time, the first block (BL1) of the third data line selection circuit 153 is connected to the channel terminal CH of the integrated driving chip 180 and the 1, 5, 9,. . . The first selection transistor SW1 is connected to the second data line DL4m-3 and is driven by a first line block selection signal (hereinafter referred to as TG1) from the integrated driving chip 180. The second block (BL2) includes channel terminals CH and 2, 6, 10,. . . The second selection transistor SW2 is connected to the second data line DL4m-2 and is driven by a second line block selection signal (hereinafter referred to as TG2) from the integrated driving chip 180. Further, the third block (BL3) includes the channel terminal CH of the integrated driving chip 180 and the 3, 7, 11,. . . The third selection transistor SW3 is connected to the third data line DL4m-1 and is driven by a third line block selection signal (hereinafter referred to as TG3) from the integrated driving chip 180. The fourth block (BL4) includes channel terminals CH and 4, 8, 12. . . The fourth selection transistor SW4 is connected to the fourth data line DL4m and is driven by a fourth line block selection signal (hereinafter referred to as TG4) from the integrated driving chip 180. At this time, the TG1, TG2, TG3, and TG4 signals alternately have high periods.

  Specifically, when a high signal is applied to the TG1 signal, the first selection transistor SW1 is driven by the TG1 signal, and the analog pixel data from the channel terminal CH is the 1, 5, 9,. . . Applied to the second data line (DL4m-3). On the other hand, when a high signal is applied to the TG2 signal, the second selection transistor SW2 is driven by the TG2 signal, and the analog pixel data from the channel terminal CH is 2, 6, 10. . . Applied to the second data line (DL4m-2). Further, when a high signal is applied to the TG3 signal, the third selection transistor SW3 is driven by the TG3 signal, and the analog pixel data from the channel terminal CH is 3, 7, 11,. . . Applied to the second data line (DL4m-1). When a high signal is applied to the TG4 signal, the fourth selection transistor SW4 is driven by the TG4 signal, and the analog pixel data from the channel terminal CH is stored in the 4, 8, 12,. . . Applied to the second data line (DL4m).

  As shown in FIG. 13, when the gate lines GL1 to GLn are sequentially driven by the gate line driving circuit 140, the TG1, TG2, The TG3 and TG4 signals have high level sections alternately. In other words, the TG1, TG2, TG3, and TG4 signals are maintained at a high level in the divided section by dividing the active section of the plurality of gate lines (GL1 to GLn) into 1/4.

  Accordingly, when the TG1 signal becomes high level during the active period of the first gate line GL1, the first selection transistor SW1 is driven and the analog pixel data is transferred to the data line (DL4m-3) of the first block (BL1). Applied. When the TG2 signal becomes high level, the second selection transistor SW2 is driven and the analog pixel data is applied to the data line (DL4m-2) of the second block (BL2). Further, when the TG3 signal becomes high level, the third selection transistor SW3 is driven, and the analog pixel data is applied to the data line (DL4m-1) of the third block (BL3). Further, when the TG4 signal becomes high level, the fourth selection transistor SW4 is driven, and the analog pixel data is applied to the data line (DL4m) of the fourth block (BL4).

  When the TG1 signal becomes high level during the active period of the second gate line GL2, the first selection transistor SW1 is driven and the analog pixel data is applied to the data line (DL4m-3) of the first block (BL1). Is done. Further, when the TG2 signal becomes high level, the second selection transistor SW2 is driven, and the analog pixel data is applied to the data line (DL4m-2) of the second block (BL2). Further, when the TG3 signal becomes high level, the third selection transistor SW3 is driven and the analog pixel data is applied to the data line (DL4m-1) of the third block (BL3). Further, when the TG4 signal becomes high level, the fourth selection transistor SW4 is driven, and the analog pixel data is applied to the data line (DL4m) of the fourth block (BL4).

  8 to 13, even if the number of channel terminals CH of the integrated driving chip 180 is fixed to m, the number of data lines commonly connected to each of the channel terminals CH is reduced. 2, 3, 4,. . . In addition, by selectively applying pixel data to the plurality of data lines, various resolutions of the liquid crystal display device 500 can be realized. That is, the block unit is the number of data lines, which is 1/1, 1/2, 1/3, 1/4. . . By doing so, you can change the resolution in various ways.

  However, in order to increase the resolution of the liquid crystal display device 500, the main clock is set to 2, 3, 4,. . . When divided into two, the time for charging the pixel data of the liquid crystal display device 500 is reduced accordingly. Accordingly, it is preferable to increase the resolution of the liquid crystal display device 500 in consideration of the charging time of the pixel data.

  Hereinafter, a gate driving circuit formed in the left peripheral region of the liquid crystal display panel will be described in detail with reference to the drawings.

  FIG. 14 is a block diagram of a first shift register according to the first embodiment of the present invention that constitutes the gate driving circuit shown in FIG. 15 is a specific circuit diagram of each stage of the first shift register shown in FIG. 14, and FIG. 16 is an output waveform diagram of FIG.

  Here, FIGS. 14 to 16 show a gate driving circuit integrated in the left peripheral region of the liquid crystal display panel.

  As shown in FIG. 14, the gate driving circuit 140 includes one first shift register 141 in which a plurality of stages (SRC1 to SRCn) are cascade-connected. That is, by connecting the output terminal OUT of each stage to the input terminal IN of the next stage, the stages are connected in a dependent manner. The first shift register 141 includes n stages (SRC1 to SRCn) corresponding to the gate lines (GL1 to GLn) and one dummy stage (SRCn + 1). Each stage has an input terminal IN, an output terminal OUT, a control terminal CT, a clock signal input terminal, a first power supply voltage terminal VSS, and a second power supply voltage terminal VDD.

  The disclosure signal ST is input to the input terminal IN of the first stage. Here, the disclosure signal ST is a pulse signal synchronized with the vertical synchronization signal VSYN from the controller unit 182 shown in FIG.

  The output signals (OUT1 to OUTn) of each stage are connected to the corresponding gate lines (GL1 to GLn). The first clock signal CK is provided to the odd-numbered stages (SRC1, SRC3), and the second clock signal CKB is provided to the even-numbered stages (SRC2, SRC4). At this time, the first clock signal CK and the second clock signal CKB have opposite phases.

  The output signals (OUT2, OUT3, OUT4) of the next stages SRC2, SRC3, SRC4 are inputted to the control terminals CT of the respective stages SRC1, SRC2, SRC3 as control signals. That is, the control signal input to the control terminal CT is used to lower the output signal of the previous stage to a low level.

  Accordingly, since the output signals of the respective stages have active sections (high state) in order, the gate lines corresponding to the active sections of the respective output signals are sequentially selected.

  As shown in FIG. 15, each stage of the first shift register 141 includes a pull-up unit 142, a pull-down unit 144, a pull-up driving unit 146 and a pull-down driving unit 148.

  The pull-up unit 142 includes a first NMOS transistor NT1 having a drain connected to the clock signal input terminal, a gate connected to the third node N3, and a source connected to the output terminal OUT.

  The pull-down unit 144 includes a second NMOS transistor NT2 having a drain connected to the output terminal OUT, a gate connected to the fourth node N4, and a source connected to the first power supply voltage terminal VSS.

  The pull-up driver 146 includes a capacitor C and third to fifth NMOS transistors NT3 to NT5. The capacitor C is connected between the third node N3 and the output terminal OUT. The third NMOS transistor NT3 has a drain connected to the second power voltage terminal VDD, a gate connected to the input terminal IN, and a source connected to the third node N3. The fourth NMOS transistor NT4 has a drain connected to the third node N3, a gate connected to the control terminal CT, and a source connected to the first power voltage terminal VSS. The fifth NMOS transistor NT5 has a drain connected to the third node N3, a gate connected to the fourth node N4, and a source connected to the first power voltage terminal VSS.

  At this time, the size of the third NMOS transistor NT3 is about twice as large as the size of the fifth NMOS transistor NT5.

  The pull-down driver 148 includes sixth and seventh NMOS transistors NT6 and NT7. The sixth NMOS transistor NT6 has a drain and a gate commonly connected to the second power supply voltage terminal VDD, and a source connected to a fourth node N4. The seventh NMOS transistor NT7 has a drain connection to the fourth node N4, a gate connected to the third node N3, and a source connected to the first power voltage terminal VSS.

At this time, the size of the sixth NMOS transistor NT6 is about 10 times larger than the size of the seventh NMOS transistor NT7.
As described above, each stage of the shift register includes one capacitor C and five transistors NT3 to NT7, so that the size of the liquid crystal display device can be reduced and the yield can be increased.

As shown in FIG. 16, when the first and second clock signals (CK, CKB) and the disclosure signal ST are supplied to the first shift register 141, the edge of the disclosure signal ST is generated in the first stage SRC1. In response to this, the capacitor C is charged to turn on the pull-up means 142, and a high level interval of the first clock signal CK is generated at the output terminal OUT as the first output signal OUT1. In response to the edge of the next gate line drive signal, the capacitor C is discharged, and the pull-up means 142 is turned off. On the other hand, the seventh NMOS transistor NT7 is turned off by releasing the potential of the third node N3, and the potential of the fourth node N4 rises. As the fourth node N4 rises, the fifth NMOS transistor NT5 is turned on, and the pull-up means 142 is turned off. Also, the pull-down means 144 is turned on in response to the edge of the next gate line drive signal.
Thereafter, in the second stage SRC2, in response to the first output signal OUT1 of the first stage SRC1, a high level interval of the second clock signal CKB is generated at the output terminal OUT as the second output signal OUT2. As described above, the first to n-th output signals (OUT1 to OUTn) are sequentially generated at the output terminal OUT of each stage.

  FIG. 17 is a block diagram of a second shift register according to the second embodiment of the present invention that constitutes the gate driving circuit shown in FIG.

  As shown in FIG. 17, the gate driving circuit 140 includes a second shift register 142 in which a plurality of stages (SRC1 to SRCn) are cascade-connected. That is, the output terminal OUT of each stage is connected to the input terminal IN of the next stage, and is connected to the control terminal CT of the previous stage, so that the stages are connected in a dependent manner.

  The second shift register 142 includes n stages (SRC1 to SRCn) corresponding to the gate lines (GL1 to GLn) and one dummy stage (SRCn + 1). That is, the n gate lines GL are sequentially scanned by sequentially driving the stages during one frame.

  Here, the dummy stage (SRCn + 1) is a stage prepared for providing a control signal to the control terminal CT of the Nth stage SRCn. However, since the dummy stage (SRCn + 1) is the last stage of the shift register and there is no next stage, the control terminal CT of the dummy stage (SRCn + 1) is in a floating state, and the dummy stage (SRCn + 1) It may work unstable.

  In order to eliminate such unstable operation of the dummy stage (SRCn + 1), as shown in FIG. 17, a disclosure signal is provided to the first stage SRC1 to the control terminal CT of the dummy stage (SRCn + 1). Disclosure signal input terminals for connecting. That is, the control signal CT of the dummy stage (SRCn + 1) is supplied with the disclosed signal as a control signal.

  In operation, when a disclosure signal having a high level period is input to the disclosure signal input terminal of the first stage SRC1 for the next frame after one frame ends, the dummy driven in the previous frame is input. The control terminal CT of the stage (SRCn + 1) is provided with a high level section of the disclosed signal as a control signal.

  As described above, the dummy stage (SRCn + 1) is connected to the input terminal IN of the first stage SRC1 to which the disclosure signal is input to the control terminal CT of the dummy stage (SRCn + 1), thereby preventing the unstable operation of the dummy stage (SRCn + 1). Can be prevented.

  Of course, in order to eliminate the unstable operation of the dummy stage (SRCn + 1), it is possible to immediately receive a control signal from the previous stage as shown in FIG.

  18 is a block diagram of a third shift register according to the third embodiment of the present invention that constitutes the gate driving circuit shown in FIG. 5, and FIG. 19 is a block diagram illustrating the third shift register shown in FIG. It is the circuit diagram shown.

  As shown in FIG. 18, the gate driving circuit 140 includes a third shift register 143 in which a plurality of stages (SRC1 to SRCn) are cascade-connected. That is, the output terminal OUT of each stage is connected to the input terminal IN of the next stage, and is connected to the control terminal CT of the previous stage, so that the stages are connected in a dependent manner.

  The third shift register 143 includes n stages (SRC1 to SRCn) corresponding to the gate lines (GL1 to GLn) and one dummy stage (SRCn + 1). Here, the dummy stage (SRCn + 1) is a stage prepared for providing a control signal to the control terminal CT of the Nth stage SRCn. However, since the dummy stage (SRCn + 1) is the last stage and there is no next stage, the output terminal of the next stage is not connected to the control terminal CT of the dummy stage (SRCn + 1).

  Accordingly, the control terminal CT of the dummy stage (SRCn + 1) is connected to the fourth node N4 of the Nth stage SRCn.

  Then, the potential of the fourth node N4 will be briefly described with reference to FIG.

  First, in the Nth stage SRCn, the output signal of the previous stage is provided to the input terminal IN to turn on the seventh NMOS transistor NT7. Accordingly, the potential of the fourth node N4 is lowered to the first power supply voltage terminal VSS.

  Thereafter, even if the seventh NMOS transistor NT7 is turned on, the size of the sixth NMOS transistor NT6 is about 16 times larger than the size of the seventh NMOS transistor NT7, so that the fourth node N4 continues to be in the state of the first power supply voltage terminal VSS. Maintained. At this time, when the output signal of the dummy stage (SRCn + 1) provided to the control terminal CT of the Nth stage SRCn rises to a turn-on voltage, the seventh NMOS transistor NT7 is turned off, and thus the sixth NMOS transistor NT6 is used to turn the seventh NMOS transistor NT6 on. Only the second power supply voltage terminal VDD is supplied to the four nodes N4. Accordingly, the potential of the fourth node N4 starts to rise from the first power supply voltage terminal VSS to the second power supply voltage terminal VDD.

  Subsequently, even if the output signal of the dummy stage (SRCn + 1) applied to the control terminal CT is lowered to a low level and the fourth NMOS transistor NT4 is turned off, the fourth node N4 is connected to the second node through the sixth NMOS transistor NT6. The state of being biased to the power supply voltage terminal VDD is maintained.

  Here, since the fourth node N4 is connected to the control terminal CT of the dummy stage (SRCn + 1), the fourth NMOS transistor NT4 of the dummy stage (SRCn + 1) is turned on by the potential of the fourth node N4. Thus, the output signal of the output terminal OUT of the dummy stage (SRCn + 1) is changed to the turn-off voltage state. Thereby, the dummy stage (SRCn + 1) can perform a stable operation.

  In this way, the second shift register 142 according to the second embodiment of the present invention shown in FIG. 17 is obtained by connecting the control terminal CT of the dummy stage (SRCn + 1) to the fourth node N4 of the Nth stage SRCn. As described above, a separate wiring for connecting the input terminal IN of the first stage SRC1 and the control terminal CT of the dummy stage (SRCn + 1) is not required.

  20 is a perspective view illustrating a flexible printed circuit board FPC having a single pattern layer illustrated in FIG.

  As shown in FIG. 20, the FPC 190 includes a circuit board disposed outside the liquid crystal display panel 110 and a plurality of patterns 191 a for electrically connecting the liquid crystal display panel 110. That is, the FPC 190 serves to provide the integrated driving chip 180 with a signal generated from the circuit board.

  At this time, an external video data signal 181a and an external control signal 181b are input to the integrated driving chip 180. Specifically, the external control signal 181b includes vertical and horizontal synchronization signals (VSYNC, HSYNC) and a main clock signal (MCLK).

  That is, by mounting the integrated driving chip 180 in the liquid crystal display panel 100, the number of signals provided to the liquid crystal display panel 100 through the FPC 190 is reduced, so that the number of patterns 191a provided in the FPC 190 is reduced. Will be reduced accordingly.

  Meanwhile, the plurality of patterns 191 a are formed on the first film 191 of the FPC 190 and are covered with a second film 192 provided to face the first film 191. As described above, the FPC 190 includes a single pattern layer due to a decrease in the number of the patterns 191a.

  FIG. 21 is a plan view illustrating a liquid crystal display panel according to another embodiment of the present invention. 22 is a block diagram specifically showing the liquid crystal display panel shown in FIG. 21, and FIG. 23 is an output waveform diagram of the shift register shown in FIG.

  As shown in FIG. 21, the thin film transistor substrate 120 is divided into a first region corresponding to the color filter substrate 130 and a second region not corresponding thereto. The first area includes a display area and a peripheral area. In the display area, a plurality of data lines DL are formed extending in the row direction, and a plurality of gate lines GL are formed extending in the column direction.

At this time, the first and second gate driving circuits 160 and 170 are symmetrically disposed in the left and right peripheral areas of the display area. That is, the first gate driving circuit 160 connected to the odd-numbered lines of the plurality of gate lines GL is disposed in the left peripheral region of the display region, and the plurality of the plurality of gate lines GL are disposed in the right peripheral region of the display region. A second gate driving circuit 170 connected to the even-numbered lines of the gate lines is disposed. A line block selection circuit 150 connected to the plurality of data lines is disposed in the left peripheral region and the upper peripheral region adjacent to the right peripheral region.
The line block selection circuit 150 receives an analog drive signal in units of blocks, selects each line block of the plurality of data lines DL, and switches the analog drive signals in units of data lines DL of the selected line block.

  At this time, an integrated driving chip 180 that controls the overall driving of the liquid crystal display panel 110 is mounted on the second region of the thin film transistor substrate 120. An external video data signal 181 a and an external control signal 181 b are input to the integrated driving chip 180 from a circuit board disposed outside the liquid crystal display panel 110. The integrated driving chip 180 outputs first and second driving control signals (GC1 and GC2) for controlling driving of the first and second gate driving circuits 160 and 170, and supplies the line block selection circuit 150 with a line block. A selection signal TG is output, and analog pixel data is output to each of the plurality of data lines DL.

  Of the plurality of output terminals of the integrated driving chip 180, first and second driving control signal output terminals are connected to input terminals of the first and second gate driving circuits 160 and 170 to output the line block selection signal. The terminal is connected to the control terminal of the line block selection circuit 150. Meanwhile, the plurality of channel terminals CH are connected to the input terminal of the line block selection circuit 150. The output terminals of the line block selection circuit 150 are connected to the plurality of data lines DL, respectively.

  Specifically, the first drive control signal GC1 includes a disclosure signal ST, a first clock signal CK, a first power supply voltage VOFF or VSS, and a second power supply voltage VON or VDD, and the second drive control signal GC2 is a second signal. The clock signal CKB, the first power supply voltage VOFF or VSS, and the second power supply voltage VON or VDD are included.

  As shown in FIG. 22, the first gate driving circuit 160 is disposed in the right peripheral region of the display region where the odd-numbered gate lines (GL1 to GL2n-1) extend, and the respective output terminals (OUT1 to OUT2n-1). Is formed of a first shift register transistor 161 connected to the odd-numbered gate lines (GL1 to GL2n-1). Meanwhile, the second gate driving circuit 170 is disposed in the right peripheral region of the display region where the even-numbered gate lines (GL2 to GL2n) extend, and the output terminals (OUT2 to OUT2n) are connected to the even-numbered gate lines (GL2 to GL2). GL2n) is constituted by a second shift register transistor 171 connected to the GL2n).

  The output of the i-th stage SRCi of the first shift register 161 is provided to the input terminal INj of the j-th stage SRCj of the second shift register 171 in the right peripheral region through the i-th gate line GLi, and at the same time the j-ith stage ( The control signal is provided to the control terminal CTj-1 of SRCj-i). Similarly, the output of the j-th stage SRCj of the second shift register 171 is provided to the input terminal INi + 1 of the i + 1-th stage SRCi + 1 of the first shift register transistor 161, and at the same time the control terminal of the i-th stage SRCi of the first shift register 161. Provided to the control signal to CTi. Here, i and j are, for example, i = 2n−1 and j = 2n.

  The last stage SRCn + 1 of the first shift register 161 is added to provide a control signal to the control terminal CTn of the last stage SRCn of the second shift register 171 in the dummy stage.

  As shown in FIG. 23, the odd-numbered gate lines (GL1 to GL2n-1) and the even-numbered gate lines (GL2 to GL2n) are sequentially shifted by the disclosed signal ST and synchronized with the first and second clock signals CK and CKB. It can be seen that they are scanned alternately.

  Of the plurality of pixels forming one horizontal line, odd-numbered pixels are driven by corresponding odd-numbered gate lines (GL1 to GL2n-1), and even-numbered pixels are corresponding to even-numbered gate lines (GL2 to GL2n). Driven by.

  Therefore, in order to drive all the pixels of one horizontal line, the two gate lines GL1 and GL2 are driven. Therefore, the number of gate lines is doubled, and 320 gate lines are arranged when the vertical resolution is 160 horizontal lines.

  According to such a gate driving method, two thin film transistors adjacent in the horizontal direction share one data line, and the two thin film transistors are connected to gate lines separated from each other. Accordingly, even if the pixels are on the same horizontal line, the odd-numbered pixels are first filled by the first gate driving circuit 160, and the even-numbered pixels are filled by being delayed by one clock by the second gate driving circuit 170.

  FIG. 24 is a plan view specifically showing a liquid crystal display panel according to another embodiment of the present invention.

  As shown in FIG. 24, the thin film transistor substrate 120 is divided into a first region corresponding to the color filter substrate 130 and a second region not corresponding thereto. The first area includes a display area and a peripheral area. The display area includes a plurality of data lines DL extending in the row direction and a plurality of gate lines extending in the column direction. A line block selection circuit 150 for selectively driving the plurality of data lines DL is formed in the upper peripheral area of the display area.

  Meanwhile, an integrated driving chip 200 that controls the overall driving of the liquid crystal display panel 110 is provided in the second region.

  Specifically, when an external video data signal 181a and an external control signal 181b are input to the integrated driving chip 200 from a circuit board disposed outside the liquid crystal display panel 110, odd-numbered gate lines (GL2n-1) are connected. The first gate drive signal GD1 for driving and the second gate drive signal GD2 for driving the even-numbered gate line (GL2n) are output. The integrated driving chip 200 outputs analog pixel data to each of the plurality of data lines DL.

  The first driving signal output terminal of the integrated driving chip 200 is connected to the odd-numbered gate line (GL2n-1), and the second gate driving signal output terminal is connected to the even-numbered gate line (GL2n). The channel terminal (CH) of the integrated driving chip 200 is connected to the line block selection circuit 150, and the selection signal TG output from the integrated driving chip 200 is applied to the line block selection circuit 150.

  FIG. 25 is a block diagram specifically showing the internal configuration of the integrated driving chip shown in FIG. In the description of FIG. 25, the same reference numerals are given to components that perform the same functions as the components illustrated in FIG. 7, and description of the drive elements is omitted.

  As shown in FIG. 25, the integrated driving chip 200 includes an interface unit 181, a memory unit 183, a level shift unit 184, a source driving unit 185, a first gate driving unit 188, a second gate driving unit 189, and a controller unit 182. Including.

  The controller unit 182 provides the level shift unit 184 with first and second drive control signals GC1 and GC2 and a line block selection signal TG. At this time, the first and second drive control signals GC1 and GC2 include a disclosure signal ST, a first clock signal CK, a second clock signal CKB, a first power supply voltage terminal VSS, and a second power supply voltage terminal VDD.

  The level shift unit 184 shifts the levels of the first and second drive control signals GC1 and GC2 provided from the controller unit 182 and provides them to the first gate driver 188 and the second gate driver 189, respectively.

  The first gate driver 188 outputs a first gate driving signal GD1 for driving the odd-numbered gate line (GL2n-1) according to the first driving control signal GC1, and the second gate driving unit 189 The second drive control signal GC2 outputs a second gate drive signal GD2 for driving the even-numbered gate line (GL2n).

  The integrated driving chip 200 receives a common voltage generator 186 for generating a common voltage Vcom and supplying the common voltage Vcom to a common electrode line formed on the liquid crystal display panel 110 and a DC power source 187a from the outside. It further includes a DC / DC converter 187 for raising or lowering the level of the first DC power supply voltage 187a and providing it to the timing controller 182, the level shifter 184, the source driver 185 and the common voltage generator 186. Since the integrated driving chip 200 includes the first gate driving unit 188 and the second gate driving unit 189 for driving the gate lines in two groups, the driving chip mounted on the liquid crystal display panel is integrated. It will be attached only to the side. Therefore, the size of the liquid crystal display device can be reduced.

  As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to the embodiments, and as long as it has ordinary knowledge in the technical field to which the present invention belongs, without departing from the spirit and spirit of the present invention, The present invention may be modified or changed.

  According to the above-described on-glass single-chip liquid crystal display device, by mounting one integrated driving chip for driving the liquid crystal display panel in the peripheral area of the display area, the process time and the defect rate required for mounting the chip are reduced. And the overall size can be reduced.

  In addition, a line block selection circuit is formed in the peripheral area of the display area in which the data lines extend in the peripheral area of the display area by the same process as the thin film transistor in the display area, and pixel data for one line is time-divided through the line block selection circuit By driving in this manner, compatibility between the channel terminal of the integrated driving chip and the data line can be ensured.

  In addition, the display area can be symmetrically arranged by forming the gate line driving circuit in the zigzag manner in the same process as the thin film transistor in the display area in the left and right peripheral area of the display area where the gate line extends. The present invention can also be applied to an apparatus having a high vertical resolution on a substrate.

  In addition, the liquid crystal display device is symmetrically mounted on the liquid crystal display panel by mounting an integrated driving chip including a gate driving unit for driving a plurality of gate lines and a source driving unit for driving a plurality of data lines. Due to the shape, the effective display area can be increased.

100 Liquid crystal display panel assembly 110 Liquid crystal display panel 120 Thin film transistor 130 Color filter substrate 150 Line block selection circuit 160 First gate drive circuit 161 First shift register transistor 171 Second shift register transistor 170 Second gate drive circuit 180 Integrated drive chip 181 Interface unit 181a External video data signal 181b External control signal 182 Controller unit 183 Memory unit 184 Level shift unit 185 Source drive unit 186 Common voltage generation unit 190 FPC
191 First film 192 Second film 200 Integrated drive chip 220 Lamp assembly 240 Light guide plate 260 Optical sheet 280 Reflector 290 Mold frame 300 Chassis 400 Cover

Claims (7)

A first substrate including a display region and a peripheral region of the display region;
In a liquid crystal display device including a second substrate facing the first substrate and a liquid crystal sealed between the first and second substrates,
The first substrate is
A plurality of switching elements provided in a matrix in the display area;
A plurality of pixel electrodes provided in a matrix in the display region and connected to a first current electrode of a corresponding switching element among the plurality of switching elements;
A plurality of gate lines commonly connected to a control electrode of each row direction switching element among the plurality of switching elements;
A plurality of data lines commonly connected to the second current electrodes of the switching elements in the column direction among the plurality of switching elements;
The plurality of data lines are integrated in a peripheral region where one end of the plurality of data lines extends, and an analog drive signal is input in block units, each line block of the plurality of data lines is selected, and the block is added to the data line of the selected line block. A line block selection circuit for switching the analog drive signal of the unit;
The line block selection circuit is attached to a peripheral region, and external video data and an external control signal are input to provide a first gate driving signal to odd-numbered lines of the plurality of gate lines, An integrated driving chip for providing a second gate driving signal to even-numbered lines of the gate lines and outputting a line block selection signal and an analog driving signal in units of blocks to the line block selection circuit;
The integrated drive chip is
A first gate driver for providing the first gate drive signal to the odd-numbered lines;
An on-glass single-chip liquid crystal display device, comprising: a second gate driving unit that provides the second gate driving signal to the even-numbered lines. The integrated drive chip is
An interface unit for interfacing the input of the external video data and the external control signal;
A memory unit for storing the external video data;
A source driver for inputting block-unit video data read from the memory unit and outputting a block-unit analog drive signal;
A level shift unit for shifting and outputting levels of the first drive control signal, the second drive control signal, and the line block selection signal;
In response to the external control signal input through the interface unit, the external video data is stored in the memory unit, and the first and second drive control signals and the line block selection signal are generated to the level shift unit. 2. The on-glass single-chip liquid crystal display device according to claim 1, further comprising a controller unit that provides and reads the video data stored in the memory unit in units of blocks and provides the data to the source driver.   The first gate drive signal output terminal of the integrated drive chip is connected to an odd-numbered gate line of the plurality of gate lines in the peripheral region where one ends of the plurality of gate lines extend. On-glass single-chip liquid crystal display device.   The second gate drive signal output terminal of the integrated drive chip is connected to an even-numbered gate line of the plurality of gate lines in the peripheral region where the other ends of the plurality of gate lines extend. An on-glass single-chip liquid crystal display device as described in 1. The integrated drive chip is
A common voltage generator for generating a common voltage and providing it to a common electrode line formed on the liquid crystal display panel;
The power supply further includes a DC / DC converter for receiving a voltage supply from the outside to increase or decrease the level of the external voltage and to provide the controller unit, a level shift unit, a source driver, and a common voltage generator. An on-glass single-chip liquid crystal display device as described in 1.   2. The on-glass single-chip liquid crystal display device according to claim 1, wherein two switching elements adjacent in the horizontal direction among the plurality of switching elements share one data line.   2. The on-glass single-chip liquid crystal display device according to claim 1, wherein the drive control signal includes a start signal, a first clock signal, and a second clock signal.

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