JP4930229B2 - SOI wafer evaluation method - Google Patents

Description

  The present invention relates to an SOI wafer evaluation method, and more particularly to an SOI wafer evaluation method for evaluating a silicon active layer and a buried oxide layer of an SOI wafer.

  In recent years, SOI wafers having an SOI structure in which a silicon active layer is formed on an electrically insulating silicon oxide film have excellent device speed, low power consumption, high pressure resistance, environmental resistance, etc. Therefore, it attracts particular attention as a high-performance LSI wafer for electronic devices. This is because an SOI wafer has an embedded oxide film (hereinafter referred to as a BOX layer), which is an insulator, between a support substrate and a silicon active layer (hereinafter referred to as an SOI layer). This is because it has a great advantage that the withstand voltage is high and the soft error rate of α rays is low.

  In addition, in a thin film SOI wafer having an SOI layer thickness of 1 μm or less, a MOS (Metal Oxide Semiconductor) type semiconductor device formed on the SOI layer has a source / drain PN junction area when operated in a fully depleted type. Since the capacitance can be reduced, parasitic capacitance can be reduced and device drive speed can be increased. Furthermore, since the capacitance of the BOX layer serving as the insulating layer is in series with the depletion layer capacitance formed immediately below the gate oxide film, the depletion layer capacitance is substantially reduced, and low power consumption can be realized.

  Recently, higher-quality SOI wafers are required for further miniaturization and higher performance of electronic devices. Therefore, the quality of SOI layers and BOX layers of SOI wafers is actively evaluated. As a method for evaluating the quality of this SOI wafer, a MOS (Metal Oxide Semiconductor) structure is formed on the surface of the SOI layer, and a voltage is applied to the electrode portion to evaluate the quality of the SOI layer and the BOX layer. ing.

  However, forming a MOS structure on an SOI layer for evaluating an SOI wafer requires a large-scale apparatus such as a photolithography process and a large number of processes, and is not costly and has a high burden. There was a bug.

  Therefore, an evaluation method has been developed to more easily evaluate an SOI wafer using a probe that acts as an electrode of the MOS structure without forming the MOS structure on the SOI wafer through many conventional processes. . As one of them, a Pseudo-MOSFET method using an SOI wafer as an evaluation target has been proposed (see, for example, Patent Documents 1 and 2 and Non-Patent Documents 1 and 2). According to this method, the interface state density at the interface between the SOI layer and the BOX layer and the electrical characteristics of the SOI wafer can be measured accurately and easily.

  The Pseudo-MOSFET method will be described. FIG. 4 is a schematic diagram showing a Pseudo-MOS structure. First, as shown in FIG. 4, a needle probe or a mercury probe is directly brought into contact with the SOI layer 11 side of the SOI wafer 10 forming a pseudo MOS structure as an evaluation electrode, and these are contacted with the source electrode (S). And the drain electrode (D). Then, the back surface of the SOI wafer 10, that is, the back surface of the support substrate 13 of the SOI wafer is vacuum-sucked on a stage that can also be used as an electrode, or a gate electrode (G) is formed by bringing a needle into contact with the back surface of the wafer. Various electrical characteristics can be obtained by applying a voltage between these electrodes. At this time, if the SOI wafer is washed with an aqueous solution containing hydrofluoric acid before the evaluation, the natural oxide film formed on the surface of the SOI layer can be removed. It becomes possible to obtain characteristics.

  In this evaluation method, the support substrate is regarded as a gate electrode, and the BOX film is regarded as a gate oxide film. The evaluation is based on the current value between the electrodes in contact with the surface of the SOI layer. This current path is obtained by making the SOI layer a strong inversion state and using the inversion layer formed at the SOI / BOX interface as the SOI layer. / BOX interface quality can be evaluated. For example, in the case of a P-type substrate, the electron mobility of the SOI layer and the interface state density at the interface between the SOI layer and the BOX layer can be obtained by applying a gate voltage to the positive side and measuring. On the other hand, the hole mobility of the SOI layer and the charge density of the BOX layer can be obtained by measuring the gate voltage applied to the negative side.

  However, in the Pseudo-MOSFET method, when the gate voltage is applied through the BOX film, if the SOI layer is thin, it is impossible to evaluate the electrical characteristics of the SOI wafer. Although it was considered to apply a very high gate voltage for measurement, a thin SOI layer generally has a thin BOX film, and the BOX film breaks down during measurement, which makes measurement difficult. There was a problem.

JP 2001-60676 A JP 2001-267384 A S. Cristaleveanu et al. "A Review of the Pseudo-MOS Transistor in SOI Wafers: Operation, Parameter Extraction, and Applications" IEEE Trans. ElectronDev, 47 1018 (2000) H. J. et al. Hovel, “Si film electrical characteristics in SOI substrates by HgFET technologies” Solid-State Electronics, 47, 1311 (2003)

  The present invention has been made in view of the above problems, and it is possible to easily measure electrical characteristics such as electron mobility, interface state density, hole mobility, and BOX layer charge density even in an ultra-thin SOI wafer. The purpose is to provide an evaluation method.

  In order to solve the above problems, in the present invention, in a method for evaluating an SOI wafer using a Pseudo-MOSFET, a source electrode and a drain electrode are brought into contact with an SOI layer of the SOI wafer, and a gate electrode is brought into contact with a support substrate of the SOI wafer. An evaluation method for an SOI wafer is provided, wherein the evaluation is performed while injecting carriers into the SOI layer when evaluating the electrical characteristics of the SOI wafer.

  Thus, when evaluating the electrical characteristics of an SOI wafer using a Pseudo-MOSFET, by performing the evaluation while injecting carriers into the SOI layer, a current value sufficient for measurement cannot be obtained due to insufficient carriers. Therefore, the electrical characteristics of the thin film SOI wafer that could not be evaluated can be evaluated by an easy means without imposing an excessive load on the BOX layer.

Moreover, it is preferable to irradiate light as a method for injecting carriers.
In this manner, by irradiating light and injecting carriers, carriers can be easily injected, and measurement can be easily performed without damaging the SOI layer and the BOX layer.

  As described above, in the SOI wafer evaluation method of the present invention, when evaluating the electrical characteristics of the SOI wafer, the evaluation is performed while carriers are injected into the SOI layer. For this reason, even an ultra-thin SOI wafer with a small number of carriers in the layer can compensate for the shortage of carriers, so damage to the wafer structure can be achieved without applying a load such as increasing the gate voltage. Without giving, electrical characteristics such as electron mobility, interface state density, hole mobility, and BOX layer charge density can be easily measured in a short time.

Hereinafter, the present invention will be described more specifically.
As described above, in the Pseudo-MOSFET method, it is difficult to perform evaluation when the SOI layer is thin. Therefore, development of a method for easily evaluating the electrical characteristics of a thin film SOI wafer in a short time has been awaited.

  Therefore, the present inventor decided to investigate the reason why the electrical characteristics of the thin film SOI wafer cannot be evaluated by the Pseudo-MOSFET method.

  As a result, when a gate voltage is applied through the BOX film, if the SOI layer is thin, sufficient carriers cannot be generated to form this inversion layer, and it becomes impossible to evaluate the electrical characteristics of the SOI wafer. I understood it. For example, in the case of evaluating a P-type substrate, especially when a voltage is applied to the positive side, the carriers in the strong inversion layer are few, and when applied to the negative side, the accumulation layer is formed at the BOX interface. It was found that the measurement was not possible due to the small number.

  Therefore, the present inventor has intensively studied a method that can easily compensate for the shortage of carriers in the SOI layer without greatly affecting the structure of the SOI layer or the BOX layer.

  As a result, the present inventor has found that the problem can be solved by evaluating electrical characteristics while injecting carriers into the SOI layer, and has completed the present invention.

Hereinafter, the present invention will be described in detail with reference to FIG. 1, but the present invention is not limited thereto.
An example of an SOI wafer evaluated by the evaluation method of the present invention has a general structure as shown below.
For example, an insulating layer is formed on a supporting substrate, and an SOI layer is formed on the insulating layer.
The procedure of the evaluation method of the present invention is exemplified below.

First, an SOI wafer to be evaluated is prepared. The SOI wafer to be prepared is an SOI wafer obtained by laminating the polished surfaces of two mirror-polished wafers having a silicon oxide film formed on at least one silicon wafer surface, grinding one of the wafers, and then thinning the wafer by polishing. prepare.
In addition, after ion implantation of hydrogen into one mirror-polished wafer in advance, the polished surfaces of the two mirror-polished wafers were bonded together, and one wafer was peeled off with a hydrogen ion-implanted layer by subsequent heat treatment to form an SOI structure. Thereafter, an SOI wafer obtained by polishing the surface of a thin film to be an SOI layer may be used.
Further, it may be a so-called SIMOX (Separated Implanted Oxide) wafer manufactured by performing high-temperature heat treatment after oxygen is ion-implanted into one mirror-polished wafer.

Then, in order to remove the natural oxide film formed on the SOI layer surface of the SOI wafer, the SOI wafer is washed with an aqueous solution containing hydrofluoric acid.
The concentration of the hydrofluoric acid in the aqueous solution containing hydrofluoric acid only needs to be such that the natural oxide film can be removed, and the cleaning conditions such as the temperature of the aqueous solution and the cleaning time need only be such that the natural oxide film can be removed. If the concentration of hydrofluoric acid is high, the BOX layer 12 interposed between the SOI layer 11 and the support substrate 13 may be etched. Therefore, it is preferable that the hydrofluoric acid concentration is low.

After washing the SOI wafer with such an aqueous solution containing hydrofluoric acid, the SOI wafer is rinsed with pure water and dried.
In the drying method, drying can be performed by applying dry air to the SOI wafer. It can also be dried using a device such as a spin dryer. Alternatively, it may be dried using a chemical solution such as IPA (isopropyl alcohol).

  The electrical characteristics of the SOI wafer 10 preprocessed by the above procedure are evaluated as shown in FIG. First, the surface of the SOI wafer 10 on the support substrate 13 side is sucked by the vacuum chuck 14. The vacuum chuck 14 is made of a conductive material such as metal and can also serve as a gate electrode (G).

Here, the carrier injection source 15 is prepared. Evaluation is performed while carriers are injected into the SOI layer 11 by a carrier injection source. Here, light can be irradiated as a method for injecting carriers. As the light source, a halogen lamp can be used, an LED can be used, and a fluorescent lamp can be used. That is, any material that emits light can be used as a carrier injection source.
Moreover, there is no restriction | limiting in particular regarding the illumination intensity of light. If light is applied at any illuminance, carriers can be injected into the SOI layer, and the electrical characteristics of the SOI wafer can be evaluated by the Pseudo-MOSFET method. Here, the halogen lamp has a peak in the vicinity of 700 nm (˜1.8 eV) at a wavelength of 400 nm (˜3.1 eV) to 900 nm (˜1.4 eV), and is lower than the band gap (˜9 eV) of SiO _2. This is advantageous because it is higher than the band gap (˜1.1 eV).

  When the SOI wafer 10 is attracted to the vacuum chuck 14, a needle probe or a mercury probe is brought close to the surface of the SOI layer 11 and brought into contact with the SOI layer 11. Either one is a source electrode (S) and the other is a drain electrode (D). Further, by preparing a carrier injection source 15 on the SOI layer 11 side and injecting carriers into the SOI layer 11, Pseudo-MOSFET measurement becomes possible.

The Pseudo-MOS structure while forming by applying a constant drain voltage, by changing the gate voltage in this state, monitors the change in the drain current, the relationship between the gate voltage V _G and the drain current I _D, i.e. measuring the V _G -I _D characteristic. The measured V _{G- ID} characteristic is as shown in FIG. 2, for example. Then, the electron mobility from the measured V _G -I _D characteristic can be determined interface state density, the hole mobility and oxide charge density.

  By performing the above steps, the electron mobility, interface state density, hole mobility, and oxide film charge density of the SOI layer can be evaluated.

  The thickness of the SOI layer can be 40 nm or less. The thickness of the BOX layer can be 100 nm or less. By injecting carriers into the SOI layer, it has been difficult to obtain a sufficient amount of carriers for evaluation unless the SOI layer has a thickness of 50 nm or more and the BOX layer has a thickness of 145 nm or more. By performing the evaluation while injecting carriers as in the invention, a sufficient amount of current can be obtained for evaluating electrical characteristics without running out of carriers even when the layer thickness is reduced. Even an SOI wafer having a small thickness can be evaluated.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Example)
As a measurement target wafer, a silicon SOI wafer having a conductive P type, a diameter of 200 mm, and a crystal orientation <100> was prepared as a support substrate and a wafer to be an SOI layer. Note that boron is used as a dopant for making the wafer P-type, and the resistivity of the wafer is 10 Ω · cm. The thicknesses of the SOI layer and the BOX layer are about 20 nm and 50 nm, respectively.

The SOI wafer was washed with an aqueous solution containing 1% by mass of hydrofluoric acid for 1 minute, rinsed with pure water, and then dried by blowing dry air to remove moisture. After contacting the probes to the SOI wafer, in order to inject carriers in the SOI layer, to prepare the halogen lamp 20W, while being irradiated with light, measurements were made V _G -I _D characteristic. The measurement was performed by monitoring the drain current by changing the gate voltage while applying a constant drain voltage. The result is shown in FIG. FIG. 2 is a diagram showing an example in which the V _{G- ID} characteristic is obtained according to the present invention. A Keithley semiconductor parameter analyzer SC4200 was used for this measurement.

(Comparative example)
In the example, when measuring the V _{G- ID} characteristic by bringing the probe into contact, the evaluation of the SOI wafer was performed under the same conditions as in the example except that the measurement was performed without irradiating the SOI layer with light. Went. The measurement results are shown in FIG. FIG. 3 is a diagram showing an example in which the V _{G- ID} characteristics in the comparative example are obtained.

From FIG. 2, the V _G -I _D characteristic embodiment, the electron mobility of the SOI layer, the interface state density, a sufficient V _G -I _D characteristic to evaluate the hole mobility and oxide charge density I was able to get it.
On the other hand, in the V _{G- ID} measurement result of the comparative example shown in FIG. 3, since the carrier in the SOI layer is insufficient, a sufficient current value cannot be obtained. From this result, the electron transfer of the SOI layer The degree, interface order density, etc. could not be calculated.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

It is a schematic explanatory drawing for demonstrating this invention. Is a diagram showing an example of obtaining the V _G -I _D characteristic by the present invention. Is a diagram showing an example of obtaining the V _G -I _D characteristic in a comparative example. It is a schematic diagram showing a Pseudo-MOS structure.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... SOI wafer, 11 ... SOI layer, 12 ... BOX layer, 13 ... Supporting substrate, 14 ... Vacuum chuck, 15 ... Carrier injection | pouring source.

Claims (2)

  In a method for evaluating an SOI wafer using a Pseudo-MOSFET, when a source electrode and a drain electrode are brought into contact with an SOI layer of the SOI wafer and a gate electrode is brought into contact with a support substrate of the SOI wafer, the electrical characteristics of the SOI wafer are evaluated. And evaluating the SOI wafer while injecting carriers into the SOI layer.   2. The method for evaluating an SOI wafer according to claim 1, wherein light is irradiated as a method for injecting the carrier.

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