JP4926460B2 - 擬似対称に構成された低温共焼成セラミック構造体の強制焼結法 - Google Patents
擬似対称に構成された低温共焼成セラミック構造体の強制焼結法 Download PDFInfo
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- JP4926460B2 JP4926460B2 JP2005337422A JP2005337422A JP4926460B2 JP 4926460 B2 JP4926460 B2 JP 4926460B2 JP 2005337422 A JP2005337422 A JP 2005337422A JP 2005337422 A JP2005337422 A JP 2005337422A JP 4926460 B2 JP4926460 B2 JP 4926460B2
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Classifications
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- B32B18/00—Layered products essentially comprising ceramics, e.g. refractory products
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C14/00—Glass compositions containing a non-glass component, e.g. compositions containing fibres, filaments, whiskers, platelets, or the like, dispersed in a glass matrix
- C03C14/004—Glass compositions containing a non-glass component, e.g. compositions containing fibres, filaments, whiskers, platelets, or the like, dispersed in a glass matrix the non-glass component being in the form of particles or flakes
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- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/622—Forming processes; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Description
本発明は、1層または複数の層の低kガラス含有内部自己強制テープと、1層または複数の層の高kガラス含有内部自己強制テープと、少なくとも1層のガラス含有プライマリテープとから本質的になる、ゆがみがなく、そりのない非対称性の、低温共焼成されたセラミック構造体であって、上記低kテープの比誘電率は8未満であり、上記高kテープの比誘電率は8超であり、各自己強制テープは独立に、圧力補強のより少ない自己強制焼結LTCCアセンブリに上記プライマリテープを配備することができ、上記自己強制テープは、自己強制テープを前記プライマリテープと一体とみなしたとき構造的対称性を保持するように配置されており、上記内部強制テープおよび上記プライマリテープをラミネートして非対称構造のラミネートを形成し、上記アセンブリを熱処理してx、y収縮の相互抑制を示す構造を作るセラミック構造体である。
本発明で使用する内部強制テープ(501、502)は、標準処理温度である850℃を大幅に下回る温度で、流動し稠密になり、かつ柔軟性になるガラスを含む。強制テープは最終LTCCボディの一部となるので、強制テープ材料に対する性能の要求事項を著しく増大させることになる。強制テープの電気特性(例えば比誘電率k)は、テープをつくる材料の選択によって調節することもできる。これによって、LTCC回路の一部の誘電特性および他の電気特性を局部的に制御するために、2つ以上の化学的タイプのプライマリテープを使用することが可能になる。
プライマリテープ(100)は一般にLTCCアセンブリの大部分を占めるテープであり、得られる焼成アセンブリは、その機械的および電気的特徴をプライマリテープから得る。大抵の場合、構造体において強制テープは小さな部分を占める存在である。強制テープは、効果的にアセンブリの誘電特性および他の電気的特性面を局部的に改変するために使用することができるが、その最も大きな影響は、x、y収縮を実質的にゼロに強制することによって物理的構造を制御することである。
本発明のアセンブリを加熱している間、強制テープ(501または502それぞれについて、低Kまたは高K)中のガラスは、プライマリテープ(低k)のガラスより早くその転移温度(その温度でガラスが焼結を開始し、続いて流動化と稠密化する温度である)に到達し、流動してプライマリテープの隣接層の表面粒子を十分に覆う。強制テープガラスの結晶化温度はどちらも、その転移温度に近くかつそれより高いので、結晶化はその後直ぐに起こる。これはガラスを硬化させ、そのコンポジット粘度を著しく上昇させるかまたは第1の共焼成プロセスおよび/または続く焼成後プロセスの825℃から875℃のピーク焼成温度を超えて再溶融温度を上昇させる結果をもたらす。
内部強制する成分およびプライマリテープ成分ならびに処方を以下に論じる。内部強制テープ(501、502)は、結晶化可能かまたはフィラー反応性ガラス組成を有するAl2O3、TiO2、ZrO2、ZrSiO4、BaTiO3等のフィラーセラミック材料を含み、それによって、焼成の際のその流動、稠密化および剛性化がプライマリテープの残る層へと進むことをさらに特徴としている。強制テープまたはプライマリテープは通常1つのガラスと1つのフィラーからなるが、当分野の技術者は2つ以上のガラスまたは2つ以上のフィラーを使用するように設計することができる。熱処理の際にプライマリテープによって、強制テープのx、y収縮を抑制する物理的働きは、従来のプライマリテープアセンブリの外部から施用したリリース層とよく類似している。しかし、「プライマリテープ」および「強制テープ」という用語を本発明で使用するが、「プライマリテープ」は、そのより低温での焼結/結晶化プロセスの間に「強制テープ」を強制し、他方、すでに焼結された「強制テープ」は、より高温での焼成の間に「プライマリテープ」を強制することに留意されたい。しかし、非犠牲型強制テープとして働く適切な材料のための要件は異なる。材料要件を以下に検討する。
強制テープまたはプライマリテープとして使用するためのグリーンテープは、上記のガラス、セラミックフィラー、ポリマー系バインダーおよび溶媒のスラリー分散液の薄い層をフレキシブル基板上にキャスティングし、そのキャスト層を加熱して揮発性溶媒を除去して形成させる。プライマリテープは、厚さが20ミル未満、好ましくは1から10ミルであることが好ましい。強制テープは1から10ミル、好ましくは1から3ミルの厚さであることが好ましい。次いでテープをシート中にブランク(blank)するかまたはロールの形でまとめる。グリーンテープは一般に多層電子回路用の誘電性すなわち絶縁材料として使用される。グリーンテープのシートは、それぞれの隅を、回路の実際の寸法より若干大きいサイズに整合ホールでブランクする。多層回路の様々な層を連結するために、グリーンテープにビアホールを形成させる。これは一般に機械パンチングで行う。しかし、鋭く焦点をあわせたレーザーを用いて、揮発させ、グリーンテープ中にビアホールを形成させることができる。典型的なビアホールサイズは0.004”から0.25”の範囲である。層間の相互連結は、ビアホールを厚いフィルム導電性インクで満たして形成させる。このインクは通常、標準的なスクリーンプリンティング技術で塗布する。回路の各層はスクリーンプリンティング導電体トラックで仕上げる。また、レジスタインクまたは高比誘電率インクを、選択した層上にプリントして抵抗性または容量性の回路エレメントを形成することができる。さらに、多層コンデンサ業界で使用されるものと類似した特別処方の高比誘電率グリーンテープを、多層回路の一部として組み込むことが可能である。
揮発性溶媒または溶媒ブレンド中で、この実施例で使用するテープ組成物を、微細な無機粉末とバインダーをボールミルで摩砕して調製した。ラミネート化、回路をパターン化する能力、テープバーンアウト特性および焼成されたミクロ構造の進行を最適化するためには、スリップの以下の容積%の処方が有利であることが分かった。実用上の参考として、典型的なスリップ組成の処方も重量パーセントで示した。無機相は、ガラスで4.5g/cc、アルミナで4.0g/ccの比重を有するものとし、有機媒体は1.1g/ccの比重を有するものとする。したがって、比重が本実施例で想定したものと異なる可能性のあるガラス、およびアルミナ以外の酸化物を用いた場合、重量%組成は変ってくる。
プライマリ#2テープ(4.5ミル厚さ)は、実施例1で示したものと同一の合計/強制テープ厚さ比を有する2つの異なる強制テープ組成(強制#1および強制#2)と一組にする。
この実施例ではプライマリテープ#2を有する強制テープ#2および3を使用する。比誘電率k値に関して、強制テープ#2は、強制テープ#3の比誘電率k値と類似したプライマリテープ#2のそれより高い。
別の実験では、プライマリテープ#2と強制テープ#1および#2を用いた。実施例2の試験#7と、実施例4の試験#14〜#16の差は多層ラミネートの配置にある。
Claims (9)
- 1層または複数の層の低kガラス含有内部自己強制テープ、1層または複数の層の高kガラス含有内部自己強制テープ、および、少なくとも1層のガラス含有プライマリテープとから本質的になる、ゆがみがなく、そりのない非対称性の、低温共焼成されたセラミック構造体であって、
前記低kガラス含有内部自己強制テープのガラスは、全組成物に対する重量%で、SiO 2 12〜14、ZrO 2 3〜6、B 2 O 3 20〜27、BaO12〜15、MgO33〜36、Li 2 O1〜3、P 2 O 5 3〜8、Cs 2 O0〜2を含み、
前記高kガラス含有内部自己強制テープのガラスは、全組成物に対する重量%で、B2O36〜13、BaO20〜22、Li2O0.5〜1.5、P2O53.5〜4.5、TiO225〜33、Cs2O1〜6.5、Nd2O329〜32を含み、
前記ガラス含有プライマリテープの前記ガラスは、全組成物に対する重量%で、SiO 2 52〜55、Al 2 O 3 12.5〜14.5、B 2 O 3 8〜9、CaO16〜18、MgO0.5〜5、Na 2 O1.7〜2.5、Li 2 O0.2〜0.3、SrO0〜4、K 2 O1〜2を含み、
前記低kガラス含有内部自己強制テープの比誘電率は8未満であり、前記高kガラス含有内部自己強制テープの比誘電率は8超であり、
各ガラス含有内部自己強制テープは、それぞれ独立して、圧力補強のより少ない自己強制焼結LTCCアセンブリに前記ガラス含有プライマリテープを配備することができ、
前記ガラス含有内部自己強制テープは、ガラス含有内部自己強制テープを前記ガラス含有プライマリテープと一体とみなしたとき構造的対称性を保持するように配置されており、
前記ガラス含有内部自己強制テープのガラスの焼結開始温度は、前記ガラス含有プライマリテープのガラスの焼結開始温度よりも75〜85℃低く、前記ガラス含有内部自己強制テープのガラスは前記ガラス含有プライマリテープの焼結開始前に焼結を開始して剛体をもたらし、
前記ガラス含有内部自己強制テープおよび前記ガラス含有プライマリテープをラミネートして非対称構造のラミネートを形成し、
前記アセンブリを熱処理してx、y収縮の相互抑制を示す構成とした、
ことを特徴とするセラミック構造体。 - 前記ガラス含有プライマリテープの比誘電率は7から9の範囲であることを特徴とする請求項1に記載のセラミック構造体。
- 前記ガラス含有内部自己強制テープ層およびガラス含有プライマリテープ層は、平坦でかつ相互連結した形で金属化されていることを特徴とする請求項1に記載のセラミック構造体。
- 表面実装構成要素を備えることを特徴とする請求項1に記載のセラミック構造体。
- 前記ガラス含有内部自己強制テープおよび前記ガラス含有プライマリテープは、より大きいサイズの粒子のD50が1.5から3ミクロンの範囲であり、より小さいサイズの粒子のD50が0.3から0.8ミクロンの範囲の二峰性の粒子径分布を有するフィラー粒子を含むことを特徴とする請求項1に記載のセラミック構造体。
- その層の1つとして請求項1に記載のセラミック構造体を有することを特徴とする多層電子回路。
- 請求項1に記載の剛性構造体を含む多層電子回路であって、前記ガラス含有内部自己強制テープ層はコンデンサの機能を提供することを特徴とする多層電子回路。
- 1層または複数の層の低kガラス含有内部自己強制テープ、1層または複数の層の高kガラス含有内部自己強制テープ、および、少なくとも1層のガラス含有プライマリテープとから本質的になる、ゆがみがなく、そりのない非対称性の、低温共焼成されたセラミック構造体であって、
前記低kガラス含有内部自己強制テープのガラスは、全組成物に対する重量%で、SiO 2 12〜14、ZrO 2 3〜6、B 2 O 3 20〜27、BaO12〜15、MgO33〜36、Li 2 O1〜3、P 2 O 5 3〜8、Cs 2 O0〜2を含み、
前記高kガラス含有内部自己強制テープのガラスは、全組成物に対する重量%で、B2O36〜13、BaO20〜22、Li2O0.5〜1.5、P2O53.5〜4.5、TiO225〜33、Cs2O1〜6.5、Nd2O329〜32を含み、
前記ガラス含有プライマリテープの前記ガラスは、全組成物に対する重量%で、SiO 2 52〜55、Al 2 O 3 12.5〜14.5、B 2 O 3 8〜9、CaO16〜18、MgO0.5〜5、Na 2 O1.7〜2.5、Li 2 O0.2〜0.3、SrO0〜4、K 2 O1〜2を含み、
前記低kガラス含有内部自己強制テープの比誘電率は8未満であり、前記高kガラス含有内部自己強制テープの比誘電率は8超であり、
各ガラス含有内部自己強制テープは、それぞれ独立して、圧力補強のより少ない自己強制焼結LTCCアセンブリに前記ガラス含有プライマリテープを配備することができ、
前記ガラス含有内部自己強制テープは、ガラス含有内部自己強制テープを前記ガラス含有プライマリテープと一体とみなしたとき構造的対称性を保持するように配置されており、
前記ガラス含有内部自己強制テープのガラスの焼結開始温度は、前記ガラス含有プライマリテープのガラスの焼結開始温度よりも75〜85℃低く、前記ガラス含有内部自己強制テープのガラスは前記ガラス含有プライマリテープの焼結開始前に焼結を開始して剛体をもたらし、
前記ガラス含有内部自己強制テープおよび前記ガラス含有プライマリテープをラミネートして非対称構造のラミネートを形成し、
前記アセンブリを熱処理してx、y収縮の相互抑制を示す構造を作る、
ことを特徴とするセラミック構造体の作製方法。 - 前記ガラス含有内部自己強制テープ層およびガラス含有プライマリテープ層は、平坦でかつ相互連結した形で金属化されていることを特徴とする請求項8に記載の方法。
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US10/994,594 US7067026B2 (en) | 2004-11-22 | 2004-11-22 | Process for the constrained sintering of a pseudo-symmetrically configured low temperature cofired ceramic structure |
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US6776861B2 (en) * | 2002-06-04 | 2004-08-17 | E. I. Du Pont De Nemours And Company | Tape composition and process for internally constrained sintering of low temperature co-fired ceramic |
US7175724B2 (en) * | 2004-11-22 | 2007-02-13 | E. I. Du Pont De Nemours And Company | Process for the constrained sintering of a pseudo-symmetrically configured low temperature cofired ceramic structure |
US20060163768A1 (en) * | 2005-01-26 | 2006-07-27 | Needes Christopher R | Multi-component LTCC substrate with a core of high dielectric constant ceramic material and processes for the development thereof |
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WO2020129945A1 (ja) * | 2018-12-21 | 2020-06-25 | 株式会社村田製作所 | 積層体及び電子部品 |
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US4536535A (en) | 1983-06-07 | 1985-08-20 | E. I. Du Pont De Nemours And Company | Castable ceramic compositions |
US4654095A (en) | 1985-03-25 | 1987-03-31 | E. I. Du Pont De Nemours And Company | Dielectric composition |
US5102720A (en) * | 1989-09-22 | 1992-04-07 | Cornell Research Foundation, Inc. | Co-fired multilayer ceramic tapes that exhibit constrained sintering |
US5085720A (en) | 1990-01-18 | 1992-02-04 | E. I. Du Pont De Nemours And Company | Method for reducing shrinkage during firing of green ceramic bodies |
US5254191A (en) | 1990-10-04 | 1993-10-19 | E. I. Du Pont De Nemours And Company | Method for reducing shrinkage during firing of ceramic bodies |
US5144526A (en) | 1991-08-05 | 1992-09-01 | Hughes Aircraft Company | Low temperature co-fired ceramic structure containing buried capacitors |
US5396397A (en) * | 1992-09-24 | 1995-03-07 | Hughes Aircraft Company | Field control and stability enhancement in multi-layer, 3-dimensional structures |
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EP1099246A1 (de) * | 1998-07-15 | 2001-05-16 | Siemens Aktiengesellschaft | Verfahren zur herstellung eines keramischen körpers mit einem integrierten passiven elektronischen bauelement, derartiger körper und verwendung des körpers |
US6205032B1 (en) * | 1999-03-16 | 2001-03-20 | Cts Corporation | Low temperature co-fired ceramic with improved registration |
US6139666A (en) | 1999-05-26 | 2000-10-31 | International Business Machines Corporation | Method for producing ceramic surfaces with easily removable contact sheets |
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US6776861B2 (en) * | 2002-06-04 | 2004-08-17 | E. I. Du Pont De Nemours And Company | Tape composition and process for internally constrained sintering of low temperature co-fired ceramic |
US6827800B2 (en) * | 2003-01-30 | 2004-12-07 | E. I. Du Pont De Nemours And Company | Process for the constrained sintering of asymmetrically configured dielectric layers |
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