JP4902640B2 - Integrated circuit and integrated circuit system - Google Patents

Description

  The present invention relates to memory sharing, and in particular, to a technique for sharing an external memory with a plurality of integrated circuits.

A technique for sharing a memory such as an SDRAM (Synchronous Dynamic Random Access Memory) is disclosed in the patent literature.
Patent Document 1 is a technique for selectively switching data processing devices that access SDRAM when a plurality of data processing devices including a CPU (Central Processing Unit) and the like share and access one SDRAM. This prevents the SDRAM from malfunctioning due to interruption of the control signal to the SDRAM at the time of switching, thereby allowing each data processing device to stably access the SDRAM.

Patent Document 2 is a technique for improving the efficiency of data bus use when a plurality of processors share and access a synchronous DRAM. A time slot that can be accessed by each processor is set in advance. The synchronous DRAM is accessed in the set time slot.
In addition, when a plurality of processors are mounted on a single integrated circuit and the SDRAM is shared, when an access request is issued from each of these processors, the access order of each processor to the SDRAM is determined in advance. A technique is known in which commands and addresses for each access request are sequentially input to the SDRAM in accordance with an arbitration rule. This takes into account that data is read or written after a predetermined clock after the SDRAM receives a read or write command or address input from a processor or the like, and the reading or writing of data for one command or address ends. By inputting the next command or address until this time, data transfer is controlled so as to be performed continuously, and the use efficiency of the data bus can be improved.
Japanese Patent Application Laid-Open No. 2004-102779 JP-A-7-311730

By the way, recent digital information devices and the like are required to have higher functions and more functions, and there are cases where it is desired to add other functions to an existing integrated circuit.
In such a case, for efficient and economical reasons, rather than remanufacturing an integrated circuit to which a new function is added, an integrated circuit having only a new functional part is manufactured and connected to the existing integrated circuit. There is a desire to control access from these integrated circuits with the same use efficiency of the data bus as in the case of sharing the SDRAM used in the circuit with a new integrated circuit and transferring data with a single integrated circuit.

  However, the above-described existing integrated circuit is not manufactured on the assumption that an external integrated circuit is connected, and includes access to the SDRAM by a newly manufactured integrated circuit using the technique of the above-mentioned patent document. Even if arbitration is performed, a command or the like relating to the access request of the other integrated circuit cannot be output until the data transfer relating to the access request from one integrated circuit is completed.

  The present invention has been made in view of the above situation. When processors in a plurality of integrated circuits share a recording device such as an SDRAM, access requests from the processors are arbitrated, and data transfer efficiency is improved. An object of the present invention is to provide an integrated circuit and an integrated circuit system that allow access to a recording device so as to improve the performance of the conventional device.

  In order to solve the above problems, an integrated circuit according to the present invention includes a plurality of master circuits that share an external recording device and issue an access request including an address for data transfer to the recording device. An integrated circuit chip that controls access to the plurality of master circuits by selectively allowing one of the master circuits to access the recording device, and requests access from an external master circuit of the own chip. Accepting an access request from the external master circuit until the data transfer based on the input interface to be accepted and the access request of one of the master circuits selected to access the recording device is completed In this case, the address related to the access request from the external master circuit is output during the data transfer. To, to determine the output timing of the address, and characterized in that it comprises an access control circuit which controls to access to the recording apparatus in accordance with the timing of the determined to the outside of the master circuit. The recording device is an SDRAM (Synchronous Dynamic Random Access Memory).

  With the above-described configuration, the integrated circuit according to the present invention includes a master circuit such as a processor that accesses the same recording device such as SDRAM in a recording device such as SDRAM that can output an address or the like prior to actual data transfer. Even when an external integrated circuit including the external integrated circuit is connected, access to the recording apparatus from each master circuit can be controlled so that the master circuit in the external integrated circuit is in its own chip. In other words, when an internal master circuit is selected as an access target to a recording device such as an SDRAM, and an access request from an external master circuit is received by the end of the data transfer of the master circuit, data transfer of the internal master circuit is performed. In order to continuously transfer data of the external master circuit, the address to output an address related to the access request of the external master circuit during the data transfer of the internal master circuit before the start of the data transfer. Determine the output timing. Therefore, unlike the prior art, it is not possible to output an address related to the data transfer of the master circuit in the other integrated circuit until the data transfer of the master circuit in one integrated circuit is completed. Data transfer similar to that in the chip can be performed.

  The integrated circuit chip has an output interface for outputting timing information for instructing an output timing of an address to the recording device to the outside of the chip, and the access control circuit When an access request is received from the plurality of master circuits and the external master circuit, a master circuit for accessing the recording apparatus is sequentially selected from the master circuits that have issued the received access request, and the address An arbitration circuit that determines an output timing; and an access signal generation circuit that generates an access signal based on an access request of the plurality of master circuits, the arbitration circuit serving as the master circuit for accessing the recording device If the master circuit is selected, the output timing of the determined address is When the timing information to be output is output from the output interface and the plurality of master circuits are selected, arbitration result information indicating the selected master circuits is sent to the access signal generation circuit, and the access signal generation circuit May generate an access signal based on the access request of the master circuit indicated by the arbitration result information and send it to the recording apparatus.

  According to this configuration, the arbitration circuit transmits at least the output timing of the address to the external integrated circuit when the external integrated circuit connected to the chip accesses the recording device, and the access signal generation circuit Since only the data transfer related to the access request from the master circuit in the own chip is controlled, even when the number of integrated circuits connected to the outside increases, the processing related to the data transfer can be shared for each integrated circuit. .

  An integrated circuit according to the present invention includes a plurality of master circuits that share an external recording device and issue an access request including an address for data transfer to the recording device, and one of the plurality of master circuits. An integrated circuit chip that controls access to the plurality of master circuits by selectively allowing one master circuit to access the recording device, and an input interface that receives an access request from an external master circuit of the chip; Based on each access request received from a plurality of master circuits and the external master circuit, under a predetermined condition, select one of the plurality of master circuits to perform data transfer to the recording device, and then perform the external transfer The master circuit of each master circuit is determined to perform data transfer, and precedes the data transfer timing of each master circuit by a predetermined time. The output timing of the address related to the access request of the master circuit is determined regardless of whether or not it overlaps the period in which data transfer by any of the master circuits is performed, and the master circuit is determined according to the determined output timing. And an access control circuit for controlling the recording apparatus to access.

  The predetermined condition is when an access request from an external master circuit is received following an access request from an internal master circuit, and data transfer based on the access request from the internal master circuit is performed prior to the external master circuit. The subsequent data transfer is performed as soon as possible after the end of the previous data transfer. According to this configuration, under the above conditions, the access control circuit performs the previous data transfer regardless of whether the previous data transfer period and the output period of the address related to the subsequent data transfer overlap. Since the output timing can be determined so as to output an address related to the subsequent data transfer in between, even if the object to be accessed to the recording device is changed between the internal master circuit and the external master circuit, The internal and external master circuits can perform data transfer with the same data transfer efficiency as that of the integrated circuit.

  An integrated circuit according to the present invention includes a plurality of master circuits that share an external recording device and issue an access request including an address for data transfer to the recording device, and one of the plurality of master circuits. An integrated circuit chip that controls access to the plurality of master circuits by selectively allowing the one master circuit to access the recording device, and outputs an output interface that outputs the access request to the outside of the chip. An input interface that accepts timing information indicating the output timing of an address related to an access request from the outside, and the access request from each of the plurality of master circuits, and sequentially outputs the access request from the output interface according to a predetermined rule And accepting the timing information from the input interface Based on the timing information received, she characterized in that it comprises an access control circuit for controlling so as to perform the access to the master circuit initiates an access request the output.

  According to this configuration, the integrated circuit according to the present invention includes the input interface that can accept the output timing of the address related to the access request from the master circuit in the own chip from the outside. However, when connected to an existing integrated circuit that can output the output timing of the address corresponding to the access request from the master circuit in its own chip, it accepts the data transfer timing from the integrated circuit and The recording device can be accessed.

  An integrated circuit system according to the present invention is an integrated circuit system in which an external recording device is shared by a first integrated circuit chip and a second integrated circuit chip, and the first integrated circuit chip is connected to the recording device. A plurality of master circuits that issue access requests including addresses for data transfer, an input interface that accepts access requests for data transfer from the master circuit in the second integrated circuit chip to the recording device, and the recording device An output interface that outputs timing information for instructing the output timing of the address to the second integrated circuit chip, and an access request of one of the plurality of master circuits selected to access the recording device. Access from the master circuit in the second integrated circuit chip before the data transfer based on When the request is accepted, the output timing of the address is determined so that the address related to the access request from the master circuit of the second integrated circuit chip is output during the data transfer, and the master of the second integrated circuit chip is determined. An access control circuit that controls the circuit to access the recording device according to the determined timing, and the second integrated circuit chip issues a plurality of access requests including an address for data transfer to the recording device A master circuit, an output interface for outputting the access request to the first integrated circuit chip, an input interface for receiving the timing information from the outside, and accepting the access request from each of the plurality of master circuits, according to a predetermined rule The access request is sequentially sent from the output interface to the first An access control circuit that outputs to the product circuit chip, receives the timing information from the input interface, and controls the master circuit that issued the output access request to perform access based on the received timing information. It is characterized by.

  The data processing apparatus according to the present invention is a data processing apparatus including a first integrated circuit chip, a second integrated circuit chip, and a recording device, wherein the first integrated circuit chip transfers data to the recording device. A plurality of master circuits that issue an access request including the address of the input; an input interface that accepts the access request from the master circuit in the second integrated circuit chip; and timing information for instructing an access timing to the recording device. An output interface for outputting to two integrated circuit chips, and the second integrated circuit until data transfer based on an access request of one of the plurality of master circuits selected to access the recording device is completed When an access request from the master circuit in the chip is received, the second integration is performed during the data transfer. The output timing of the address is determined so that an address related to the access request from the master circuit of the road chip is output, and the master circuit of the second integrated circuit chip is accessed according to the determined timing. The second integrated circuit chip includes a plurality of master circuits for issuing an access request including an address for data transfer to the recording device, and the access request to the first integrated circuit chip. Output interface, an input interface for receiving timing information indicating the output timing of the address related to the output access request, and the access request from each of the plurality of master circuits, and the access request according to a predetermined rule From the output interface sequentially, before An access control circuit that outputs to the first integrated circuit chip, receives the timing information from the input interface, and controls the master circuit that issued the output access request to access based on the received timing information; It is characterized by providing.

  According to this configuration, the first integrated circuit chip and the second integrated circuit chip transfer the access request in the second integrated circuit chip and the output timing of the address related to the access request of the master circuit in the second integrated circuit chip. They are connected to each other so that the timing information shown can be exchanged. Therefore, the access request of the master circuit in both chips is arbitrated according to a predetermined arbitration rule in the first integrated circuit, and the access timing of each master circuit is determined so that the data transfer by the master circuit in both chips is continuously performed. can do. Further, the second integrated circuit chip can transfer data to the master circuit in the own chip based on the timing instructed from the first integrated circuit chip, and the data transfer processing is shared for each integrated circuit chip. Can do.

<Embodiment>
<Overview>
FIG. 1 shows a configuration diagram of an integrated circuit system including a main LSI (Large Scale Integration) and a sub LSI according to the embodiment, and an SDRAM shared by the main LSI and the sub LSI.

The main LSI 100 and the sub LSI 200 shown in the figure are mounted on a data processing apparatus that performs arithmetic processing such as image processing of a digital information device, for example, and both LSIs are mounted in the same apparatus.
The masters A to C and the masters a to c in the figure are a CPU that uses the SDRAM 300 as a main memory, a DSP (Digital Signal Processor) that stores image data in the SDRAM 300 shown in the figure, and the like. Each master circuit in the LSI 200 shares the SDRAM 300.

  The data processing apparatus including the main LSI 100 and the sub LSI 200 according to the present invention, when an access request (Read request or Write request) to the SDRAM 300 is issued from each master circuit in each LSI, the main LSI 100 accesses these. The request is arbitrated and the access timing to the SDRAM 300 is determined. Each LSI accesses the SDRAM 300 based on the arbitration result and the access timing.

It is assumed that the data processing device on which the main LSI 100 and the sub LSI 200 are mounted includes a clock supply circuit (not shown) and supplies a clock signal to the main LSI 100, the sub LSI 200, and the SDRAM 300.
<Configuration>
1. SDRAM300
The SDRAM 300 is a clock synchronous DRAM and includes a clock input terminal, an address input terminal, a data input / output terminal, a command input terminal, and control terminals such as activation control. The SDRAM 300 includes a command signal line connected to a command input terminal, an address signal line connected to an address input terminal, a data signal line connected to a data input / output terminal, and a control signal line connected to a control terminal. The access signal generation circuit 130 of the main LSI 100 and the access signal generation circuit 230 of the sub LSI 200 are connected.

Here, it is assumed that a plurality of signal lines for data transmission in parallel with the SDRAM 300 are prepared as data signal lines.
The SDRAM 300 receives a command signal indicating a command (Write or Read), an address signal indicating an address, and a data signal indicating data from the corresponding terminals at a timing based on a clock from the main LSI 100 and the sub LSI 200.

In addition, data stored in the address indicated by the address signal is read at a preset timing according to the command indicated by the received command signal, or indicated by the data signal at the address indicated by the address signal. The data to be written is written.
In this embodiment, for example, in the case of a Read command, data reading is started at a timing two clocks after the command input, and in the case of a Write command, data writing is performed at a timing one clock after the command input. Shall begin.

2. Main LSI 100
1 includes a master A 111, a master B 112, a master C 113, an arbitration circuit 120, and an access signal generation circuit 130. The main LSI 100 is connected to the SDRAM 300, and is also connected to the sub LSI 200.
Hereinafter, each part will be described.

<Master A to C>
As described above, the master circuits of the master A 111, the master B 112, and the master C 113 are a CPU, a DSP, and the like, and each independently transfers data to the SDRAM 300.
Each master circuit is connected to the arbitration circuit 120 via Req-A, Req-B, Req-C Req signal lines, and Ack-A, Ack-B, Ack-C Ack signal lines, respectively. Each master circuit has Com-A, Com-B, and Com-C Com signal lines for sending commands to the SDRAM 300, and Data-A, Data-B, and Data- for sending and receiving data to and from the SDRAM 300. The data signal line of c and the Add signal lines of Add-A, Add-B, and Add-C for designating the address of the SDRAM 300 are connected to the access signal generation circuit 130.

Each master circuit, when requesting data transfer, sends an access request including information such as a command and a data transfer amount to the arbitration circuit 120 through each Req signal line.
Each master circuit accepts a response signal to the transmitted access request from the arbitration circuit 120 through each Ack signal line. Each master circuit needs to send a command, an address, and data relating to the sent access request to the access signal generation circuit 130 through each Com signal line, Add signal line, and Data signal line, and subsequently transfer data. If there is, the next access request is sent to the arbitration circuit 120 when a response signal is received from the arbitration circuit 120.

<Arbitration circuit 120>
As described above, the arbitration circuit 120 is connected to each master circuit (A to C) by the Req signal line and the Ack signal line, and is an access signal generation circuit with a timing control signal line for transmitting the access timing including the arbitration result. 130 is connected. The arbitration circuit 120 is connected to the sub LSI 200 via an external Req signal line for receiving an access request from the sub LSI 200 to the SDRAM 300 and a timing control signal line for transmitting access timing to the SDRAM 300.

Note that the timing control signal lines in the main LSI 100 are prepared as signal lines for transmitting access timing for each master circuit (A to C).
The arbitration circuit 120 receives an access request from each master circuit through each Req signal line, and also receives an access request from the sub LSI 200. The arbitration circuit 120 stores access request information indicating an access request in a buffer (not shown) in the order in which it is received.

In this embodiment, for example, a FIFO buffer is used as the buffer. The access request information stored in the buffer includes information for identifying an access request source, a command type, and a data transfer amount related to the access request. This information is associated with information.
Further, after storing the access request information in the buffer, the arbitration circuit 120 follows the master request (AC) and the sub LSI 200 based on the access request information according to a prearranged arbitration rule such as the order in which the access requests are received. Any one of these is selected as a target for causing the SDRAM 300 to perform data transfer.

  Further, the arbitration circuit 120 calculates the number of clock cycles required for data transfer of each access request information based on the data transfer amount of the access request information stored in the buffer and the predetermined number of bits that can be transmitted in parallel. Based on the timing based on the clock signal and the calculated number of clock cycles, the arbitration circuit 120 receives the command signal from the master circuit or the sub LSI 200 that selects sequentially so that the data transfer related to each access request is continuously performed. The timing for sending the address signal to the SDRAM 300 is determined.

  That is, the arbitration circuit 120 determines whether or not each access request is made without determining whether or not the data transfer based on each access request is completed, regardless of whether the master circuit that issued the access request to be transferred is an internal master circuit. Command signal and address related to the access request of the master circuit selected as the data transfer target after the data transfer during the output of the data signal related to each data transfer. The output timing of the command signal and the address signal is determined so as to output the signal.

  Further, when the arbitration circuit 120 determines the timing, if the selected master circuit is the master circuit in the main LSI 100, the arbitration circuit 120 receives a timing control signal indicating the timing determined through the timing control signal line corresponding to the master circuit as an access signal. If the selected master circuit is the master circuit of the sub LSI 200, a timing control signal indicating the determined timing is sent to the sub LSI 200.

In the present embodiment, it is assumed that the arbitration circuit 120 transmits the access control timing to the access signal generation circuit 130 and the sub LSI 200 by outputting the timing control signal at a low level.
<Access signal generation circuit 130>
As described above, the access signal generation circuit 130 is connected to each master circuit by each Com signal line, Add signal line, and Data signal line, and to the arbitration circuit 120 by a timing control signal line for each master circuit. The SDRAM 300 is connected with a command signal line, an address signal line, a data signal line, and a control signal line.

  The access signal generation circuit 130 receives a command, an address, and data relating to an access request through the Com signal line, the Add signal line, and the Data signal line of each of the master A 111, the master B 112, and the master C 113, and stores them in a buffer (not shown). Store. The access signal generation circuit 130 generates an access signal for performing data transfer with the SDRAM 300 based on the stored command, address, and data.

Here, the access signal to be generated includes each signal indicating each of the command, address, and data, a control signal for making the SDRAM 300 active, NOP (NOOPERATION) for causing burst transfer during writing to the end, etc. Command signal.
Further, when the access signal generation circuit 130 receives the low-level timing control signal from the arbitration circuit 120, the access signal generation circuit 130 indicates an access signal (hereinafter referred to as “command”) indicating a command from the master circuit indicated by the timing control signal including the arbitration result information. And an access signal indicating an address (hereinafter referred to as an “address signal”) is sent to the SDRAM 300 through a command signal line and an address signal line. In the case of a data write request, an access signal (hereinafter referred to as a “data signal”) indicating data is transmitted through the data signal line at the predetermined timing described above and one clock after the command signal is transmitted. To send.

3. Sub LSI 200
Similar to the main LSI 100, the sub LSI 200 shown in the figure includes a master a 211, a master b 212, a master c 213, an arbitration circuit 220, and an access signal generation circuit 230, and is connected to the SDRAM 300.
<Master a to c>
The masters a to c are CPUs, DSPs, and the like, similar to the masters A to C described above, and each master circuit has a Req signal line (Req-a, Req-b, Req-c) and an Ack signal line. (Ack-a, Ack-b, Ack-c) are connected to the arbitration circuit 220, and each Com signal line (Com-a, Com-b, Com-c), Add signal line (Add-a, Add-c) b, Add-c) and Data signal lines (Data-a, Data-b, Data-c) are connected to the access signal generation circuit 230.

  When transferring data to the SDRAM 300, each master circuit sends an access request to the arbitration circuit 220 through each Req signal line, and receives a response signal from the arbitration circuit 220 through each Ack signal line. Each master circuit sends a command, an address, and data related to the access request sent to the arbitration circuit 220 to the access signal generation circuit 230 through each signal line.

<Arbitration circuit 220>
As described above, the arbitration circuit 220 is connected to the master circuits (a to c) via the respective Req signal lines and Ack signal lines, and is connected to the main LSI 100 via the external Req signal lines and timing control signal lines. The access signal generation circuit 230 is connected to a signal line for transmitting master specifying information indicating a master circuit to which data is to be transferred to the SDRAM 300.

The arbitration circuit 220 accepts access requests sent by the master circuits (a to c), stores access request information in a buffer (not shown) in the order of acceptance, for example, a prearranged arbitration rule such as the order in which access requests are accepted. Accordingly, the master circuits (a to c) that cause the SDRAM 300 to perform data transfer are sequentially selected.
Further, the command indicating the access request information of the selected master circuit, data transfer amount, and information indicating the address are sent to the main LSI 100 and the selection result is stored.

When the arbitration circuit 220 receives the low-level timing control signal from the main LSI 100, the arbitration circuit 220 identifies the master circuit based on the stored selection result, and sends the master identification information indicating the identified master circuit to the access signal generation circuit 230. Send it out.
When it is necessary to send a plurality of access requests to the main LSI 100, the arbitration circuit 220 sends the next access request when it receives a timing control signal at a low level.

<Access signal generation circuit 230>
As described above, the access signal generation circuit 230 is connected to each master circuit (a to c) by each Com signal line, Add signal line, and Data signal line, and the arbitration circuit 220 is for receiving master specifying information. Connected with signal lines. The SDRAM 300 is connected by a command signal line, an address signal line, and a data signal line, and each signal line is the same as described above.

The access signal generation circuit 230 receives commands, addresses, and data from the respective master circuits (a to c) through the respective Com signal line, Add signal line, and Data signal line, and generates each access signal for accessing the SDRAM 300. And store it in the buffer.
Further, the access signal generation circuit 230 receives the master specifying information from the arbitration circuit 220, sends the access signal of the command and address of the master circuit indicated by the master specifying information to the SDRAM 300 through each signal line, and responds to the command. For example, in the case of a data write request, a data signal is sent to the SDRAM 300 through the data signal line at a timing one clock after the command input.
<Data>
FIG. 2A shows an example of access request information received by the arbitration circuit 120 from the master circuits (A to C) and stored in the FIFO buffer. As shown in FIG. 2A, the master A 111, the master B 112, The access requests are received in the order of the master C113.

The access request information 10 is information in which the reception order 11, the Req signal line 12, the command 13, and the transfer amount 14 are associated with each other.
Here, the acceptance order 11 indicates the order in which the arbitration circuit 120 accepts access requests for convenience of explanation, and it is assumed that access request information extracted from the buffer does not remain in the buffer.

The Req signal line 12 is information for identifying the transmission source of the access request, and indicates the Req signal line that has accepted the access request.
The command 13 is a command indicating reading or writing of data with respect to the SDRAM 300. For example, in the case of a data write request, it is indicated by “Write”, and for the sake of convenience of description, a character for identifying the master circuit is indicated, such as “Write A”.

The transfer amount 14 indicates the amount of data that each master circuit needs to transfer to the SDRAM 300. In this embodiment, the unit of the data amount is expressed in bytes.
In the present embodiment, the number of bits that can be transmitted in parallel is 16 bits. For example, when transferring 4 bytes of data, the number of data transfer cycles is 2.
FIG. 2B shows an example of access request information received from the master circuits (ac) and stored in the buffer by the arbitration circuit 220 of the sub LSI 200. As shown in FIG. It shows that the access request is received in the order of a211 and master c213.

The access request information 20 shown in the figure is the same as the access request information 10 shown in FIG.
FIG. 2C shows an example of access request information received by the arbitration circuit 120 of the main LSI 100 from the master circuits (A to C) and the sub LSI 200 and stored in the buffer. As shown in FIG. It shows that the access request is received in the order of A111, sub LSI 200, and master C113.

The access request information 30 in the figure is also the same as the access request information 10 in FIG.
<Operation>
Hereinafter, operations of the main LSI 100 and the sub LSI 200 having the above-described configuration will be described with reference to FIGS. 2, 3, and 4.

The SDRAM 300 used in this operation example is a DDR SDRAM (Double Data Rate Synchronous DRAM). In the timing charts shown in FIGS. 3 and 4, ck and / ck * are clocks for the SDRAM 300 to operate. CK * is a signal having the same cycle as that of CK and having a phase opposite to that of CK. Ck is indicated by a solid line and / ck * is indicated by a dotted line. The SDRAM 300 controls the input / output of data in synchronization with both rising and falling edges of the clock (ck), and the command is the rising edge of the clock (ck) and the falling edge of the clock (/ ck *). It is assumed that latching is performed in synchronization with the timing of the intersection. If the burst length is 4 cycles and a data write request is made, data writing is started one clock after the write command is input.
(1 LSI operation)
FIG. 3 is a timing chart showing temporal changes in which the arbitration circuit 120 that has received an access request from the masters A to C of the main LSI 100 controls data transfer to the SDRAM 300 related to the access request.

  This shows a result of the arbitration circuit 120 of the main LSI 100 controlling the data transfer to the SDRAM 300 by the masters A to C based on the access request information 10 illustrated in FIG. It is assumed that the SDRAM 300 is set in an active state in advance. In the timing chart of FIG. 3, for example, each access signal in response to a data write request from the master A 111 has a command signal WRITE-A and an address signal ADD-A. A. Write the data signal as A0.

Hereinafter, operations of the arbitration circuit 120 and the access signal generation circuit 130 will be described.
The arbitration circuit 120 sequentially receives the write request shown in the access request information 10 in FIG. 2A through the Req signal lines of the masters A to C and stores them in the buffer. Each time a write request is received, the arbitration circuit 120 receives the write request. The number of cycles required for data transfer is calculated based on the data transfer amount and the number of bits that can be transmitted in parallel.

The arbitration circuit 120 identifies the master circuit from the Req signal line that received the access request, determines the timing for inputting the command and address from the identified master circuit to the SDRAM 300, and includes the timing including the arbitration result information at the determined timing. A control signal is sent to the access signal generation circuit 130.
In the example of FIG. 2A, the arbitration circuit 120 identifies the master A that has transmitted the access request first via the Req-A signal line.

  The arbitration circuit 120 sends a low-level timing control signal to the access signal generation circuit 130 through the timing control signal line corresponding to the master A111 at the timing T1 in FIG. When receiving the timing control signal, the access signal generation circuit 130 inputs the command signal WRITE-A and address signal ADD-A of the master A111 to the SDRAM 300 at the timing of the rising edge T2 of the clock (ck).

In addition, as shown in FIG. 3, the access signal generation circuit 130 has a rising edge and a falling edge timing of the clock (ck) from T4 one clock after the input of the command signal WRITE-A and the address signal ADD-A. Data signals A0 and A1 are input to the SDRAM 300.
In the example of FIG. 2A, the arbitration circuit 120 specifies the master B 112 as a master circuit for accessing the SDRAM 300 next to the master A 111.

  Since the number of data transfer cycles of the master A111 is two, the arbitration circuit 120 has a master T111 timing at the timing of T3 so that the input of the master B112 data signal can be started from the rising edge of T6 when the master A111 data signal input ends. A low-level timing control signal is sent to the access signal generation circuit 130 through the timing control signal line corresponding to B112.

  When receiving the timing control signal, the access signal generation circuit 130 inputs the command signal WRITE-B and address signal ADD-B of the master B 112 to the SDRAM 300 at the timing of the rising edge T4 of the clock (ck). The access signal generation circuit 130 generates the NOP signal until the next timing control signal is received, and inputs the NOP signal to the SDRAM 300 at the timing of the rising edge T6 of the clock (ck).

Subsequently, the access signal generation circuit 130 receives the command signal WRITE-B and the address signal ADD-B of the master B 112, the data signal B0 at the timing of the rising edge and the falling edge of the clock (ck) from T6 one clock after the input. ... B3 is input to the SDRAM 300.
Subsequently, in the example of FIG. 2A, the arbitration circuit 120 specifies the master C113 as a master circuit that accesses the SDRAM 300 next to the master B112. Since the data transfer cycle of the master B112 is four cycles, the master C113 corresponds to the master C113 at the timing of T7 so that the transmission of the data signal of the master C113 can be started at the rising edge of the clock (ck) of T10 when the data signal input ends. LOW level timing control signal is sent through the timing control signal line.

  When receiving the timing control signal, the access signal generation circuit 130 inputs the command signal WRITE-C and the address signal ADD-C of the master C 113 to the SDRAM 300 at the timing of the rising edge T8 of the clock (ck). Further, the data signals C0 and C1 of the master C113 are input to the SDRAM 300 at the timing of the rising edge and falling edge of the clock (ck) from T10 one clock after the input of the command signal WRITE-C and the address signal ADD-C. .

The SDRAM 300 latches each access signal input at each timing described above at a timing based on the clock.
(2 LSI operation)
FIG. 4 is a timing chart showing temporal changes in which the arbitration circuit 120 that receives an access request from the master circuit of the main LSI 100 and the sub LSI 200 controls data transfer to the SDRAM 300 related to the access request.

This shows the result of the arbitration circuit 120 of the main LSI 100 controlling the data transfer from the master circuits of the main LSI 100 and the sub LSI 200 to the SDRAM 300 based on the access request information 30 illustrated in FIG. .
The access request information 20 shown in FIG. 2B indicates the access request accepted by the arbitration circuit 220 of the sub-LSI 200 as described above, and the arbitration circuit 220 accesses the earliest through the Reqb signal line. The master b 212 that sent the request is selected, an access request including information on the command “Write b” and the transfer amount “8 bytes” is sent to the main LSI 100 through the external Req signal line, and the selection result indicating the master b 212 is stored. To do.

Hereinafter, the operations of the arbitration circuits of the main LSI 100 and the sub LSI 200 and the access signal generation circuit will be described with reference to FIG.
The arbitration circuit 120 of the main LSI 100 specifies the master A 111 that has received the access request first in the access request information 30 of FIG.
The arbitration circuit 120 transmits a low-level timing control signal to the access signal generation circuit 130 through the timing control signal line corresponding to the master A 111 at T1 in FIG. The circuit 130 inputs the command signal WRITE-A and the address signal ADD-A to the SDRAM 300 at the timing T2.

The access signal generation circuit 130 outputs the data signals A0 and A1 at the timing of the rising edge and falling edge of the clock (ck) of T4 one clock after the input of the command signal WRITE-A and the address signal ADD-A. Input to SDRAM 300.
Subsequently, in the access request information 30 in FIG. 2C, the arbitration circuit 120 specifies the sub LSI 200 as an access target because the Req signal line indicating the source of the next access request is “external Req”.

Since the data transfer cycle of the master A111 is two cycles, the arbitration circuit 120 is set to the low level at the timing of T3 so that the data of the sub LSI 200 can be input from the rising edge of the clock (ck) of T6 when the input ends. Is sent to the sub-LSI 200.
When receiving the timing control signal from the main LSI 100, the arbitration circuit 220 of the sub LSI 200 specifies the master b 212 based on the stored selection result, and sends master specifying information indicating the master b 212 to the access signal generation circuit 230.

When receiving the master specifying information, the access signal generating circuit 220 inputs the command signal WRITE-b and address signal ADD-b of the master b 212 indicated by the master specifying information to the SDRAM 300 at the timing of the rising edge T4 of the clock (ck). .
The access signal generation circuit 230 also transfers the data b0 to b3 of the master b212 to the SDRAM 300 at the timing of the rising edge and the falling edge of the clock from T6 one clock after the input of the command signal WRITE-b and the address signal ADD-b. To enter.

The access signal generation circuit 130 of the main LSI 100 receives the NOP until the next access control signal is input at the timing of the rising edge T4 of the clock (ck) after the command signal WRITE-A and the address signal ADD-A are input. A signal is input to the SDRAM 300.
Subsequently, the arbitration circuit 120 of the main LSI 100 specifies the master C 113 as an access target from the access request information 30 in FIG.

Since the data transfer cycle of the sub LSI 200 is four cycles, the arbitration circuit 120 transfers data to the master C113 at the timing of T7 in order to start data transfer of the master C113 from the rising edge of the clock (ck) of T10 when the data transfer ends. A low-level timing control signal is sent to the access signal generation circuit 130 through the corresponding timing control signal line.
When receiving the timing control signal, the access signal generation circuit 130 inputs the command signal WRITE-C and address signal ADD-C of the master C 113 to the SDRAM 300 at the timing of the rising edge T8 of the clock (ck).

The access signal generation circuit 130 receives the data C0, C0 of the master C113 at the timing of the rising edge and falling edge of the clock (ck) from T10 one clock after the input of the command signal WRITE-C and address signal ADD-C of the master C113. C1 is input to the SDRAM 300.
<Discussion>
When the example of FIG. 4 shown in the above-described embodiment is realized by using the conventional technique, it is shown as in FIG.

  In the case of FIG. 6, until the data transfer based on the access request of the master A of the main LSI 100 is completed, the command and address signal related to the access request of the master b of the sub LSI 200 to be transferred next are not output to the SDRAM 300. For this reason, data transfer based on access requests output from the master circuits of the main LSI 100 and the sub LSI 200 is not continuously performed.

  In the above embodiment, as shown in FIG. 4, when the arbitration circuit 120 of the main LSI 100 receives an access request from the master circuit of the own chip and the sub LSI 200, the data transfer of the master A of the own chip is completed. Then, in order to continue the data transfer of the master b of the sub LSI 200, the timing is determined so that the command and address relating to the data transfer are output a predetermined time before the data transfer timing of the master b. The same applies when the access target is switched to the master C.

  As described above, the data transfer period of each master circuit selected as the target for accessing the SDRAM overlaps with the output period of the command and address related to the access request of the master circuit to which data transfer is performed following the data transfer. Therefore, it is possible to output a command and an address relating to the subsequent data transfer in parallel with the previous data transfer, and as a result, as in the case of a single integrated circuit, as an access target of the SDRAM. Data transfer of each selected master circuit can be performed continuously, and data transfer efficiency can be improved as compared with the conventional case.

In the above-described embodiment, the case of data writing has been described, but the same applies to the case of data reading.
<Modification>
FIG. 5 shows a configuration diagram of an integrated circuit system according to a modification of the above-described embodiment.
In the integrated circuit system according to the above-described embodiment, the arbitration circuit on the main LSI 100 side determines not only the arbitration result but also the access timing of each access request, and the access signals of the main LSI 100 and the sub LSI 200 based on the timing. In the present modification, the access timing of each access request is determined by the access signal generation circuit of the main LSI 100, and the data is transferred to the SDRAM 300.

Hereinafter, an integrated circuit system according to this modification will be described.
The arbitration circuit 121 of the main LSI 100 according to the present modification sequentially selects the master circuit or the sub LSI 200 that accesses the SDRAM 300 according to a predetermined rule, as in the embodiment, but the access signal generation circuit 131 of the main LSI 100 includes Only the arbitration result information indicating the selection result is transmitted, and a response signal indicating that the access request has been received is transmitted to the sub-LSI 200.

When receiving the response signal, the arbitration circuit 221 of the sub-LSI 200 specifies the master circuit (ac) that is the source of the access request corresponding to the response signal and accesses the master specifying information as in the embodiment. The signal is sent to the signal generation circuit 231.
The access signal generation circuit 231 generates a command, address, and data access signal for the master circuit indicated in the master identification information, and sends it to the access signal generation circuit 131 of the main LSI 100.

The access signal generation circuit 131 of the main LSI 100 generates an access signal for the master circuits (A to C) in its own chip as in the embodiment, and the generated access signal and the access signal sent from the sub LSI 200 Are sent to the SDRAM 300 based on the arbitration result information so that the data transfer related to each access request is continuously performed.
<Supplement>
As described above, the LSI according to the present invention has been described based on the embodiment. However, the present invention can be modified as follows, and the present invention is not limited to the LSI shown in the above-described embodiment.

  (1) In the present embodiment, the arbitration circuit 120 has been described using the arbitration rule that identifies the master circuit that accesses the SDRAM 300 in the order in which the access requests are received. However, for example, the arbitration rule should give priority to the access request. The master circuit priority order may be a rule determined by the user, or information indicating the arbitration rule may be acquired from the sub-LSI 200, and the arbitration of the access request may be dynamically changed according to the acquired rule. .

  (2) In the above-described embodiment, an access request is received from each master circuit, the master circuit to be accessed by the SDRAM 300 is specified, and the command, address, and data of the master circuit specified by the arbitration circuit are sent to the SDRAM and accessed. In the above description, the control operation is performed by the arbitration circuit and the access signal circuit. However, a configuration in which these operations are performed by one circuit may be employed.

  (3) In the above-described embodiment, the case where one sub-LSI is connected to the main LSI has been described, but when there are two or more sub-LSIs, the arbitration circuit of the main LSI issues an access request from each of the sub-LSIs. Accepting, arbitrating according to a predetermined arbitration rule, sending a timing control signal indicating the arbitration result and access timing to each sub-LSI, each sub-LSI generating an access signal in each LSI, indicated by the timing control signal The access signal may be sent to the SDRAM at the same timing.

(4) In the above-described embodiment, the clock is supplied to the main LSI 100 and the sub LSI 200. However, the clock is supplied to the main LSI 100, and the clock for phase adjustment is output from the main LSI 100 to the sub LSI 200. The sub LSI 200 may access at a timing based on the clock.
(5) In the above-described embodiment, it has been described that the arbitration circuit 120 determines the data transfer timing in the own chip. However, the access signal generation circuit 130 determines the data transfer timing in the own chip. Also good. In this case, the arbitration circuit 120 sends only the arbitration result information to the access signal generation circuit 130 for access to the master circuit in its own chip, and the access signal generation circuit 130 performs the master circuit in the order indicated by the arbitration result information. A signal such as a command from is sent at a timing based on the clock. The arbitration circuit 120 has a function of monitoring the status of data transfer between the access signal generation circuit 130 and the SDRAM 300. Based on the status of data transfer to the SDRAM 300, access from the master circuit of the own chip and the sub LSI 200 is performed. The access timing of the sub LSI 200 is determined and an access control signal is transmitted so that the data transfer related to the request can be continuously performed.

(6) In the above-described embodiment, the case where the SDRAM 300 is a DDR SDRAM has been described. However, a DRAM that operates in synchronization with an external clock such as a single data rate synchronous DRAM (SDR SDRAM) may be used. However, the present invention is not limited to this as long as it is a clock-synchronized recording device that performs data transfer.
(7) In the above-described embodiment, the arbitration circuit 120 and the access signal generation circuit 130 of the main LSI 100 are described as being connected through the timing control signal line for each master circuit (A to C). As long as the access timing of the circuit can be transmitted, serial transmission or other parallel transmission may be used.

(8) In the above-described embodiment, it has been described that the access signal generation circuit 130 of the main LSI 100 outputs a control signal to the SDRAM 300 based on the timing control signal, but the access signal generation circuit 230 of the sub LSI 200 to the SDRAM 300 A control signal may be output.
(9) In the above embodiment, each master circuit of the main LSI 100 and the sub LSI 200 has been described as sending an access request including the data transfer amount to the arbitration circuit. However, the data transfer amount of each master circuit is fixed. If it is long, each master circuit may not send the data transfer amount to the arbitration circuit in the access request.

  The integrated circuit system and the integrated circuit according to the present invention can be used for information equipment such as an image processing apparatus.

1 is a configuration diagram of an integrated circuit system according to an embodiment. FIG. (a) shows an example of access request information stored in the buffer of the arbitration circuit 120 in the case of only the main LSI 100 according to the embodiment. (b) shows an example of access request information stored in the buffer of the arbitration circuit 220 when an access request is issued from the main LSI 100 and the sub LSI 200 according to the embodiment, and (c) shows the embodiment. An example of access request information stored in the buffer of the arbitration circuit 120 when an access request is issued from the main LSI 100 and the sub LSI 200 is shown. 5 is a timing chart showing temporal changes for controlling data transfer when an access request is accepted only from the main LSI 100. 6 is a timing chart showing temporal changes for controlling data transfer when an access request is received from a main LSI 100 and a sub LSI 200. FIG. 6 shows a configuration diagram of an integrated circuit system according to a modification of the embodiment. It is the figure which represented the example of FIG. 4 of embodiment using the prior art.

Explanation of symbols

100 Main LSI
111 Master A
112 Master B
113 Master C
120, 121 Arbitration circuit of main LSI 130, 131 Access signal generation circuit of main LSI 200 Sub LSI
211 Master a
212 Master b
213 Master c
220, 221 Sub-LSI arbitration circuit 230, 231 Sub-LSI access signal generation circuit 300 SDRAM

Claims (7)

A plurality of master circuits that share an external recording device and issue an access request including an address for data transfer to the recording device, and selectively select one of the plurality of master circuits to the recording device; An integrated circuit chip for controlling access of the plurality of master circuits by accessing
An input interface that accepts access requests from a master circuit external to the chip;
If an access request from the external master circuit is received by the time the data transfer based on the access request of one of the plurality of master circuits selected to access the recording device is completed, the data The output timing of the address is determined so that an address according to an access request from the external master circuit is output during transfer, and the external master circuit is accessed according to the determined timing. And an access control circuit for controlling the integrated circuit chip. The integrated circuit chip has an output interface for outputting timing information for instructing an output timing of an address to the recording device to the outside of the chip,
When the access control circuit receives an access request from the plurality of master circuits and the external master circuit, the access control circuit sequentially selects a master circuit that causes the recording apparatus to access from the master circuit that has issued the received access request. And an arbitration circuit that determines the output timing of the address, and an access signal generation circuit that generates an access signal based on an access request of the plurality of master circuits,
When the external master circuit is selected as the master circuit to be accessed by the recording apparatus, the arbitration circuit outputs the timing information indicating the determined output timing of the address from the output interface, and When the master circuit is selected, arbitration result information indicating the selected master circuit is sent to the access signal generation circuit,
The integrated circuit chip according to claim 1, wherein the access signal generation circuit generates an access signal based on an access request of a master circuit indicated by the arbitration result information and sends the access signal to the recording device. A plurality of master circuits that share an external recording device and issue an access request including an address for data transfer to the recording device, and selectively select one of the plurality of master circuits to the recording device; An integrated circuit chip for controlling access of the plurality of master circuits by accessing
An input interface that accepts access requests from a master circuit external to the chip;
Based on each access request received from the plurality of master circuits and the external master circuit, under a predetermined condition, select any of the plurality of master circuits to perform data transfer to the recording device, and then The decision is made to transfer data to an external master circuit, and the output timing of the address related to the access request of the master circuit is determined by a predetermined time before the data transfer timing of each master circuit. An access control circuit that determines whether or not it overlaps with a period during which the recording is performed, and controls the master circuit to access the recording device according to the determined output timing. A plurality of master circuits that share an external recording device and issue an access request including an address for data transfer to the recording device, and selectively select one of the plurality of master circuits to the recording device; An integrated circuit chip for controlling access of the plurality of master circuits by accessing
An output interface for outputting the access request to the outside of the chip;
An input interface that accepts timing information indicating the output timing of the address related to the output access request from the outside;
Accepting the access request from each of the plurality of master circuits, sequentially outputting the access request from the output interface according to a predetermined rule, accepting the timing information from the input interface, and based on the accepted timing information, And an access control circuit that controls the master circuit that issued the access request to access.   2. The integrated circuit chip according to claim 1, wherein the recording device is an SDRAM (Synchronous Dynamic Random Access Memory). An integrated circuit system in which an external recording device is shared by a first integrated circuit chip and a second integrated circuit chip,
The first integrated circuit chip is:
A plurality of master circuits for issuing an access request including an address for data transfer to the recording device;
An input interface for receiving an access request from a master circuit in the second integrated circuit chip;
An output interface for outputting timing information for instructing an output timing of an address to the recording device to the second integrated circuit chip;
The access request from the master circuit in the second integrated circuit chip is accepted until the data transfer based on the access request of one of the plurality of master circuits selected to access the recording device is completed. The output timing of the address is determined so as to output an address related to an access request from the master circuit of the second integrated circuit chip during the data transfer, and the master circuit of the second integrated circuit chip An access control circuit for controlling the recording apparatus to access according to the determined timing,
The second integrated circuit chip is
A plurality of master circuits for issuing an access request including an address for data transfer to the recording device;
An output interface for outputting the access request to the first integrated circuit chip;
An input interface for receiving the timing information from the outside;
The access request is received from each of the plurality of master circuits, the access request is sequentially output from the output interface to the first integrated circuit chip according to a predetermined rule, and the timing information is received and received from the input interface. An integrated circuit system comprising: an access control circuit that controls the master circuit that issued the output access request to access based on the timing information. A data processing apparatus comprising a first integrated circuit chip, a second integrated circuit chip, and a recording device,
The first integrated circuit chip is:
A plurality of master circuits for issuing an access request including an address for data transfer to the recording device;
An input interface for accepting the access request from a master circuit in the second integrated circuit chip;
An output interface that outputs timing information for instructing access timing to the recording device to the second integrated circuit chip;
The access request from the master circuit in the second integrated circuit chip is accepted until the data transfer based on the access request of one of the plurality of master circuits selected to access the recording device is completed. The output timing of the address is determined so as to output an address related to an access request from the master circuit of the second integrated circuit chip during the data transfer, and the master circuit of the second integrated circuit chip An access control circuit for controlling the recording apparatus to access according to the determined timing,
The second integrated circuit chip is
A plurality of master circuits for issuing an access request including an address for data transfer to the recording device;
An output interface for outputting the access request to the first integrated circuit chip;
An input interface that accepts timing information indicating the output timing of the address related to the output access request from the outside;
The access request is received from each of the plurality of master circuits, the access request is sequentially output from the output interface to the first integrated circuit chip according to a predetermined rule, and the timing information is received and received from the input interface. A data processing apparatus comprising: an access control circuit that controls the master circuit that issued the output access request to perform access based on the timing information.

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