JP4902196B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having an array configuration in which memory cells each having two memory function bodies for storing information according to the amount of charge are arranged in a matrix. .

  Conventionally, in the MONOS memory, an insulating film is used as a charge holding layer, and an oxide film is formed between the charge holding layer and the substrate. In the MONOS memory structure, if the oxide film between the charge retention layer and the substrate is thin, charge loss due to a tunnel current is likely to occur, and there is a concern that the reliability of the memory may be reduced.

  For write / erase operations, FN (Fowler-Nordheim) tunnel current is used, but high voltage operation is required to realize write / erase by FN tunnel current. Furthermore, hot electron writing and band-to-band tunneling hot hole erasing are desirable to achieve high reliability and low voltage operation. In addition, in order to further increase the capacity, a NAND array structure is desired.

  Also, in the following Patent Document 1, a NAND type array employing hot electron writing is reported as an SI (Source Side Injection) -NAND type flash memory. As shown in FIG. It has an array configuration in which cell transistors 2 are connected in series.

Japanese Patent No. 3020355

  However, the conventional NAND type array as shown in FIG. 2 has a memory cell array configuration in which a stack gate 5 composed of a floating gate 3 and a control gate 4 is connected in series via a diffusion layer 6, and the integration density of the memory cells. However, as described above, writing and erasing are performed with the FN tunnel current, which is an obstacle to realizing high reliability and low voltage operation. Further, in order to perform writing for storing 2 bits in one memory cell, channel hot electron writing is required, which is a problem.

  Further, in the SI-NAND array configuration as shown in FIG. 1, each memory cell transistor 2 is connected in series via the auxiliary gate 1, so that a high electric field is applied between the auxiliary gate 1 and the diffusion layer 6. Therefore, it is difficult to erase by hot hole injection.

  The present invention has been made in view of the above problems, and its object is to achieve low voltage operation and increase in capacity by enabling hot electron writing and hot hole erasing by band-to-band tunneling in a NAND array configuration. An object of the present invention is to provide a suitable nonvolatile semiconductor memory device.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes two diffusion regions formed on a semiconductor surface and one side of the diffusion region on a channel region between the two diffusion regions. A memory function body that stores information according to the amount of charge formed on the first channel region and a first memory transistor unit comprising a control gate, and a second channel adjacent to the other side of the diffusion region on the channel region A memory function body for storing information according to the amount of charge formed on the region and a second memory transistor portion comprising a control gate; and a position between the first channel region and the second channel region in the channel region A memory cell having a split gate structure having a gate insulating film formed on the third channel region and an auxiliary transistor portion including an auxiliary gate The memory cell unit group having a NAND type configuration in which a plurality of knits are connected in series, the memory cell unit group sharing one diffusion region between adjacent memory cell units, and sharing the diffusion region No contact is provided.

  Further, in addition to the above characteristics, the nonvolatile semiconductor memory device according to the present invention can apply the same voltage to the control gates of the first and second memory transistor units in units of the memory cell unit. To do.

  Furthermore, in addition to any of the above features, the nonvolatile semiconductor memory device according to the present invention includes the memory function body and the control gate of the first and second memory transistor portions, It is characterized by being formed in a side wall shape in a self-aligned manner on both sides.

  Furthermore, in addition to any of the above features, the nonvolatile semiconductor memory device according to the present invention has one of the diffusion regions located at both ends of the memory cell unit group connected to one of the two bit lines, and the other being A plurality of the memory cell unit groups are connected in parallel between the two bit lines along the extending direction of the two bit lines, connected to the other of the two bit lines. To do.

  Furthermore, in addition to any of the above features, the nonvolatile semiconductor memory device according to the present invention includes a plurality of memory cell unit groups arranged in a parallel direction of a plurality of bit lines parallel to each other. One of the diffusion regions located at both ends is connected to one of the two bit lines, the other is connected to the other of the two bit lines, and the two memory cell unit groups adjacent in the parallel direction are One of the diffusion regions located at both ends of the memory cell unit group is commonly connected to one bit line.

  Furthermore, in addition to the above characteristics, the nonvolatile semiconductor memory device according to the present invention can write data in one memory cell unit of the memory cell unit group by using the memory cell unit group including the memory cell unit to be written. When the two bit lines respectively connected to the diffusion regions located at both ends are selected bit lines, and the bit lines that are not the selected bit lines are non-selected bit lines, the two selected bits A predetermined voltage is applied to the non-selected bit line adjacent to the selected bit line having a higher applied voltage in the line, and a ground voltage is applied to the other non-selected bit lines, or a floating state is set. It is characterized by performing by doing.

  Furthermore, in addition to any one of the above features, the nonvolatile semiconductor memory device according to the present invention writes the memory cell unit of one of the memory cell unit groups in the diffusion region located at both ends of the memory cell unit group. A write voltage is applied in between, and hot electrons are injected into the memory function body of the first or second memory transistor portion of the memory cell unit to be written from the third channel region side. To do.

  Furthermore, in addition to any one of the above features, the nonvolatile semiconductor memory device according to the present invention can erase one of the memory cell units of the memory cell unit group by using the diffusion region located at both ends of the memory cell unit group. The erasing positive voltage supplied from at least one of the memory cell units is applied to at least one of the two diffusion regions of the memory cell unit to be erased, and the erasing positive voltage is applied from the diffusion region. It is performed by injecting hot holes into the memory function body, or a positive voltage for erasure supplied from both of the diffusion regions located at both ends of the memory cell unit group is set to 2 of the memory cell unit to be erased. Hot diffusion is applied to each of the two memory functional units from the two diffusion regions to which the positive voltage for erasure is applied. And performing by Le injection. Here, when erasing one of the memory cell units of the memory cell unit group, applying an erasing negative voltage to the control gate of the memory cell unit to be erased, and further, the memory cell unit to be erased It is preferable to apply a negative voltage to the auxiliary gate.

  The memory cell unit may be erased by hot electron injection instead of hot hole injection, and the memory cell unit may be written by hot hole injection. In other words, if both writing and erasing are regarded as changes in the amount of charge accumulated in the memory function body, either the change due to hot hole injection or the change due to hot electron injection may be treated as writing or erasing. is there.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a nonvolatile semiconductor memory device according to the present invention (referred to as “device of the present invention” as appropriate) and a control method related to the memory operation will be described below with reference to the drawings.

<First Embodiment>
FIG. 3 schematically shows a schematic configuration of a memory cell unit 10 provided in the device of the present invention and a memory cell unit group 30 formed by connecting two memory cell units 10 in series. 3A is a plan view showing only the auxiliary gate 21, the element isolation region 11 and the active region 12 between them, and FIG. 3B is an active region shown in FIG. 12 is a cross-sectional view taken along the line XX ′ on FIG. FIG. 3C is an equivalent circuit diagram in which the memory cell unit 10 is represented by three transistor portions described later.

  As shown in FIG. 3, one memory cell unit 10 includes two diffusion regions 13 formed in the active region 12 and first channels arranged in order on a channel region 14 between the two diffusion regions 13. The memory transistor unit 15, the auxiliary transistor unit 17, and the second memory transistor unit 16 are provided. The first memory transistor unit 15 and the second memory transistor unit 16 have a memory function body 18 for storing information on the first channel region 14a and the second channel region 14b adjacent to the two diffusion regions 13 according to the amount of charges. And the control gate 19 are stacked. The auxiliary transistor portion 17 includes a gate insulating film 20 and an auxiliary gate 21 formed on the third channel region 14c located between the first channel region 14a and the second channel region 14b. More specifically, the auxiliary gate 21 is formed of polysilicon or polysilicon and a metal salicide film in a stripe pattern orthogonal to X-X ′ as shown in FIG. The memory function body 18 and the control gate 19 of the first memory transistor section 15 and the second memory transistor section 16 become the memory function body 18 and the control gate 19 on the auxiliary transistor section 17 after forming the auxiliary transistor section 17. By sequentially depositing and etching back the film, both sides of the auxiliary gate 21 are formed in a self-aligned manner in a sidewall shape. The memory function body 18 is formed of a trapping film having a function of capturing and accumulating electrons, such as silicon oxide film-silicon nitride film-silicon oxide film (ONO film), and the control gate 19 is formed of, for example, polysilicon. Etc. are formed. The diffusion region 13 is formed by forming the first memory transistor portion 15 and the second memory transistor portion 16 and then implanting N-type impurity ions using the transistor portions 15 to 17 as a mask. The memory cell unit 10 is configured as one split gate type memory cell transistor, and the two diffusion regions 13 serve as a source electrode and a drain electrode of the memory cell transistor. Further, since the diffusion region 13 is formed simultaneously with the source / drain of the peripheral transistor for the peripheral circuit, a shallow diffusion layer can be formed.

  The control gates 19 of the first memory transistor unit 15 and the second memory transistor unit 16 are formed separately in FIG. 3B, but in this embodiment, the same control voltage is applied on the circuit. It is configured as possible.

  In the present embodiment, the memory cell unit group 30 is configured by connecting two memory cell units 10 in series. Two memory cell units 10 share one diffusion region 13b. Although not shown, the two diffusion regions 13a and 13c located at both ends of the memory cell unit group 30 are connected to metal wirings (bit lines) through contacts as signal input / output terminals in a memory operation to be described later. It will be. The intermediate diffusion region 13b is a node for connecting the two memory cell units 10 and is not used as a signal input / output terminal. Therefore, it is not necessary to connect to the metal wiring through the contact. Therefore, the larger the number of memory cell units 10 constituting the memory cell unit group 30, the smaller the memory cell area per storage unit.

  When the number of memory cell units 10 constituting the memory cell unit group 30 is three or more, FIG. 3 shows a part of two adjacent memory cell units 10.

  Next, the memory operation (data read operation, write operation, and erase operation) for the memory cell unit group 30 of the device of the present invention will be described. Here, in the description of all the memory operations, as shown in FIGS. 4 to 6, the control gates 19 of the two memory cell units 10a and 10b in the memory cell unit group 30 are CG0 and CG1, respectively, and the auxiliary gate 21 Are WL0 and WL1, respectively, and the four memory transistor portions 15 and 16 are M0A, M0B, M1A and M1B, respectively. The two diffusion regions 13a and 13c located at both ends of the memory cell unit group 30 are SD0 and SD2, and the intermediate diffusion region 13b is SD1.

(Read operation)
With reference to FIG. 4, a read operation from any memory transistor unit M0A, M0B, M1A, M1B of the memory cell unit group 30 will be described.

  At the time of reading from the memory transistor unit M0A on the memory cell unit 10a side, as shown in FIG. 4A, first, 0V and 1.5V (read voltage) are applied using SD0 as a source and SD2 as a drain, respectively. Then, 7V and 3V are applied to the control gate CG1 and the auxiliary gate WL1, respectively, so as to make the non-selected memory cell unit 10b side a conductive transfer gate, thereby forming an inversion layer in the channel region. Thereby, in the selected memory cell unit 10a, SD0 serves as a source and SD1 serves as a drain, and a read voltage is applied between SD0 and SD1. 0V and 3V are applied to the control gate CG0 and the auxiliary gate WL0 on the side of the selected memory cell unit 10a, respectively, and the auxiliary transistor is turned on. Also, the drain current (read current) flowing through the selected memory cell unit 10a is caused by the diffusion layer extending from the drain SD1, and the charge accumulation amount (whether written or erased) in the memory transistor of the memory transistor portion M0B on the drain SD1 side. And is determined largely by the charge storage amount of the memory storage body of the memory transistor portion M0A to be read on the source SD0 side. Therefore, the larger the charge accumulation amount (electron accumulation amount) of the memory storage body of the memory transistor portion M0A, the higher the threshold voltage of the memory transistor portion M0A. If the threshold voltage is higher than the applied voltage 0V to the control gate CG0 on the selected memory cell unit 10a side, the memory transistor unit M0A is turned off and the selected memory cell unit 10a is turned off. If the threshold voltage is lower, the memory transistor unit M0A Is turned on and the selected memory cell unit 10a becomes conductive, and the memory transistor portion M0A can be read.

  Next, a read operation of the memory transistor unit M0B on the memory cell unit 10a side will be described. As shown in FIG. 4B, first, 0V and 1.5V (read voltage) are applied to SD2 as a source and SD0 as a drain, respectively. Then, 7V and 3V are applied to the control gate CG1 and the auxiliary gate WL1, respectively, so as to make the non-selected memory cell unit 10b side a conductive transfer gate, thereby forming an inversion layer in the channel region. Thus, in the selected memory cell unit 10a, SD0 serves as a drain and SD1 serves as a source, and a read voltage is applied between SD0 and SD1. 0V and 3V are applied to the control gate CG0 and the auxiliary gate WL0 on the side of the selected memory cell unit 10a, respectively, and the auxiliary transistor is turned on. Further, the drain current (read current) flowing through the selected memory cell unit 10a is not largely influenced by the charge accumulation amount of the memory storage body of the memory transistor portion M0A on the drain SD0 side due to the extension of the diffusion layer from the drain SD0, and is exclusively. This is determined by the charge storage amount of the memory storage body of the memory transistor portion M0B to be read on the source SD1 side. Therefore, the larger the charge accumulation amount (electron accumulation amount) of the memory storage body of the memory transistor unit M0B, the higher the threshold voltage of the memory transistor unit M0B. When the threshold voltage is higher than the applied voltage 0V to the control gate CG0 on the selected memory cell unit 10a side, the memory transistor unit M0B is turned off and the selected memory cell unit 10a is turned off. When the threshold voltage is lower, the memory transistor unit M0B Is turned on and the selected memory cell unit 10a becomes conductive, and the memory transistor M0B can be read.

  Since the read operation of the memory transistor units M1A and M1B on the memory cell unit 10b side may be performed in accordance with the operation on the memory cell unit 10a side, a duplicate description is omitted.

  When the number of memory cell units 10 constituting the memory cell unit group 30 is three or more, only the number of memory cell units 10 that are not selected increases, and voltage application conditions for the control gate 19 and the auxiliary gate 21 that are selected and not selected. May be handled in the same manner as in the case of two memory cell units 10.

(Write operation)
Next, with reference to FIG. 5, a write operation to an arbitrary memory transistor portion M0A, M0B, M1A, M1B of the memory cell unit group 30 will be described.

  At the time of writing in the memory transistor unit M0A on the memory cell unit 10a side, as shown in FIG. 5A, first, 4V (write voltage) and 0V are applied using SD0 as a drain and SD2 as a source, respectively. Then, 10V and 7V are applied to the control gate CG1 and the auxiliary gate WL1, respectively, so as to make the non-selected memory cell unit 10b side a conductive transfer gate, thereby forming an inversion layer in the channel region. Thereby, in the selected memory cell unit 10a, SD0 serves as a drain and SD1 serves as a source, and a write voltage is applied between SD0 and SD1. When a write voltage of 10V is applied to the control gate CG0 on the selected memory cell unit 10a side, 0.5V close to the threshold voltage of the auxiliary transistor is applied to the auxiliary gate WL0, and the auxiliary transistor is turned on slightly, the opposite side A current flows between SD0 and SD1 regardless of the write state of the memory transistor portion M0B. That is, electrons used for writing flow from the source (SD1) side to the drain (SD0) side. Here, since a high electric field is generated between the memory transistor portion M0A in the channel region 14 of the selected memory cell unit 10a and the auxiliary gate WL0, the memory function of the memory transistor portion M0A from the source side (channel region side of the auxiliary transistor). Accelerated toward the body, hot electrons are injected, and writing to the memory transistor portion M0A is performed. For the memory transistor portion M0B on the opposite side, since a high electric field is not generated between the memory transistor portion M0B and the auxiliary gate WL0 in the channel region 14, electrons are not sufficiently accelerated and the memory of the memory transistor portion M0B Hot electrons are not injected into the functional body.

  Next, a write operation of the memory transistor unit M0B on the memory cell unit 10a side will be described. As shown in FIG. 5B, first, 4V (write voltage) and 0V are applied to SD2 as a drain and SD0 as a source, respectively. Then, 10V and 7V are applied to the control gate CG1 and the auxiliary gate WL1, respectively, so as to make the non-selected memory cell unit 10b side a conductive transfer gate, thereby forming an inversion layer in the channel region. In this case, since the drain voltage 4V is supplied to the selected memory cell unit 10a via the non-selected memory cell unit 10b, the applied voltage of the control gate CG1 is set high. Thus, in the selected memory cell unit 10a, SD1 serves as a drain and SD0 serves as a source, and a write voltage is applied between SD0 and SD1. When a write voltage of 10V is applied to the control gate CG0 on the selected memory cell unit 10a side, 0.5V close to the threshold voltage of the auxiliary transistor is applied to the auxiliary gate WL0, and the auxiliary transistor is turned on slightly, the opposite side A current flows between SD0 and SD1 regardless of the write state of the memory transistor portion M0A. That is, electrons used for writing flow from the source (SD0) side to the drain (SD1) side. Here, since a high electric field is generated between the memory transistor portion M0B in the channel region 14 of the selected memory cell unit 10a and the auxiliary gate WL0, the memory function of the memory transistor portion M0B from the source side (channel region side of the auxiliary transistor). Accelerated toward the body, hot electrons are injected, and writing to the memory transistor portion M0B is performed. For the memory transistor portion M0A on the opposite side, since a high electric field is not generated between the memory transistor portion M0A in the channel region 14 and the auxiliary gate WL0, electrons are not sufficiently accelerated and the memory of the memory transistor portion M0A Hot electrons are not injected into the functional body.

  As described above, SSI (Source Side Injection) writing by hot electron injection from the source side is performed on any of the memory transistor units M0A and M0B on the memory cell unit 10a side. The efficiency can be increased, the write current can be reduced, and the drain voltage can be suppressed to 5 V or less, so that the voltage and current consumption can be reduced.

  Since the write operation of the memory transistor units M1A and M1B on the memory cell unit 10b side may be performed in accordance with the operation on the memory cell unit 10a side, a duplicate description is omitted.

  When the number of memory cell units 10 constituting the memory cell unit group 30 is three or more, only the number of memory cell units 10 that are not selected increases, and voltage application conditions for the control gate 19 and the auxiliary gate 21 that are selected and not selected. May be handled in the same manner as in the case of two memory cell units 10.

(Erase method)
Next, with reference to FIG. 6, the erasing operation of the arbitrary memory transistor units M0A, M0B, M1A, M1B of the memory cell unit group 30 will be described.

  When erasing the memory transistor unit M0A on the memory cell unit 10a side, as shown in FIG. 6A, first, 4V (positive voltage for erasure) and 0V are applied using SD0 as a drain and SD2 as a source, respectively. Then, 10V and 3V are applied to the control gate CG1 and the auxiliary gate WL1, respectively, so as to make the non-selected memory cell unit 10b side a conductive transfer gate, thereby forming an inversion layer in the channel region. As a result, in the selected memory cell unit 10a, SD0 serves as a drain, SD1 serves as a source, and SD1 is grounded to 0V. When a negative voltage of -6V for erasing is applied to the control gate CG0 on the selected memory cell unit 10a side and a gate voltage lower than the threshold voltage, for example, a negative voltage is applied to the auxiliary gate WL0 to turn off the auxiliary transistor, Regardless of the writing state of the memory transistor portion M0B, an interband current flows through the end of the drain SD0, and hot holes are injected into the memory storage body of the memory transistor portion M0A due to the high voltage difference between the control gate CG1 and the drain SD0. The threshold voltage of the memory transistor portion M0A decreases, and the memory transistor portion M0A is erased. Here, by applying a negative voltage to the auxiliary gate WL0, the efficiency of hot hole injection is increased and the erase speed can be increased. In the memory transistor portion M0B on the opposite side, a sufficient voltage difference is not applied between the control gate CG1 and the source SD1, and erasing is not performed.

  Next, the erase operation of the memory transistor unit M0B on the memory cell unit 10a side will be described. As shown in FIG. 6B, first, 4 V (erasing positive voltage) and 0 V are applied to SD2 as a drain and SD0 as a source, respectively. Then, 10V and 3V are applied to the control gate CG1 and the auxiliary gate WL1, respectively, so as to make the non-selected memory cell unit 10b side a conductive transfer gate, thereby forming an inversion layer in the channel region. Thereby, in the selected memory cell unit 10a, SD1 serves as a drain and SD0 serves as a source, and 4V (positive voltage for erasure) is applied to SD1. When a negative voltage of -6V for erasing is applied to the control gate CG0 on the selected memory cell unit 10a side and a gate voltage lower than the threshold voltage, for example, a negative voltage is applied to the auxiliary gate WL0 to turn off the auxiliary transistor, Regardless of the write state of the memory transistor portion M0A, an interband current flows through the end of the drain SD1, and hot holes are injected into the memory storage of the memory transistor portion M0B due to the high voltage difference between the control gate CG1 and the drain SD1. The threshold voltage of the memory transistor portion M0B decreases, and the memory transistor portion M0B is erased. Here, by applying a negative voltage to the auxiliary gate WL0, the efficiency of hot hole injection is increased and the erase speed can be increased. In the memory transistor portion M0A on the opposite side, a sufficient voltage difference is not applied between the control gate CG1 and the source SD0, and erasing is not performed.

  Next, the erasing operation of both the memory transistor units M0A and M0B on the memory cell unit 10a side will be described. As shown in FIG. 6C, first, 4V (erasing positive voltage) is applied to both terminals SD2 and SD0. Then, 10V and 3V are applied to the control gate CG1 and the auxiliary gate WL1, respectively, so as to make the non-selected memory cell unit 10b side a conductive transfer gate, thereby forming an inversion layer in the channel region. As a result, 4 V (erasable positive voltage) is applied to SD1 and SD0 in the selected memory cell unit 10a. When a negative voltage of -6V for erasing is applied to the control gate CG0 on the selected memory cell unit 10a side, and a gate voltage lower than the threshold voltage, for example, a negative voltage is applied to the auxiliary gate WL0 to turn off the auxiliary transistor, SD0 and SD1 A band-to-band current flows through both drain ends, and a high voltage difference between the control gate CG1 and the drains SD0 and SD1 causes hot holes to be injected into both memory storage bodies of the memory transistor portions M0A and M0B. , M0B are lowered, and both of the memory transistor portions M0A, M0B are erased simultaneously. Here, by applying a negative voltage to the auxiliary gate WL0, the efficiency of hot hole injection is increased and the erase speed can be increased.

  In each of the above erasing operations, the same erasing is simultaneously performed on the other memory cell unit group 30 sharing the auxiliary gate WL0 if the voltages applied to the SD0 and SD2 at both ends are similarly performed.

  The erasing operation of the memory transistor units M1A and M1B on the memory cell unit 10b side may be performed in accordance with the operation on the memory cell unit 10a side, and thus a duplicate description is omitted.

  When the number of memory cell units 10 constituting the memory cell unit group 30 is three or more, only the number of memory cell units 10 that are not selected increases, and voltage application conditions for the control gate 19 and the auxiliary gate 21 that are selected and not selected. May be handled in the same manner as in the case of two memory cell units 10.

Next, an example of a memory cell array configuration using the memory cell unit group 30 is shown in FIG. As shown in FIG. 7, the memory cell array used in the device of the present invention has memory cells in the row direction (extension direction of the auxiliary gate 21 and the control gate 19) and the column direction (extension direction of the bit lines _{BL0 to k} ), respectively. A plurality of unit groups 30 are arranged.

In each of the plurality of memory cell unit groups 30 in the same column, one diffusion region 13 is connected to _one of two bit lines BL _i and BL _{i + 1} , and the other diffusion region 13 is connected to the two bit lines BL _i. , BL _{i + 1} , and connected in parallel between the two bit lines BL _i , BL _{i + 1} . Each bit line BL is formed of a metal wiring, and each diffusion region 13 at both ends of the memory cell unit group 30 is connected to the bit line BL through a contact, but an external signal wiring is connected to the intermediate diffusion region. There is no contact for connection with.

The plurality of memory cell unit groups 30 in the same row arranged in the row direction (the parallel direction of the bit lines _{BL0 to k} ) share the auxiliary gate 21 and the control gate 19 with each other, and the diffusion region 13 at one end. Is connected to one of the two bit lines BL _i and BL _{i + 1} (i = 0 to k−1) in parallel, and the other diffusion region 13 is connected to the other of the two bit lines BL _i and BL _{i + 1} . Connect to. Here, in the two memory cell unit groups 30 adjacent in the row direction, one of the diffusion regions 13 at both ends is commonly connected to one bit line BL _j (j = 1 to k−1).

Therefore, when one or a plurality of memory cell unit groups 30 are selected from the memory cell array shown in FIG. 7 and each of the above memory operations is executed, adjacent memory cell unit groups 30 that are the target of the memory operation are connected. Two bit lines and two sets of auxiliary gates 21 and control gates 19 are selected, and a predetermined operating voltage is applied as described above. With respect to the non-selected memory cell unit group 30 adjacent to the selected memory cell unit group 30 in the row direction, the voltage between the adjacent bit lines is set to 0 V, and the other non-selected memory cell unit groups 30 are compared with each other. Causes the bit line to float. Further, the auxiliary gate 21 and the control gate 19 of the non-selected memory cell unit group 30 are grounded to 0V, respectively, and each memory cell unit 10 is deactivated. FIG. 8 is a table showing an example of operating conditions of each memory operation for the memory cell array shown in FIG. Incidentally, the erase operation shown in FIG. 8, it is assumed that collectively erased memory cell units 10 in the same row to be connected to the auxiliary gate WL _n.

  In the write operation condition shown in FIG. 8, when writing to the memory transistor unit Mn, 1 (B), in addition to the above-described operation condition, two bit lines BL0 connected to the selected memory cell unit group 30 are used. , BL1 (selected bit line) of the non-selected bit line BL2 adjacent to the selected bit line BL1 on the high voltage (4 V applied) side is close to the threshold voltage of the auxiliary transistor applied to the auxiliary gate WLn. By applying the same voltage as 5 V, the auxiliary transistor of the non-selected memory cell unit group between the bit lines BL1 and BL2 is turned off, and the two bit lines BL1 and BL2 connected to the non-selected memory cell unit group are not connected. It becomes conduction. In this voltage application method, among the unselected bit lines connected only to the unselected memory cell unit group located on the selected bit line side on the high voltage (4 V applied) side, the selected bit line BL1 on the high voltage (4 V applied) side. Except for the non-selected bit line BL2 adjacent to, no voltage application is required (0V application or floating), and the non-selected bit lines can be made non-conductive, which is advantageous in reducing power consumption. .

  In the memory cell array shown in FIG. 7, which of the selected two bit lines becomes the source or drain depending on which memory cell unit 10 in the memory cell unit group 30 to be subjected to the memory operation is selected. Changes. Therefore, the memory cell array of the device of the present invention has a virtual ground NAND type array configuration in which bit lines and virtual ground lines can be interchanged.

  The memory cell array configuration of the device of the present invention has been described in detail above. However, as long as the memory cell unit group 30 configured by connecting a plurality of memory cell units 10 in series is used, the memory cell array configuration is shown in FIG. It is not limited to examples. The voltage condition in each memory operation is an example, and can be set as appropriate according to the specific memory configuration.

Second Embodiment
Next, a second embodiment of the device of the present invention will be described. In the second embodiment, unlike the first embodiment, a case will be described in which a plurality of memory cell units 10 are connected in series and used as a single memory cell unit 10 without constituting a memory cell unit group.

  FIG. 9 schematically shows a schematic configuration of the single memory cell unit 10. FIG. 9A is a plan view showing only the auxiliary gate 21, the element isolation region 11, and the active region 12 between them, and FIG. 9B shows the active region shown in FIG. 12 is a cross-sectional view taken along the line XX ′ on FIG. FIG. 9C is an equivalent circuit diagram in which the memory cell unit 10 is represented by three transistor portions described later.

  As shown in FIG. 9, one memory cell unit 10 includes two diffusion regions 13 formed in the active region 12 and first channels arranged in order on a channel region 14 between the two diffusion regions 13. The memory transistor unit 15, the auxiliary transistor unit 17, and the second memory transistor unit 16 are provided. The first memory transistor unit 15 and the second memory transistor unit 16 have a memory function body 18 for storing information on the first channel region 14a and the second channel region 14b adjacent to the two diffusion regions 13 according to the amount of charges. And the control gate 19 are stacked. The auxiliary transistor portion 17 includes a gate insulating film 20 and an auxiliary gate 21 formed on the third channel region 14c located between the first channel region 14a and the second channel region 14b. More specifically, the auxiliary gate 21 is formed of polysilicon or polysilicon and a metal salicide film in a stripe pattern orthogonal to X-X ′ as shown in FIG. The memory function body 18 and the control gate 19 of the first memory transistor section 15 and the second memory transistor section 16 become the memory function body 18 and the control gate 19 on the auxiliary transistor section 17 after forming the auxiliary transistor section 17. By sequentially depositing and etching back the film, both sides of the auxiliary gate 21 are formed in a self-aligned manner in a sidewall shape. The memory function body 18 is formed of a trapping film having a function of capturing and accumulating electrons, such as silicon oxide film-silicon nitride film-silicon oxide film (ONO film), and the control gate 19 is formed of, for example, polysilicon. Etc. are formed. The diffusion region 13 is formed by forming the first memory transistor portion 15 and the second memory transistor portion 16 and then implanting N-type impurity ions using the transistor portions 15 to 17 as a mask. The memory cell unit 10 is configured as one split gate type memory cell transistor, and the two diffusion regions 13 serve as a source electrode and a drain electrode of the memory cell transistor. Further, since the diffusion region 13 is formed simultaneously with the source / drain of the peripheral transistor for the peripheral circuit, a shallow diffusion layer can be formed.

  Each control gate 19 of the first memory transistor portion 15 and the second memory transistor portion 16 is formed separately in FIG. 9B, but in this embodiment, the same control voltage is applied on the circuit. It is configured as possible.

  In this embodiment, since the memory cell unit 10 is used as a single unit, the two diffusion regions 13a and 13b located at both ends of the memory cell unit 10 are not shown, but are used as signal input / output terminals in a memory operation to be described later. The two metal wirings (bit lines) are connected separately through contacts. Here, in order to reduce the memory cell area per storage unit, two diffusion regions are formed between two memory cell units 10 adjacent to each other in the bit line extending direction (XX ′ direction in FIG. 9A). One and the other of 13a and 13b share one diffusion region and one contact. Between the two memory cell units 10 adjacent to each other in the extending direction of the auxiliary gate 21 (parallel direction of the bit lines), one of the two diffusion regions 13a and 13b shares one contact, and the two bit lines Connect to one of these. As a result, one memory cell unit 10 has one contact with the other three memory cell units 10 adjacent in the extending direction of the bit line and the extending direction of the auxiliary gate 21 on one side of the two diffusion regions 13a and 13b. Similarly, the other side of the two diffusion regions 13a and 13b shares one contact with the other three memory cell units 10 adjacent to each other in the extending direction of the bit line and the extending direction of the auxiliary gate 21. The number of contacts required per memory cell unit 10 is 0.5.

  Next, memory operations (data read operation, write operation, and erase operation) for the memory cell unit 10 of the present invention device will be described. Here, in the description of all the memory operations, as shown in FIGS. 10 to 12, the two control gates 19 of the memory cell unit 10 are CG and are configured to be electrically applied with the same voltage, and the auxiliary gate 21 is It is assumed that WL1 and the two memory transistor portions 15 and 16 are MA and MB, respectively. The two diffusion regions 13a and 13b located at both ends of the memory cell unit 10 are denoted as SD0 and SD1.

(Read operation)
With reference to FIG. 10, the read operation from the arbitrary memory transistor portions MA and MB of the memory cell unit 10 will be described.

  At the time of reading from the memory transistor portion MA, as shown in FIG. 10A, first, 0V and 1.5V (read voltage) are applied to SD0 as a source and SD1 as a drain, respectively. Thereby, a read voltage is applied between SD0 and SD1. 0V and 3V are applied to the control gate CG and the auxiliary gate WL, respectively, and the auxiliary transistor is turned on. Also, the drain current (read current) flowing through the memory cell unit 10 is caused by the extension of the diffusion layer from the drain SD1, so that the charge accumulation amount (whether written or erased) in the memory storage body of the memory transistor unit MB on the drain SD1 side. It is determined largely by the amount of charge stored in the memory storage body of the memory transistor unit MA to be read on the source SD0 side. Therefore, the larger the charge accumulation amount (electron accumulation amount) of the memory storage body of the memory transistor portion MA, the higher the threshold voltage of the memory transistor portion MA. When the threshold voltage is higher than 0 V applied to the control gate CG, the memory transistor unit MA is turned off and the memory cell unit 10 is turned off. When the threshold voltage is lower, the memory transistor unit MA is turned on and the memory cell unit 10 is turned off. Becomes conductive, and the memory transistor portion MA can be read.

  Next, a read operation of the memory transistor unit MB will be described. As shown in FIG. 10B, first, 0V and 1.5V (read voltage) are applied to SD1 as a source and SD0 as a drain, respectively. Thereby, a read voltage is applied between SD0 and SD1. 0V and 3V are applied to the control gate CG and the auxiliary gate WL, respectively, and the auxiliary transistor is turned on. Further, the drain current (readout current) flowing through the memory cell unit 10 is not greatly affected by the amount of charge accumulated in the memory storage body of the memory transistor portion MA on the drain SD0 side due to the extension of the diffusion layer from the drain SD0. It is determined by the charge storage amount of the memory storage body of the memory transistor unit MB to be read on the source SD1 side. Therefore, as the charge accumulation amount (electron accumulation amount) of the memory storage unit of the memory transistor unit MB increases, the threshold voltage of the memory transistor unit MB increases. When the threshold voltage is higher than 0 V applied to the control gate CG, the memory transistor unit MB is turned off and the memory cell unit 10 is turned off. When the threshold voltage is lower, the memory transistor unit MB is turned on and the memory cell unit 10 is turned off. Becomes conductive, and the memory transistor MB can be read.

  Here, in the non-selected memory cell unit 10 in the same column in which the selected memory cell unit 10 to be read and the diffusion regions SD0 and SD1 are connected to the same bit line, the auxiliary transistor is turned off by applying 0 V to the auxiliary gate WL. In this state, the drain current (readout current) does not flow between SD0 and SD1 and is deactivated.

(Write operation)
Next, with reference to FIG. 11, a write operation to arbitrary memory transistor portions MA and MB of the memory cell unit 10 will be described.

  At the time of writing in the memory transistor portion MA, as shown in FIG. 11A, first, 4V (write voltage) and 0V are applied to SD0 as a drain and SD1 as a source, respectively. As a result, a write voltage is applied between SD0 and SD1. When a write voltage of 10 V is applied to the control gate CG, 0.5 V close to the threshold voltage of the auxiliary transistor is applied to the auxiliary gate WL, and the auxiliary transistor is turned on slightly, the write state of the memory transistor unit MB on the opposite side Regardless of the current, a current flows between SD0 and SD1. That is, electrons used for writing flow from the source (SD1) side to the drain (SD0) side. Here, since a high electric field is generated between the memory transistor part MA and the auxiliary gate WL in the channel region 14 of the memory cell unit 10, the memory function body of the memory transistor part MA from the source side (channel region side of the auxiliary transistor). Then, hot electrons are injected and data is written into the memory transistor portion MA. Note that a high electric field is not generated between the memory transistor part MB and the auxiliary gate WL in the channel region 14 for the memory transistor part MB on the opposite side, so electrons are not sufficiently accelerated and the memory of the memory transistor part MB is not generated. Hot electrons are not injected into the functional body.

  Next, the write operation of the memory transistor unit MB will be described. As shown in FIG. 11B, first, 4V (write voltage) and 0V are applied to SD1 as a drain and SD0 as a source, respectively. As a result, a write voltage is applied between SD0 and SD1. When a write voltage of 10V is applied to the control gate CG, 0.5V close to the threshold voltage of the auxiliary transistor is applied to the auxiliary gate WL, and the auxiliary transistor is turned on slightly, the write state of the memory transistor portion MA on the opposite side Regardless of the current, a current flows between SD0 and SD1. That is, electrons used for writing flow from the source (SD0) side to the drain (SD1) side. Here, since a high electric field is generated between the memory transistor portion MB in the channel region 14 of the selected memory cell unit 10 and the auxiliary gate WL, the memory function of the memory transistor portion MB from the source side (channel region side of the auxiliary transistor). It is accelerated toward the body and injected with hot electrons, and writing to the memory transistor unit MB is performed. Note that a high electric field is not generated between the memory transistor portion MA and the auxiliary gate WL in the channel region 14 for the memory transistor portion MA on the opposite side. Hot electrons are not injected into the functional body.

  As described above, SSI (Source Side Injection) writing by hot electron injection from the source side is performed for any of the memory transistor portions MA and MB, and the injection efficiency can be increased. The write current can be reduced, and the drain voltage can be suppressed to 5 V or less, so that the voltage can be reduced and the current consumption can be reduced.

  Here, in the non-selected memory cell unit 10 in the same column where the selected memory cell unit 10 to be written and the diffusion regions SD0 and SD1 are connected to the same bit line, the auxiliary transistor is turned off by applying 0 V to the auxiliary gate WL. In this state, the drain current (write current) does not flow between SD0 and SD1 and is deactivated. In addition, no write voltage is applied to the control gate CG.

(Erase method)
Next, with reference to FIG. 12, an erasing operation of arbitrary memory transistor portions MA and MB of the memory cell unit 10 will be described.

  At the time of erasing the memory transistor portion MA, as shown in FIG. 12A, first, 4V (erasing positive voltage) and 0V are applied using SD0 as a drain and SD1 as a source, respectively. Further, when a negative voltage of -6V is applied to the control gate CG and a gate voltage lower than a threshold voltage, for example, a negative voltage, is applied to the auxiliary gate WL to turn off the auxiliary transistor, the memory transistor MB on the opposite side Regardless of the write state, an interband current flows through the end of the drain SD0, and hot holes are injected into the memory storage body of the memory transistor unit MA due to a high voltage difference between the control gate CG and the drain SD0. The voltage drops and the memory transistor portion MA is erased. Here, by applying a negative voltage to the auxiliary gate WL, the efficiency of hot hole injection is increased and the erase speed can be increased. In the opposite memory transistor portion MB, a sufficient voltage difference is not applied between the control gate CG and the source SD1, and erasing is not performed.

  Next, the erase operation of the memory transistor unit MB will be described. As shown in FIG. 12B, first, 4V (erasing positive voltage) and 0V are applied to SD1 as a drain and SD0 as a source, respectively. Further, when a negative voltage of -6V is applied to the control gate CG and a gate voltage lower than a threshold voltage, for example, a negative voltage, is applied to the auxiliary gate WL to turn off the auxiliary transistor, the memory transistor MA of the opposite side Regardless of the write state, an inter-band current flows through the end of the drain SD1, and a high voltage difference between the control gate CG and the drain SD1 causes a hot hole to be injected into the memory storage body of the memory transistor unit MB. The threshold voltage decreases and the memory transistor unit MB is erased. Here, by applying a negative voltage to the auxiliary gate WL, the efficiency of hot hole injection is increased and the erase speed can be increased. In the memory transistor portion MA on the opposite side, a sufficient voltage difference is not applied between the control gate CG and the source SD0, and erasing is not performed.

  Next, the simultaneous erasing operation of both memory transistor portions MA and MB will be described. As shown in FIG. 12C, first, 4V (erasing positive voltage) is applied to both terminals SD1 and SD0. Further, when a negative voltage of -6V is applied to the control gate CG and a gate voltage lower than a threshold voltage, for example, a negative voltage, is applied to the auxiliary gate WL to turn off the auxiliary transistor, the drain terminals of both SD0 and SD1 A band-to-band current flows through the gate, and a high voltage difference between the control gate CG and the drains SD0 and SD1 causes hot holes to be injected into both memory storages of the memory transistor units MA and MB. The voltage drops, and both memory transistor parts MA and MB are erased simultaneously. Here, by applying a negative voltage to the auxiliary gate WL, the efficiency of hot hole injection is increased and the erase speed can be increased.

  In each of the above erasing operations, the same erasing is performed at the same time for the other memory cell units 10 sharing the auxiliary gate WL if the voltages applied to SD0 and SD1 at both ends are similarly performed.

  Here, the non-selected memory cell unit 10 in the same column in which the selected memory cell unit 10 to be erased and the diffusion regions SD0 and SD1 are connected to the same bit line applies, for example, a positive voltage for erasing to the auxiliary gate WL. A high voltage is not applied between the control gate CG and the drains SD0 and SD1, and hot holes are deactivated without being injected into the memory storage bodies of the memory transistor portions MA and MB. Also, 0V is applied to the auxiliary gate WL to turn it off, thereby preventing unnecessary current from flowing between SD0 and SD1.

Next, an example of a memory cell array configuration using the memory cell unit 10 is shown in FIG. As shown in FIG. 13, the memory cell array used in the device of the present invention in the second embodiment has a row direction (extension direction of the auxiliary gate 21 and the control gate 19) and a column direction (extension direction of the bit lines _{BL0 to k} ). Each of the memory cell units 10 is configured by arranging a plurality of memory cell units 10.

In each of the plurality of memory cell units 10 in the same column, one diffusion region 13 is connected to _one of the two bit lines BL _i and BL _{i + 1} , and the other diffusion region 13 is connected to the two bit lines BL _i , Connected to the other of BL _{i + 1} and connected in parallel between the two bit lines BL _i and BL _{i + 1} . Each bit line BL is formed by a metal wiring, and each diffusion region 13 at both ends of the memory cell unit 10 and the bit line BL are connected via a contact.

The plurality of memory cell units 10 in the same row arranged in the row direction (the parallel direction of the bit lines _{BL0 to k} ) share the auxiliary gate 21 and the control gate 19 with each other, and the diffusion region 13 at one end is formed. Connected to one of the two bit lines BL _i and BL _{i + 1} (i = 0 to k−1) in parallel, and the diffusion region 13 at the other end is connected to the other of the two bit lines BL _i and BL _{i + 1} . Connecting. Here, in the two memory cell units 10 adjacent in the row direction, one of the diffusion regions 13 at both ends is commonly connected to one bit line BL _j (j = 1 to k−1).

Therefore, when one or a plurality of memory cell units 10 are selected from the memory cell array shown in FIG. 13 and each of the memory operations is executed, two adjacent memory cell units 10 connected to the memory operation target 10 are connected. One bit line, two sets of auxiliary gates 21 and control gate 19 are selected, and a predetermined operating voltage is applied as described above. For the non-selected memory cell unit 10 adjacent to the selected memory cell unit 10 in the row direction, the voltage between the adjacent bit lines is set to 0V, and for the other non-selected memory cell units 10, the bit is Make the line floating. Further, the auxiliary gate 21 and the control gate 19 of the non-selected memory cell unit 10 are grounded to 0V, respectively, and each memory cell unit 10 is deactivated. FIG. 14 is a table showing an example of operating conditions of each memory operation for the memory cell array shown in FIG. Incidentally, the erase operation shown in FIG. 14, it is assumed that collectively erased memory cell units 10 in the same row to be connected to the auxiliary gate WL _n.

  In the write operation condition shown in FIG. 14, when writing to the memory transistor portion Mn, 1 (B), in addition to the above-described operation condition, two bit lines BL0, BL0 connected to the selected memory cell unit 10 are used. A non-selected bit line BL2 adjacent to the selected bit line BL1 on the high voltage (4 V applied) side of BL1 (selected bit line) is 0.5 V close to the threshold voltage of the auxiliary transistor applied to the auxiliary gate WLn. , The auxiliary transistor of the non-selected memory cell unit between the bit lines BL1 and BL2 is turned off, and the two bit lines BL1 and BL2 connected to the non-selected memory cell unit become non-conductive. . In this voltage application method, among the unselected bit lines connected only to the unselected memory cell units located on the selected bit line side on the high voltage (4 V applied) side, the selected bit line BL1 on the high voltage (4 V applied) side is applied. Except for the adjacent non-selected bit line BL2, voltage application is not required (0V application or floating), and non-conduction bit lines can be made non-conductive, which is advantageous in reducing power consumption.

  In the memory cell array shown in FIG. 13, which of the two selected bit lines becomes the source or drain depends on which memory transistor unit in the memory cell unit 100 that is the target of the memory operation is selected. To do. Therefore, the memory cell array of the device of the present invention has a virtual ground type array configuration in which bit lines and virtual ground lines can be interchanged.

  Although the memory cell array configuration of the device of the present invention has been described in detail above, the memory cell array configuration is not limited to the embodiment shown in FIG. The voltage condition in each memory operation is an example, and can be set as appropriate according to the specific memory configuration.

  Next, another embodiment of the device of the present invention will be described.

  In the erase operation in each of the above embodiments, the case where a negative voltage for erase of −6 V is applied to the control gate CG of the memory cell unit 10 to be erased has been described, but the diffusion region SD1 on the memory transistor unit side to be erased or It is sufficient if a high voltage sufficient for erasing is applied between SD0 and control gate CG. If the positive voltage for erasing applied to diffusion region SD1 or SD0 is high, the voltage applied to control gate CG is not necessarily a negative voltage. You don't have to.

  INDUSTRIAL APPLICABILITY The nonvolatile semiconductor memory device according to the present invention can be used for a nonvolatile semiconductor memory device, and more specifically, memory cells including two memory function bodies that store information according to the amount of charge are arranged in a matrix. This is useful for a nonvolatile semiconductor memory device having the above array configuration.

Element cross-sectional view schematically showing a conventional SI-NAND array configuration Element cross-sectional view schematically showing a conventional NAND gate array structure with a stacked gate structure The top view, sectional drawing, and equivalent circuit diagram which show typically the memory cell unit group which comprises the NAND type array in 1st Embodiment of the non-volatile semiconductor memory device based on this invention Sectional drawing which shows the operating condition in read-out operation | movement of the memory cell unit group in 1st Embodiment of the non-volatile semiconductor memory device based on this invention. Sectional drawing which shows the operating condition in write-in operation | movement of the memory cell unit group in 1st Embodiment of the non-volatile semiconductor memory device based on this invention. Sectional drawing which shows the operating condition in erase | eliminating operation | movement of the memory cell unit group in 1st Embodiment of the non-volatile semiconductor memory device concerning this invention. 1 is an equivalent circuit diagram schematically showing a NAND array configuration in a first embodiment of a nonvolatile semiconductor memory device according to the present invention; Table showing operating conditions of each memory operation for the NAND array configuration in the first embodiment of the nonvolatile semiconductor memory device according to the present invention. The top view, sectional drawing, and equivalent circuit diagram which show typically the memory cell unit group which comprises the virtual ground type array in 2nd Embodiment of the non-volatile semiconductor memory device which concerns on this invention Sectional drawing which shows the operating condition in read-out operation | movement of the memory cell unit group in 2nd Embodiment of the non-volatile semiconductor memory device concerning this invention. Sectional drawing which shows the operating condition in write-in operation | movement of the memory cell unit group in 2nd Embodiment of the non-volatile semiconductor memory device based on this invention. Sectional drawing which shows the operating condition in erase | eliminating operation | movement of the memory cell unit group in 2nd Embodiment of the non-volatile semiconductor memory device based on this invention. The equivalent circuit schematic which shows typically the virtual ground type | mold array structure in 2nd Embodiment of the non-volatile semiconductor memory device based on this invention Table showing operating conditions of each memory operation for the virtual ground type array configuration in the second embodiment of the nonvolatile semiconductor memory device according to the present invention

Explanation of symbols

1: Auxiliary gate 2: Memory cell transistor 3: Floating gate 4: Control gate 5: Stack gate 6: Diffusion layer 10, 10a, 10b: Memory cell unit 11: Element isolation region 12: Active region 13, 13a, 13b, 13c : Diffusion region 14: Channel region 14a: First channel region 14b: Second channel region 14c: Third channel region 15: First memory transistor portion 16: Second memory transistor portion 17: Auxiliary transistor portion 18: Memory function body 19 : Control gate 20: Gate insulating film 21: Auxiliary gate 30: Memory cell unit group CG, CG0, CG1: Control gates BL _{0 to} BL _k : Bit lines MA, MB, M0A, M0B, M1A, M1B: Memory transistor section SD0 , SD1, SD2: diffusion region W , WL0, WL1: auxiliary gate

Claims (12)

Two diffusion regions formed on the semiconductor surface;
A first memory transistor unit comprising a memory function body for storing information according to the amount of charge formed on the first channel region adjacent to one side of the diffusion region on the channel region between the two diffusion regions and a control gate When,
A second memory transistor unit comprising a memory function body for storing information according to the amount of charge formed on the second channel region adjacent to the other side of the diffusion region on the channel region, and a control gate;
An auxiliary transistor portion comprising a gate insulating film and an auxiliary gate formed on a third channel region located between the first channel region and the second channel region in the channel region;
A memory cell unit group having a NAND type structure in which a plurality of memory cell units having a split gate structure are connected in series,
The nonvolatile semiconductor memory device, wherein the memory cell unit group shares one diffusion region between adjacent memory cell units, and the shared diffusion region does not have a contact.   The nonvolatile semiconductor memory device according to claim 1, wherein the same voltage can be applied to the control gates of the first and second memory transistor units in units of the memory cell unit.   The memory function body and the control gate of the first and second memory transistor portions are formed in a side wall shape in a self-aligned manner on both sides of the auxiliary gate of the auxiliary transistor portion. Item 3. The nonvolatile semiconductor memory device according to Item 1 or 2.   One of the diffusion regions located at both ends of the memory cell unit group is connected to one of the two bit lines, the other is connected to the other of the two bit lines, and a plurality of the memory cell unit groups are 4. The nonvolatile semiconductor memory device according to claim 1, wherein the two bit lines are connected in parallel along the extending direction of the two bit lines. 5. A plurality of the memory cell unit groups are arranged in a parallel direction of a plurality of bit lines parallel to each other,
One of the diffusion regions located at both ends of the memory cell unit group is connected to one of the two bit lines, the other is connected to the other of the two bit lines,
2. The two memory cell unit groups adjacent in the parallel direction, wherein one of the diffusion regions located at both ends of the memory cell unit group is commonly connected to one bit line. Item 5. The nonvolatile semiconductor memory device according to any one of Items 1 to 4.   The writing of one memory cell unit of the memory cell unit group is performed by two bits connected to the diffusion regions located at both ends of the memory cell unit group including the memory cell unit to be written. When the selected bit line is a selected bit line and the bit line that is not the selected bit line is a non-selected bit line, the non-selected bit line adjacent to the selected bit line with the higher applied voltage of the two selected bit lines is used. 6. The nonvolatile semiconductor memory according to claim 5, wherein a predetermined voltage is applied to the selected bit line and a ground voltage is applied to the other non-selected bit lines, or a floating state is set. apparatus.   For writing to one memory cell unit of the memory cell unit group, a write voltage is applied between the diffusion regions located at both ends of the memory cell unit group, and the first or second of the memory cell unit to be written is written. The nonvolatile semiconductor memory device according to claim 1, wherein hot electron injection is performed from the third channel region side to the memory function body of a two-memory transistor section.   In erasing one memory cell unit of the memory cell unit group, a positive voltage for erasure supplied from at least one of the diffusion regions located at both ends of the memory cell unit group is set to be erased from the memory cell unit to be erased. The method is performed by applying at least one of the two diffusion regions and injecting hot holes from the diffusion region to which the positive voltage for erasure is applied to the memory function body. 8. The nonvolatile semiconductor memory device according to any one of items 7.   In erasing one memory cell unit of the memory cell unit group, a positive voltage for erasure supplied from both of the diffusion regions located at both ends of the memory cell unit group is set to 2 of the memory cell unit to be erased. 8. The method according to claim 1, wherein said hot diffusion is performed by individually injecting hot holes from said two diffusion regions to which said positive voltage for erasure is applied to said two memory function bodies. The non-volatile semiconductor memory device according to any one of the above.   10. The nonvolatile memory according to claim 8, wherein a negative voltage for erasure is applied to the control gate of the memory cell unit to be erased when erasing one memory cell unit of the memory cell unit group. Semiconductor memory device.   11. The negative voltage according to claim 8, wherein a negative voltage is applied to an auxiliary gate of the memory cell unit to be erased when erasing one of the memory cell units in the memory cell unit group. Nonvolatile semiconductor memory device.   7. The nonvolatile semiconductor memory device according to claim 1, wherein writing into the memory cell unit is performed by hot hole injection and erasing of the memory cell unit is performed by hot electron injection.