JP4996179B2 - Icカード、及びicカードの製造方法 - Google Patents
Icカード、及びicカードの製造方法 Download PDFInfo
- Publication number
- JP4996179B2 JP4996179B2 JP2006236745A JP2006236745A JP4996179B2 JP 4996179 B2 JP4996179 B2 JP 4996179B2 JP 2006236745 A JP2006236745 A JP 2006236745A JP 2006236745 A JP2006236745 A JP 2006236745A JP 4996179 B2 JP4996179 B2 JP 4996179B2
- Authority
- JP
- Japan
- Prior art keywords
- antenna
- card
- terminal
- module
- connection terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Credit Cards Or The Like (AREA)
Description
図1は、本発明の一実施の形態である接触、非接触の両方式で外部とデータ通信を行うことができるコンビカードの等価回路を示すものである。
Claims (4)
- 内蔵アンテナを有するカード基材と、
このカード基材に形成され、前記内蔵アンテナの端子を露出させる収納用凹部と、
基板と、この基板の一面側に配設されるLSI、及び該LSIに接続されるアンテナ接続端子と、前記基板の他面側に配設される接触通信用の接続端子、及び予備用の接続端子と、前記基板に穿設され、前記予備用の接続端子に対向する貫通孔と、前記アンテナ接続端子或いは、前記アンテナ接続端子と前記貫通孔に亘って供給される導電性接着部材とを有して構成されるICモジュールとを具備し、
前記ICモジュールは、前記カード基材の収納用凹部内に前記基板の一面側から収納されることにより前記内蔵アンテナの端子に対し、前記導電性接着部材を介して前記アンテナ接続端子、或いは、前記予備用の接続端子を電気的に接続させることを特徴とするICカード。 - 前記予備用の接続端子は非接触通信に用いられることを特徴とする請求項1記載のICカード。
- 内蔵アンテナを有するカード基材に収納用凹部を形成することにより、前記内蔵アンテナの端子を露出させる工程と、
基板の一面側にLSI、及び該LSIに接続されるアンテナ接続端子を配設し、前記基板の他面側に接触通信用の接続端子、及び予備用の接続端子を配設し、前記基板に前記予備用の接続端子に対向する貫通孔を穿設してICモジュールを構成する工程と、
前記ICモジュールの前記アンテナ接続端子或いは、前記アンテナ接続端子と前記貫通孔に亘って導電性接着部材を塗布する工程と、
前記ICモジュールをその基板の一面側から前記カード基材の収納用凹部内に収納することにより前記内蔵アンテナの端子に対し、前記導電性接着部材を介して前記アンテナ接続端子、或いは、前記予備用の接続端子を電気的に接続する工程と
を具備することを特徴とするICカードの製造方法。 - 前記収納用凹部の形成時に、前記アンテナの両端子を切断することを特徴とする請求項3記載のICカードの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006236745A JP4996179B2 (ja) | 2006-08-31 | 2006-08-31 | Icカード、及びicカードの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006236745A JP4996179B2 (ja) | 2006-08-31 | 2006-08-31 | Icカード、及びicカードの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008059370A JP2008059370A (ja) | 2008-03-13 |
JP4996179B2 true JP4996179B2 (ja) | 2012-08-08 |
Family
ID=39242008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006236745A Expired - Fee Related JP4996179B2 (ja) | 2006-08-31 | 2006-08-31 | Icカード、及びicカードの製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4996179B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5932470B2 (ja) * | 2012-05-08 | 2016-06-08 | 株式会社東芝 | Icカード |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4839510B2 (ja) * | 2001-01-17 | 2011-12-21 | 大日本印刷株式会社 | カード基体、icカード及びその製造方法 |
JP4422494B2 (ja) * | 2003-05-07 | 2010-02-24 | 大日本印刷株式会社 | Icカードおよびsim |
JP4580725B2 (ja) * | 2004-10-08 | 2010-11-17 | 大日本印刷株式会社 | Uim用icカードと小型サイズuim |
-
2006
- 2006-08-31 JP JP2006236745A patent/JP4996179B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008059370A (ja) | 2008-03-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7352588B2 (en) | Semiconductor device and a method for manufacturing the same | |
US20050014298A1 (en) | Memory card with raised portion | |
US9390365B2 (en) | Integrated circuit module for a dual-interface smart card | |
JP2007004775A (ja) | 半導体メモリカード | |
WO2007125948A1 (ja) | アンテナ内蔵電子回路モジュールとその製造方法 | |
JP2006252390A (ja) | Icカードの製造方法およびicカード | |
US7621457B2 (en) | Reader / writer and method for manufacturing the same | |
JP7474251B2 (ja) | チップカード用電子モジュール | |
CN109583552B (zh) | 用于制造便携式数据载体的方法及数据载体主体 | |
JP4996179B2 (ja) | Icカード、及びicカードの製造方法 | |
CN108370087B (zh) | 具有cms器件的单面天线模块 | |
JP2009116647A (ja) | 複合型icカードおよびその製造方法 | |
JP2002288618A (ja) | 携帯可能電子媒体及び電子回路部品 | |
JP2009075782A (ja) | Icモジュール及びicカード | |
JPH06344692A (ja) | 薄型モジュール | |
US8763912B1 (en) | Dual interface module and dual interface card having a dual interface module | |
JP2011170525A (ja) | カード基材及びこのカード基材を有するicカード | |
JP5195241B2 (ja) | 耐熱性icタグストラップ | |
KR101427339B1 (ko) | 알에프아이디 카드 및 그 제조방법 | |
KR100789893B1 (ko) | 메모리 카드 및 여기에 사용되는 메모리 소자 | |
JP2010072930A (ja) | Icモジュール、及びこれを用いたicカード | |
US6275158B1 (en) | Device arranged for contactless communication and provided with a data carrier with fully enclosed connection means for electrically connecting a chip and a passive component | |
JP2003067701A (ja) | 非接触通信媒体及びその製造方法 | |
JPH11296633A (ja) | Icカード | |
JP2010238081A (ja) | Icカード及び通信装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090319 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110811 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110906 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111107 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120417 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120511 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150518 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150518 Year of fee payment: 3 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20120529 |
|
A072 | Dismissal of procedure |
Free format text: JAPANESE INTERMEDIATE CODE: A072 Effective date: 20121009 |
|
LAPS | Cancellation because of no payment of annual fees |