JP4839394B2 - Data receiving apparatus and data receiving method - Google Patents

Description

The present invention relates to a data receiver for a digital video signal, and more particularly to a data receiver for transmitting a control signal and additional data during a blanking period of a digital video signal.

  Conventionally, for example, when a video signal is transmitted to a liquid crystal monitor or a CRT, an analog RGB interface is used and the video signal is analogly transmitted. However, for example, in a liquid crystal monitor, the number of pixels that can be displayed is determined in advance, and with the spread of this liquid crystal monitor, digital transmission has attracted attention. In addition, it is required to increase the refresh rate in order to reduce flicker, and to send data at high speed to display images on a wider screen. Conventional analog transmission has a large transmission distortion and ghosting occurs. Therefore, the importance of digital transmission is increasing along with the improvement in image quality.

With the demand for digital transmission, DVI (Digital Visual Interface) has been attracting attention in recent years. This DVI is an interface for digital display connection defined by the Digital Display Working Group (DDWG), and transfers data using a plurality of data channels based on TMDS (Transition Minimized Differential Signaling) technology. If a digital transmission method using DVI is used, high-quality video data with less transmission distortion can be provided at low cost by digital transmission.
In addition, there exist the following as a prior art.

DDWG (Digital Display Working Group), Digital Visual Interface DVI, April 1999, Rev.1.0, p.24-32, http://www.ddwg.org/register/index.php3

  Thus, by adopting DVI, it is possible to obtain a screen with higher image quality than analog transmission. In addition, in DVI, there is a blanking period in which other data can be transmitted in addition to a period in which RGB (Red, Green, Blue) pixel data is transmitted. For example, an audio signal can be transmitted using this blanking period.

  Here, when digital video signals are transmitted, transmission errors such as garbled bits may occur. However, in the case of video signals, even if transmission errors occur, the screen will not be noticeable and will be a big problem. There is no. However, for example, when a transmission error occurs during transmission of an audio signal, noise or abnormal noise may occur, and the error rate needs to be considered to be stricter than when a video signal is transmitted. In other words, when data with conspicuous errors other than video signals is transmitted using a blanking period of DVI, separate processing for error detection and error correction is required. Since processing for error detection and error correction generally requires a lot of hardware, there has been a problem that the apparatus becomes larger and the cost is increased.

The present invention has been made to solve such a technical problem, and an object of the present invention is to provide a data receiving apparatus capable of simplifying a circuit configuration and improving an error rate with respect to superimposed data. Is to provide etc.
Another object is to improve the error rate by simplifying the circuit configuration.

For this purpose, the present invention transmits video data using the first, second and third channels in the DVI format , and represents the synchronization signal in the blanking period of the video data of the first channel. Data is arranged and transmitted, and a plurality of codes having a predetermined number of types are arranged and transmitted in the blanking period of the video data of the second channel and the third channel, respectively. And a data receiving device for receiving the data of the third three channels, means for extracting the code arranged in the blanking period from the video data transmitted through the second channel and the third channel, Means for obtaining audio data from the data relating to the audio signal corresponding to the received code. The video data transmitted through the third channel is configured to include at least three times the same data relating to the audio signal corresponding to the code.

Here, it is preferable to further include a buffer for accumulating and outputting the audio data, and a timing generation means for generating a timing for outputting the audio data from the buffer.
It is preferable to further include a PLL circuit for converting the transmitted clock into a pixel clock and supplying the converted pixel clock to the timing generation means.

Furthermore, according to the present invention, video data is transmitted using the first, second and third channels in the DVI format, and data representing a synchronization signal is arranged in the blanking period of the video data of the first channel. The first, second, and third 3 are transmitted and transmitted by arranging a plurality of codes having a predetermined number of types in the blanking period of the video data of the second channel and the third channel. In a data receiving method for receiving data of one channel, a step of extracting a code arranged in a blanking period from video data transmitted by a second channel and a third channel, and corresponding to the extracted code Obtaining audio data from data relating to the audio signal, the second channel and the second channel Of the video data transmitted by the channel, characterized in that the same data according to the audio signal corresponding to the code is configured to include at least three times.

According to the data receiving apparatus and the like of the present invention, the error rate for the superimposed data can be improved by simplifying the circuit configuration.

It is the figure which showed an example of the digital video signal transmission / reception system to which this Embodiment is applied. It is a figure for demonstrating the structure of a transmission part. (a), (b) is a figure for demonstrating a DVI transmission timing. It is a figure for demonstrating code allocation in this Embodiment. It is a figure for demonstrating the structure of the receiving part shown in FIG. It is a timing chart for demonstrating the judgment by a receiving part with respect to the data of 10 bit strings sent. (a), (b) is a figure for demonstrating the 1st majority processing method implemented in a majority processing part. It is a figure for demonstrating the 2nd majority processing method implemented in a majority processing part. (a), (b) is a figure for demonstrating the 3rd majority processing method implemented in a majority processing part. (a)-(d) is a figure for demonstrating the specific example of the calculation by the 3rd majority process method shown by Fig.9 (a), (b). It is the figure which showed the relationship with the data error in the symbol actually received with respect to the error of a transmission line.

Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings.
FIG. 1 is a diagram showing an example of a digital video signal transmission / reception system to which the present embodiment is applied. Here, a digital tuner 10 which is a digital video signal transmitting side (transmitter) and a monitor 20 which is a digital video signal receiving side (receiver) are provided. The digital tuner 10 and the monitor 20 are: They are connected by a line 9 that supports DVI (Digital Visual Interface) which is an interface for digital display connection.

  The digital tuner 10 receives, for example, a high-frequency radio wave in which digital data such as compressed video and audio is modulated by the antenna 8, and outputs the digital data such as compressed video and audio by releasing the modulation. It has. The output from the front end 11 is decoded by an AV (Audio Visual) decoder 12, passed to the transmission unit 30, and output as a digital video signal via the line 9.

  The digital component video signal sent to the monitor 20 via the line 9 is input to the receiving unit 50 and decoded. The decoded RGB pixel data is converted into an analog signal by the D / A converter 21 and amplified by the amplifier (RGB AMP) 22. The output from the amplifier 22 is synchronized by a horizontal / vertical synchronization signal (H / V SYNC) 23 acquired by the receiving unit 50 and displayed on the CRT 24. On the other hand, the audio signal obtained by the receiving unit 50 is converted into an analog signal by the D / A converter 25 and output by the speaker 26 as sound.

  FIG. 2 is a diagram for explaining the configuration of the transmission unit 30. The transmission unit 30 to which this exemplary embodiment is applied outputs a digital signal applied to DVI to the reception unit 50 via the line 9. The transmission unit 30 assigns a code longer than the bit length of the RGB video data and converts it into serial data for transmission. In addition, using the blanking period, superimposed data that is additional data such as audio data is transmitted, and the superimposed data is characterized in that the same data is repeatedly transmitted.

  As a specific configuration, the transmission unit 30 inputs encoder data 31, 32, 33 that converts 8-bit RGB pixel data that is input into 10-bit serial data, superimposition data such as audio data, and the timing And a timing generator 35 for receiving the blanking signal and the pixel clock and generating a timing for outputting the superimposed data. Also, a PLL (Phase-Locked Loop) 36 that converts a parallel 8-bit pixel clock into a serial 10-bit clock, inquires about the frequency that can be synchronized with the monitor 20, and what capabilities the monitor 20 supports. Is provided with a DDC (Display Data Channel) 37 for transmitting and receiving data. The 2-bit and 1-bit superimposition data output from the buffer 34 is converted into 10-bit serial data during the blanking period (video blanking period) and output to the receiving side. The CTL 3 input to the encoder 31 can include information related to the control of the monitor 20, for example. The encoder 33 also receives horizontal synchronization (HSYNC) and vertical synchronization (VSYNC) signals. Note that, instead of RGB pixel data, video data including Y as luminance and RY and BY as color differences may be input.

  3A and 3B are diagrams for explaining the DVI transmission timing. 3A shows the transmission timing before entering the encoders 31, 32, and 33, and FIG. 3B shows the DVI transmission timing output from the encoders 31, 32, and 33. As shown in FIG. 3A, a video blanking period (Blanking) is provided following 3-channel data of 8 bits for each of RGB. As shown in FIG. 3B, the outputs from the encoder 31, the encoder 32, and the encoder 33 are converted into 10 bits, and constitute three independent channels of channel 2, channel 1, and channel 0, respectively. That is, R, G, and B pixel data are transmitted through independent channels 0 to 2, and are transmitted in 10 bits to form one pixel. In the video blanking period, in addition to horizontal synchronization (HSYNC) and vertical synchronization (VSYNC), data other than pixel data can be transmitted using CTL0 / CTL1 / CTL2 / CTL3.

FIG. 4 is a diagram for explaining code assignment in the present embodiment. Four codes can be assigned to the video blanking period, and any one of the codes can be determined as the video blanking period. In FIG. 4, as four codes S _{0 to} S ₃ , for (0, 0), (0, 1), (1, 0), (1, 1) of (bit1, bit0), respectively A 10-bit CTRL code is assigned. Using these four codes, it is possible to transmit a total of 6 bits of information for 2 bits per pixel clock per pixel clock. Of these, CTL0 to CTL3 excluding horizontal synchronization (HSYNC) and vertical synchronization (VSYNC) These 4 bits can be used for transmission of superimposed data. In this embodiment, when superimposing data is sent using a blanking period, the same superimposing data is repeatedly sent to, for example, three out of four of CTL0 to CTL3. 1 bit of superimposition data is sent as 3 bits of CTL0 to CTL2. At this time, continuous data can be sent using the buffer 34 shown in FIG. Further, the repetitive data may be transmitted while being shifted by a fixed clock for each channel. In this way, it is possible to reduce errors in additional data reception by repeatedly sending the same superimposed data.

  FIG. 5 is a diagram for explaining the configuration of the receiving unit 50 shown in FIG. The receiving unit 50 to which the present embodiment is applied is assigned to decoders 51, 52, and 53 that demodulate 10-bit serial data output from the transmitting unit 30 into RGB pixel data each having 8 bits, and are assigned to blanking periods. The blanking signal generator 54 outputs a blanking period (blanking signal) when the four codes are input, and the result obtained by demodulating the four codes by each channel is input and finally Is provided with a majority processing unit 55 for determining superimposition data, for example, a buffer 56 for restoring and outputting the transmission timing of audio data. Also, a PLL 57 that generates a serial 10-bit clock from the transmitted clock and converts it into a stable parallel 8-bit pixel clock, and a timing for outputting superimposed data based on the pixel clock from the PLL 57. A timing generation unit 58 for generation is provided. Furthermore, an EDID (Extended Display Identification Data) 59 for transmitting the capability on the monitor 20 side to the host digital tuner 10 side is provided. Based on the blanking signal output from the blanking signal generation unit 54, control is performed so that RGB pixel data is not actually output during the blanking period, and superimposed data is output based on the blanking signal. The

FIG. 6 is a timing chart for explaining the determination by the receiving unit 50 for the 10-bit string data to be sent. Here, pixel data and superimposition data are received in order corresponding to the pixel clock. The blanking signal generator 54 extracts a bit string indicating a blanking period from 10-bit data transmitted corresponding to the pixel clock, and outputs a data enable signal (DE) as Low. A correct blanking signal is generated from these three channels. Also, based on the transmitted 10-bit data, the decoders 51 to 53 generate 2 bits S _{0 to} S ₃ , the decoder 53 outputs them as HSYNC and VSYNC, 1 bit of the decoder 51 and 2 bits of the decoder 52 The bit is output to the majority processing unit 55. The remaining 1 bit is output as CTL3.

In FIG. 6, 10-bit data is transmitted in the order of codes S ₀ → S ₁ → S ₃ → S ₁ shown in FIG. 4, and 0 → 1 → 1 → 1 is obtained in bit 0 based on the 10-bit data. , Bit1 is 0 → 0 → 1 → 0. For example, audio data which is superimposition data can be obtained by this bit string. In channel 1, since CTL0 / CTL1 is assigned, for example, bit0 is treated as CTL0 and bit1 is treated as CTL1. In channel 2, since CTL2 / CTL3 is assigned, for example, bit0 is treated as CTL2 and bit1 is treated as CTL3. In this embodiment, for example, the same data is sent to three of CTL0 to CTL3 to reduce the error rate. Therefore, for example, to send the same data to CTL 0 / CTL1 is 10-bit CTRL code based on the code _{S 0} and _{S 3} is to be sent over the channel 1 from the transmitting side.

FIGS. 7A to 7D are diagrams for explaining a first majority processing method implemented by the majority processing unit 55. In FIGS. 7A, 7C, and 7D, “Erase” indicates a portion that is not a blanking signal, and this portion can be interpreted as having no data. That is, the decoder of each channel outputs “Erase” when it does not match the bit string of Ri and the blanking signal. In the majority processing 61, the number of 3-bit “1” s obtained from the outputs R ₁ and R _{2 of} the decoders 52 and 53 and the number of “0” are compared, and the larger one is used as the bit output. At this time, the symbol “Erase” is not included in the number. For example, as an example of 3-bit repetition, it is assumed that repetition as shown in FIG. 7B is obtained. At this time, the number of “0” is 2, the number of “1” is 1, and the number of “0” is large. Therefore, “0” is obtained as the output Sout of the majority processing 61. Further, as an example of the case where “Erase” exists, it is assumed that repetition as shown in FIG. 7C is obtained. At this time, except for the “Erase” symbol of R ₁ , the number of “0” is 0 and the number of “1” is 1. As a result, since the number of “1” is large, “1” is obtained as the output Sout of the majority processing 61.

Next, as another example of the case where “Erase” exists, it is assumed that the repetition as shown in FIG. 7D is obtained. At this time, except for the “Erase” symbol of R ₂ , “0” and “1” may be the same number. Since it is clear that the transmission data that is a series of “0” or “1” is garbled in the middle, the code assignment shown in FIG. 4 is softly determined from the code with the smaller Hamming distance and output. . Hamming distance S ₀ and the Hamming distance _{S 2, S 1} and _{S 3} are both 1 and smaller, because the Hamming distance than it is as large as 9 or 10, _{S 0} in the case of _{S 2,} i.e., the majority processing "0" is obtained as the output Sout of 61, _{S 3} in the case of _{S 1,} i.e., "1" is obtained as the output Sout of the majority processing 61. When all are “Erase”, the output Sout may be “1” or “0”.

FIG. 8 is a diagram for explaining a second majority processing method implemented by the majority processing unit 55. Here, in addition to the majority process 61 described with reference to FIGS. 7A to 7C, a feature is that a Hamming majority process 62 that takes a majority vote after selecting a hamming distance is selected. That is, in the case of “Erase”, the decoders 52 and 53 simultaneously output a symbol R′i having the minimum hamming distance between the received bit string and the bit string assigned to each symbol. Decisions based on are taken into account. Here, the “Hamming distance” indicates the number of bits extracted from the received bit string that is different from the original bit string. The smaller the number, the higher the matching degree, and the larger the number, the lower the matching degree. . In each of the decoders 52 and 53, the four CTL codes corresponding to the codes S _{0 to} S ₃ are compared with the input bit string, and the codes R ′ ₁ and R ′ ₂ having a short Hamming distance are output. In the Hamming majority process 62, the number of “1” and the number of “0” of the corresponding bits of R ′ ₁ and R ′ ₂ output from the decoders 52 and 53 are output.

  That is, in the second majority processing method shown in FIG. 8, unless all are “Erase” and the number of “1” and “0” is the same number, they are shown in FIGS. The same value as in the first majority processing method is output, and the result of the majority processing 61 is obtained as Sout. When all of them are “Erase” (when there is actually no data) and when the numbers of “1” and “0” are the same, the output from the Hamming majority process 62 is obtained using the code R′i. Sout can be used to assist when neither of them can determine data, that is, when there is no more data.

  FIGS. 9A and 9B are diagrams for explaining a third majority processing method executed by the majority processing unit 55. In this third majority processing method, the second majority processing method shown in FIG. 8 is multiplied by the weighting calculated from the error probability to the Hamming distance output from each decoder 52, 53. is doing. As shown in FIG. 9A, the decoders 52 and 53 provide a symbol R′i having the minimum hamming distance from the bit string assigned to each symbol and a hamming distance di for all bit strings. Is output. In the majority process 63, information as shown in FIG. 9B is held. That is, a coefficient Wjd determined based on the Hamming distance d and the probability that each bit j of the selected symbol is an error is predetermined and prepared. This coefficient Wjd is normally set to be the maximum when the hamming distance is 0 and to become smaller as the hamming distance becomes larger.

  In the majority processing 63, the coefficient Wjdi determined by the obtained Hamming distance di is set to a positive number Wjdi when the bit of each symbol is “1”, and is negative when the bit is “0”. The sum is calculated for all received bits as the number -Wjdi. From the majority process 63, “1” is output when the calculation result is a positive number, and “0” is output when the calculation result is negative.

FIGS. 10A to 10D are diagrams for explaining a specific example of calculation by the third majority processing method shown in FIGS. 9A and 9B. Here, it is assumed that a value as shown in FIG. 10A is obtained as the symbol R′i input to the majority process 63 and a value as shown in FIG. 10B is obtained as the Hamming distance di. . Further, it is assumed that the value shown in FIG. 10C is determined as the weighting coefficient Wjd. A specific calculation is shown in FIG. First, as shown in FIG. 10B, since the Hamming distance of “d ₁ ” is “4”, the coefficient Wjd obtained from FIG. 10C is “2” for bit 0 and “1” for bit 1. " In the symbol R ′ ₁ shown in FIG. 10A, since bit 0 is “0” and bit 1 is “0”, “2” and “1” are negative numbers, and “−2”, “ -1 "is obtained. Similarly, “+32” is obtained from the symbol R ′ ₂ and the Hamming distance d ₂ . At this time, bit 1 is excluded because it is not used repeatedly. These sums are “29”, which is larger than “0”, and the output Sout from the majority process 63 can obtain “1”. As described above, in the third majority processing method, the error rate can be greatly improved as compared with the simple majority by making a determination based on the weighting based on the probability of occurrence of a close one. .

  FIG. 11 is a diagram showing a relationship between a transmission line error and a data error in a symbol that is actually received. In the figure, the horizontal axis indicates the error value of the transmission line, and the vertical axis indicates the error value of the data included in the received output. In FIG. 11, CTL0 and CTL1 are cases where the respective CTLs are transmitted as they are, and circles 1 to 3 shown in the figure indicate the results of using the majority process in the present embodiment. Circle 1 indicates the first majority processing method described above, circle 2 indicates the second majority processing method, circle 3 indicates the third majority processing method, and the weights are values as shown in the upper right diagram. Here, weighting is determined for three of CTL0, CTL1, and CTL2 to which the same superimposed data is sent. Thus, it can be understood that the error of the output data can be improved by sending the same superimposed data a plurality of times as indicated by circles 1 to 3 as compared to the case where the superimposed data is sent alone. Also, compared with “Maru 1, first majority processing method” which simply takes a majority decision, the decision is made with the smallest symbol of the distance when the decision cannot be made by majority because of “Erase”. The majority vote processing method "makes it possible to significantly reduce the error rate. Furthermore, the error rate improvement effect can be further enhanced by adopting the “circle 3, third majority processing method” that is determined flexibly by weighting the distance.

8 ... Antenna, 9 ... Line, 10 ... Digital tuner, 11 ... Front end, 12 ... AV (Audio Visual) decoder, 20 ... Monitor, 21 ... D / A converter, 22 ... Amplifier (RGB AMP), 23 ... Horizontal Vertical synchronization signal (H / V SYNC), 24 ... CRT, 25 ... D / A converter, 26 ... speaker, 30 ... transmitter, 31,32,33 ... encoder, 34 ... buffer, 35 ... timing generator, 36 ... PLL (Phase-Locked Loop), 37 ... DDC (Display Data Channel), 50 ... Receiver, 51,52,53 ... Decoder, 54 ... Blanking signal generator, 55 ... Major decision processor, 56 ... Buffer, 57 ... PLL, 58 ... timing generator, 59 ... EDID (Extended Display Identification Data), 61 ... majority processing, 62 ... Humming majority processing, 63 ... majority processing

Claims (4)

Video data is transmitted using the first, second and third channels in the DVI format, and data representing a synchronization signal is arranged and transmitted during the blanking period of the video data of the first channel. In the blanking period of the video data of the second channel and the third channel, a plurality of codes having a predetermined number of types are arranged and transmitted, respectively. In a data receiving device for receiving channel data,
Audio is obtained by demodulating the code from the same data related to the audio signal corresponding to the code transmitted so as to be included in the blanking period at least three times by the second channel and the third channel. A data receiving apparatus comprising means for acquiring data. A buffer for storing and outputting the audio data;
The data receiving apparatus according to claim 1, further comprising timing generation means for generating timing for outputting the audio data from the buffer.   The data receiving apparatus according to claim 2, further comprising a PLL circuit that converts the transmitted clock into a pixel clock and supplies the converted pixel clock to the timing generation unit. Video data is transmitted using the first, second and third channels in the DVI format, and data representing a synchronization signal is arranged and transmitted during the blanking period of the video data of the first channel. In the blanking period of the video data of the second channel and the third channel, a plurality of codes having a predetermined number of types are arranged and transmitted, respectively. In a data receiving method for receiving channel data,
Audio is obtained by demodulating the code from the same data related to the audio signal corresponding to the code transmitted so as to be included in the blanking period at least three times by the second channel and the third channel. A data receiving method comprising the step of acquiring data.

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