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JP4828997B2 - SEMICONDUCTOR PACKAGE AND ITS MOUNTING METHOD, AND INSULATED WIRING BOARD USED FOR THE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD - Google Patents

SEMICONDUCTOR PACKAGE AND ITS MOUNTING METHOD, AND INSULATED WIRING BOARD USED FOR THE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD Download PDF

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JP4828997B2
JP4828997B2 JP2006119241A JP2006119241A JP4828997B2 JP 4828997 B2 JP4828997 B2 JP 4828997B2 JP 2006119241 A JP2006119241 A JP 2006119241A JP 2006119241 A JP2006119241 A JP 2006119241A JP 4828997 B2 JP4828997 B2 JP 4828997B2
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wiring board
semiconductor package
back surface
conductive film
insulating
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JP2007294584A (en
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節哉 奥
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Description

本発明は、半導体パッケージおよびその実装方法、ならびにその半導体パッケージに使用する絶縁配線基板およびその製造方法に関する。   The present invention relates to a semiconductor package and a mounting method thereof, and an insulated wiring board used for the semiconductor package and a manufacturing method thereof.

近年、ＩＣ(Integrated Circuit）の大規模集積化に伴い、半導体パッケージと外部基板との接続端子数も増加し、ＱＦＰ(Quad Flat Package)やＱＦＮ(Quad Flat Non-Leaded Package)では対応しきれなくなり、多ピン・ファインピッチ(0.5mm以下）のＢＧＡ(Ball Grid Array)やＬＧＡ(Land Grid Array)が採用されて来ている。   In recent years, with the large-scale integration of ICs (Integrated Circuits), the number of connection terminals between semiconductor packages and external boards has increased, and QFP (Quad Flat Package) and QFN (Quad Flat Non-Leaded Packages) cannot be supported. BGA (Ball Grid Array) and LGA (Land Grid Array) with a multi-pin fine pitch (0.5 mm or less) have been adopted.

従来の半導体パッケージの一例としてのＣＳＰ(Chip Size Package)を図８に示す。図８（ａ）はＣＳＰの概略構成を模式的に示す断面斜視図であり、図８（ｂ）は縦断面図である。   FIG. 8 shows a CSP (Chip Size Package) as an example of a conventional semiconductor package. FIG. 8A is a sectional perspective view schematically showing a schematic configuration of the CSP, and FIG. 8B is a longitudinal sectional view.

図８において、１０１は従来のＣＳＰ、１０２は半導体チップ、１０２ａは表面電極、１０３は絶縁配線基板、１０３ａは表面配線パターン、１０３ｂは内部配線、１０３ｃは外部接続電極、１０４，１０５は接合材としての半田ボール、１０６は封止樹脂である。   In FIG. 8, 101 is a conventional CSP, 102 is a semiconductor chip, 102a is a surface electrode, 103 is an insulated wiring board, 103a is a surface wiring pattern, 103b is an internal wiring, 103c is an external connection electrode, and 104 and 105 are bonding materials. The solder ball 106 is a sealing resin.

ＣＳＰ１０１は、インターポーザと呼ばれる絶縁配線基板１０３の表面側に半導体チップ１０２が搭載されている。   The CSP 101 has a semiconductor chip 102 mounted on the surface side of an insulated wiring substrate 103 called an interposer.

半導体チップ１０２の表面電極１０２ａは、その上に形成された半田ボール１０４により、絶縁配線基板１０３に形成された表面配線パターン１０３ａとフリップチップボンディングされている。   The surface electrode 102 a of the semiconductor chip 102 is flip-chip bonded to the surface wiring pattern 103 a formed on the insulating wiring substrate 103 by solder balls 104 formed thereon.

また、表面配線パターン１０３ａは、絶縁配線基板１０３内部に形成された内部配線１０３ｂを介して、絶縁配線基板１０３裏面に形成された外部接続電極１０３ｃと電気接続されている。   The front surface wiring pattern 103 a is electrically connected to an external connection electrode 103 c formed on the back surface of the insulating wiring substrate 103 via an internal wiring 103 b formed inside the insulating wiring substrate 103.

また、各外部接続電極１０３ｃ上には半田ボール１０５が形成されている。   A solder ball 105 is formed on each external connection electrode 103c.

そして、半導体チップ１０２の部分は、封止樹脂１０６により被覆されている。   The portion of the semiconductor chip 102 is covered with a sealing resin 106.

このように、絶縁配線基板１０３を介して、半導体チップ１０２の表面電極１０２ａは、そのピッチよりも大きなピッチの外部基板（図示せず）と電気接続できるようになっている。（例えば、特許文献１参照）。   As described above, the surface electrode 102a of the semiconductor chip 102 can be electrically connected to an external substrate (not shown) having a pitch larger than the pitch through the insulating wiring substrate 103. (For example, refer to Patent Document 1).

尚、上記では、半導体チップ１０２をフリップチップボンディングする構成で説明したが、絶縁配線基板１０３に対する半導体チップ１０２の搭載形態は、これに限らず、半導体チップ１０２を表裏反転させずに搭載して、ボンディングワイヤ（図示せず）を用いて電気接続する構成であってもよい。   In the above description, the configuration in which the semiconductor chip 102 is flip-chip bonded has been described. However, the mounting form of the semiconductor chip 102 on the insulating wiring substrate 103 is not limited to this, and the semiconductor chip 102 is mounted without being turned upside down. It may be configured to be electrically connected using a bonding wire (not shown).

また、上記では、半導体チップ１０２の部分を封止樹脂１０６で被覆する構成で説明したが、樹脂封止せずに半導体チップ１０２と絶縁配線基板１０３との間にアンダーフィル（図示せず）と呼ばれる接着剤を充填させるだけの構成であってもよい。
特開２００１−９４００４号公報 図２０ 特開２００１−９４００４号公報 図４ In the above description, the semiconductor chip 102 is covered with the sealing resin 106. However, it is called underfill (not shown) between the semiconductor chip 102 and the insulating wiring board 103 without resin sealing. The structure which only fills an adhesive agent may be sufficient.
Japanese Patent Laid-Open No. 2001-94004 Japanese Patent Laid-Open No. 2001-94004

しかしながら、上記のようなＣＳＰ１０１においては、以下のような問題があった。   However, the CSP 101 as described above has the following problems.

接合材としての半田ボール１０５と外部接続電極１０３ｃとの接合形態が、単に、半田ボール１０５を平面電極である外部接続電極１０３ｃに突合わせた平面接合である上、接合面積が外部接続電極１０３ｃの平面積に限定されるため接合強度が弱いという問題があった。   The bonding form of the solder ball 105 as the bonding material and the external connection electrode 103c is simply planar bonding in which the solder ball 105 is abutted against the external connection electrode 103c which is a flat electrode, and the bonding area of the external connection electrode 103c is There is a problem that the bonding strength is weak because it is limited to a flat area.

とくに近年、このようなＣＳＰ１０１は、携帯通信機（モバイル）への利用が盛んであり、落下などの衝撃に耐え得る接合強度が要求されている。   In particular, in recent years, such a CSP 101 is actively used for a mobile communication device (mobile), and a bonding strength that can withstand an impact such as a drop is required.

また、接合材としての半田ボール１０５が絶縁配線基板１０３裏面から突出する格好となるため、半田ボール１０５を溶融させた際に、その溶融状況によっては、高さのバラツキが生じ、外部基板（図示せず）に対するＣＳＰ１０１の水平度が悪化するという問題があった。   Further, since the solder balls 105 as the bonding material are projected from the back surface of the insulated wiring substrate 103, when the solder balls 105 are melted, the height varies depending on the melting state, and the external substrate (FIG. There is a problem that the level of the CSP 101 deteriorates with respect to (not shown).

尚、特許文献２には、従来の他の例として、図９のような構成が開示されている。図９は縦断面図である。   Note that Patent Document 2 discloses a configuration as shown in FIG. 9 as another conventional example. FIG. 9 is a longitudinal sectional view.

図９において、２００は従来の他の例のＣＳＰ、２０１は半導体チップ、２０２は接続電極、２０３は半田ボール、２０４は貫通孔、２０５は封止樹脂、２０６は絶縁配線基板、２０７は配線、２０８は金バンプ、２０９はバンプ電極、２１０はアンダーフィルである。   9, 200 is another conventional CSP, 201 is a semiconductor chip, 202 is a connection electrode, 203 is a solder ball, 204 is a through hole, 205 is a sealing resin, 206 is an insulating wiring board, 207 is a wiring, 208 is a gold bump, 209 is a bump electrode, and 210 is an underfill.

この構成では、絶縁配線基板２０６の裏面側から表面配線パターン２０７に達する貫通凹部２０４が設けられ、その貫通凹部２０４の内部に表面配線パターン２０７の裏面と接合した半田ボール２０３の一部が形成されている。   In this configuration, a through recess 204 that reaches the surface wiring pattern 207 from the back surface side of the insulated wiring board 206 is provided, and a part of the solder ball 203 bonded to the back surface of the surface wiring pattern 207 is formed inside the through recess 204. ing.

しかしながら、このような構成であっても、絶縁配線基板２０６と半田ボール２０３との接合形態および接合面積の点では、平面接合であることに代わりなく、十分な接合強度が得られるとは言えなかった。   However, even with such a configuration, in terms of the bonding form and bonding area between the insulated wiring board 206 and the solder balls 203, it cannot be said that sufficient bonding strength is obtained instead of flat bonding. It was.

また、半田ボール２０３の一部が貫通凹部２０４から突出しているため、半田を溶融させた際に、外部基板（図示せず）に対するＣＳＰ２００の水平度が悪化するおそれがあった。   Further, since a part of the solder ball 203 protrudes from the through recess 204, the level of the CSP 200 with respect to the external substrate (not shown) may be deteriorated when the solder is melted.

本発明の主な課題は、絶縁配線基板と接合材との接合強度を増大させることで、その結果として半導体パッケージと外部基板との接合強度を増大させ、かつ、外部基板に対する半導体パッケージの水平度を悪化させることのない半導体パッケージおよびその実装方法ならびにその半導体パッケージに使用する絶縁配線基板およびその製造方法をを提供することである。   The main object of the present invention is to increase the bonding strength between the insulated wiring board and the bonding material, thereby increasing the bonding strength between the semiconductor package and the external substrate, and the level of the semiconductor package with respect to the external substrate. The present invention provides a semiconductor package and a mounting method thereof, and an insulated wiring board used for the semiconductor package and a manufacturing method thereof.

本発明の半導体パッケージは、
表面側に表面配線パターン、裏面側に表面配線パターンと内部配線で電気接続された外部接続電極が形成された絶縁配線基板と、
絶縁配線基板の表面側に搭載され、表面配線パターンと電気接続された半導体チップとを備えた半導体パッケージにおいて、
外部接続電極は、絶縁配線基板の裏面に設けられた有底凹部の底面および側面に形成された導電膜でなることを特徴とする半導体パッケージである。 The semiconductor package of the present invention is
An insulating wiring board on which an external connection electrode electrically connected by a front surface wiring pattern on the front surface side and a front surface wiring pattern and internal wiring is formed on the back surface side;
In a semiconductor package equipped with a semiconductor chip mounted on the surface side of an insulated wiring board and electrically connected to the surface wiring pattern,
The external connection electrode is a semiconductor package comprising a conductive film formed on the bottom and side surfaces of a bottomed recess provided on the back surface of the insulated wiring board.

本発明の半導体パッケージの実装方法は、
表面側に表面配線パターンが形成され、裏面側に表面配線パターンと内部配線で電気接続された外部接続電極が形成された絶縁配線基板と、
絶縁配線基板の表面側に搭載され、表面配線パターンと電気接続された半導体チップとを備えた半導体パッケージにおいて、
外部接続電極は、絶縁配線基板の裏面に設けられた有底凹部の底面および側面に形成された導電膜でなる半導体パッケージの実装方法であって、有底凹部に導電性ペーストを充填した後、絶縁配線基板の裏面を外部基板に隙間なく当接させて、導電性ペーストで接合する半導体パッケージの実装方法である。 The mounting method of the semiconductor package of the present invention is as follows:
An insulating wiring board in which a front surface wiring pattern is formed on the front surface side and an external connection electrode electrically connected by a front surface wiring pattern and internal wiring is formed on the back surface side;
In a semiconductor package equipped with a semiconductor chip mounted on the surface side of an insulated wiring board and electrically connected to the surface wiring pattern,
The external connection electrode is a semiconductor package mounting method comprising a conductive film formed on the bottom and side surfaces of the bottomed recess provided on the back surface of the insulated wiring board, and after filling the bottomed recess with a conductive paste, This is a semiconductor package mounting method in which the back surface of an insulated wiring substrate is brought into contact with an external substrate without any gap and bonded with a conductive paste.

本発明の半導体パッケージに使用する絶縁配線基板は、
表面側に表面配線パターン、裏面側に表面配線パターンと内部配線で電気接続された外部接続電極が形成された絶縁配線基板であって、
外部接続電極は、その裏面に設けられた有底凹部の底面および側面に形成された導電膜でなることを特徴とする絶縁配線基板である。 The insulated wiring board used for the semiconductor package of the present invention is
An insulating wiring board on which a front surface wiring pattern is formed on the front surface side and an external connection electrode electrically connected to the front surface wiring pattern and the internal wiring is formed on the back surface side,
The external connection electrode is an insulated wiring board characterized by comprising a conductive film formed on the bottom and side surfaces of a bottomed recess provided on the back surface thereof.

本発明の半導体パッケージに使用する絶縁配線基板の製造方法は、
表面側に所定の表面配線パターンと、それと電気接続され、裏面の所定位置に露出する内部配線とが形成された絶縁性基板を準備し、その裏面に、外部接続電極を形成する予定領域を開口部とする樹脂パターンを形成するステップと、
絶縁性基板の裏面全面に導電膜を形成するステップと、
樹脂パターンの開口部の底部および内側面をレジストで埋め込んだレジストマスクを形成するステップと、
レジストマスクをエッチングマスクとして導電膜をエッチングするステップと、
レジストマスクを除去するステップとを、備えたことを特徴とした絶縁配線基板の製造方法である。 The manufacturing method of the insulated wiring board used for the semiconductor package of the present invention is:
Prepare an insulating substrate that has a predetermined surface wiring pattern on the front side and internal wiring that is electrically connected to it and exposed at a predetermined position on the back side. Forming a resin pattern as a part;
Forming a conductive film on the entire back surface of the insulating substrate;
Forming a resist mask in which the bottom and inner surface of the opening of the resin pattern are embedded with a resist;
Etching the conductive film using the resist mask as an etching mask;
And a step of removing the resist mask. A method of manufacturing an insulated wiring board, comprising:

本発明の半導体パッケージおよびその実装方法、ならびにその半導体パッケージに使用する絶縁配線基板およびその製造方法によると、半導体パッケージと外部基板との接合強度を増大させることができるとともに、外部基板に対する半導体パッケージの水平度を悪化させるおそれがない。   According to the semiconductor package and the mounting method of the present invention, and the insulated wiring board used for the semiconductor package and the manufacturing method thereof, the bonding strength between the semiconductor package and the external substrate can be increased, and the semiconductor package with respect to the external substrate can be increased. There is no risk of worsening the level.

本発明は、半導体パッケージと外部基板との接合強度を増大させるとともに、外部基板に対する半導体パッケージの水平度を悪化させるおそれがない半導体パッケージおよびその実装方法、ならびにその半導体パッケージに使用する絶縁配線基板およびその製造方法を提供するという目的を、外部接続電極を、絶縁配線基板の裏面に設けた有底凹部の底面および側面に形成した導電膜とすることで実現した。   The present invention increases a bonding strength between a semiconductor package and an external substrate, and does not deteriorate the level of the semiconductor package with respect to the external substrate, a mounting method thereof, an insulated wiring substrate used for the semiconductor package, and The object of providing the manufacturing method is realized by using the external connection electrodes as conductive films formed on the bottom and side surfaces of the bottomed recess provided on the back surface of the insulated wiring board.

本発明の半導体パッケージの実施例１に係るＣＳＰ(Chip Size Package)を図１に示す。図１（ａ）はＣＳＰの概略構成を模式的に示す縦断面図であり、図１（ｂ）は部分平面図（裏面側）である。また、図８と同一部分には同一符号を付す。   FIG. 1 shows a CSP (Chip Size Package) according to a first embodiment of the semiconductor package of the present invention. FIG. 1A is a longitudinal sectional view schematically showing a schematic configuration of the CSP, and FIG. 1B is a partial plan view (back side). The same parts as those in FIG.

図１において、１０は本発明のＣＳＰ、１１は外部接続電極、１２は有底凹部、１３は導電膜である。   In FIG. 1, 10 is a CSP of the present invention, 11 is an external connection electrode, 12 is a bottomed recess, and 13 is a conductive film.

ＣＳＰ１０は、インターポーザと呼ばれる絶縁配線基板１０３の表面側に半導体チップ１０２が搭載されている。   The CSP 10 has a semiconductor chip 102 mounted on the surface side of an insulated wiring substrate 103 called an interposer.

半導体チップ１０２の表面電極１０２ａは、その上に形成された半田ボール１０４により、絶縁配線基板１０３に形成された表面配線パターン１０３ａとフリップチップボンディングされている。   The surface electrode 102 a of the semiconductor chip 102 is flip-chip bonded to the surface wiring pattern 103 a formed on the insulating wiring substrate 103 by solder balls 104 formed thereon.

また、表面配線パターン１０３ａは、絶縁配線基板１０３内部に形成された内部配線１０３ｂを介して、絶縁配線基板１０３裏面に形成された外部接続電極１１と電気接続されている。   Further, the front surface wiring pattern 103 a is electrically connected to the external connection electrode 11 formed on the back surface of the insulating wiring substrate 103 via the internal wiring 103 b formed inside the insulating wiring substrate 103.

そして、半導体チップ１０２の部分は、封止樹脂１０６により被覆されている。   The portion of the semiconductor chip 102 is covered with a sealing resin 106.

ここで、絶縁配線基板１０３の内部配線１０３ｂと対応する裏面位置には、有底凹部１２が設けられている。   Here, a bottomed recess 12 is provided at a back surface position corresponding to the internal wiring 103 b of the insulating wiring substrate 103.

そして、この有底凹部１２の底面および内側面には、例えば、銅膜とその上に積層された錫膜とでなる導電膜１３が形成され、内部配線１０３ｂと電気接続されて外部接続電極１１を形成している。   A conductive film 13 made of, for example, a copper film and a tin film laminated thereon is formed on the bottom surface and the inner side surface of the bottomed recess 12, and is electrically connected to the internal wiring 103 b to be connected to the external connection electrode 11. Is forming.

このような外部接続電極１１は、有底凹部１２の底面に加えて内側面も導電性ペーストなどの接合材（拡大図中、斜め破線領域で示す）との接合面となり得るため、外部接続電極１１と接合材とは立体的に接合され、かつ、内側面の面積分だけ接合面積が増加するため接合が確実となり接合強度が向上する。   In such an external connection electrode 11, in addition to the bottom surface of the bottomed recess 12, the inner side surface can also be a bonding surface with a bonding material such as a conductive paste (indicated by an oblique broken line region in the enlarged view). 11 and the bonding material are three-dimensionally bonded, and the bonding area increases by the area of the inner surface, so that the bonding is ensured and the bonding strength is improved.

また、接合材を有底凹部１２に収容できるため絶縁配線基板１０３裏面から突出せず、外部基板（図示せず）と絶縁配線基板１０３の裏面とを隙間なく当接させた状態で接合でき、接合材を溶融させた際に、外部基板（図示せず）に対するＣＳＰ１０の水平度を悪化させる心配がない。   In addition, since the bonding material can be accommodated in the bottomed recess 12, it does not protrude from the back surface of the insulated wiring substrate 103 and can be bonded in a state where the external substrate (not shown) and the back surface of the insulated wiring substrate 103 are in contact with each other without gaps When the bonding material is melted, there is no fear of deteriorating the level of the CSP 10 with respect to the external substrate (not shown).

このように、絶縁配線基板１０３を介して、半導体チップ１０２の表面電極１０２ａは、そのピッチよりも大きなピッチの外部基板（図示せず）と電気接続できるようになっている。   As described above, the surface electrode 102a of the semiconductor chip 102 can be electrically connected to an external substrate (not shown) having a pitch larger than the pitch through the insulating wiring substrate 103.

尚、上記では、外部接続電極１１を有底凹部１２の底面および内側面に形成した導電膜１３で成る構成で説明したが、実施例１の変形例として、図２に示すように、外部接続電極１１をなす導電膜１３を、さらに、有底凹部１２の開口部周辺１２ａまで延在させる構成とし、さらに、接合面積の増加を図ってもよい。   In the above description, the external connection electrode 11 has been described with the configuration of the conductive film 13 formed on the bottom surface and the inner side surface of the bottomed recess 12. However, as a modification of the first embodiment, as shown in FIG. The conductive film 13 that forms the electrode 11 may be further extended to the periphery 12a of the opening of the bottomed recess 12 to further increase the bonding area.

また、上記では、半導体チップ１０２をフリップチップボンディングする構成で説明したが、絶縁配線基板１０３に対する半導体チップ１０２の搭載形態は、これに限らず、半導体チップ１０２を表裏反転させずに搭載して、ボンディングワイヤ（図示せず）を用いて電気接続する構成であってもよい。   In the above description, the configuration in which the semiconductor chip 102 is flip-chip bonded has been described. However, the mounting form of the semiconductor chip 102 on the insulating wiring substrate 103 is not limited to this, and the semiconductor chip 102 is mounted without being turned upside down. It may be configured to be electrically connected using a bonding wire (not shown).

また、上記では、半導体チップ１０２の部分を封止樹脂１０６で被覆する構成で説明したが、樹脂封止せずに半導体チップ１０２と絶縁配線基板１０３との間にアンダーフィル（図示せず）と呼ばれる接着剤を充填させるだけの構成であってもよい。   In the above description, the semiconductor chip 102 is covered with the sealing resin 106. However, it is called underfill (not shown) between the semiconductor chip 102 and the insulating wiring board 103 without resin sealing. The structure which only fills an adhesive agent may be sufficient.

次に、本発明の半導体パッケージの実施例２に係るＣＳＰ(Chip Size Package)を図３に示す。図３（ａ）はＣＳＰの概略構成を模式的に示す縦断面図であり、図３（ｂ）は部分平面図（裏面側）である。また、図１，図２，図８と同一部分には同一符号を付す。   Next, a CSP (Chip Size Package) according to Example 2 of the semiconductor package of the present invention is shown in FIG. FIG. 3A is a longitudinal sectional view schematically showing a schematic configuration of the CSP, and FIG. 3B is a partial plan view (back side). The same parts as those in FIGS. 1, 2 and 8 are denoted by the same reference numerals.

図３において、２０は本発明の実施例２に係るＣＳＰ、２１は通気溝である。   In FIG. 3, 20 is a CSP according to Embodiment 2 of the present invention, and 21 is a ventilation groove.

実施例２の構成は、実施例１の構成に加えて、絶縁配線基板１０３の裏面に、有底凹部１２の各々と絶縁配線基板１０３の側面とを通気可能に連通する通気溝２１を設けた構成となっている。   In the configuration of the second embodiment, in addition to the configuration of the first embodiment, the back surface of the insulated wiring board 103 is provided with a ventilation groove 21 that allows each of the bottomed recesses 12 and the side surface of the insulated wiring board 103 to communicate with each other. It has a configuration.

このような通気溝２１を設けておくと、外部基板（図示せず）との接合のための加熱で発生するエアやフラックスガスなどのガスを外部に放出、あるいは、通気溝２１内部に収容できて好適である。   If such a ventilation groove 21 is provided, a gas such as air or a flux gas generated by heating for bonding to an external substrate (not shown) can be discharged to the outside or accommodated in the ventilation groove 21. It is preferable.

次に、本発明の半導体パッケージの実施例３に係るＣＳＰ(Chip Size Package)を図４に示す。図４（ａ）はＣＳＰの概略構成を模式的に示す縦断面図であり、図４（ｂ）は部分平面図（裏面側）である。また、図１〜３，図８と同一部分には同一符号を付す。   Next, a CSP (Chip Size Package) according to Example 3 of the semiconductor package of the present invention is shown in FIG. 4A is a longitudinal sectional view schematically showing a schematic configuration of the CSP, and FIG. 4B is a partial plan view (back side). The same parts as those in FIGS.

図４において、３０は本発明の実施例３に係るＣＳＰ、３１は柱状突起、３１ａは導電膜、３１ｂは絶縁物である。   In FIG. 4, 30 is a CSP according to Example 3 of the present invention, 31 is a columnar protrusion, 31a is a conductive film, and 31b is an insulator.

実施例３の構成は、実施例２の構成に加えて、有底凹部１２の内部の略中央に、表面を導電膜３１ａで被覆した絶縁物３１ｂでなる柱状突起３１を設けた構成となっている。   In the configuration of the third embodiment, in addition to the configuration of the second embodiment, a columnar protrusion 31 made of an insulator 31b whose surface is covered with a conductive film 31a is provided at the approximate center inside the bottomed recess 12. Yes.

このような柱状突起３１を設けておくと、有底凹部１２に収容した導電性ペーストなどの接合材（拡大図中、斜め破線領域で示す）が毛管現象により柱状突起３１に沿って這い上がるため有底凹部１２内面の濡れ性を促進できるとともに、柱状突起３１の側面積分が接合面積として増加するため接合強度の向上が図れる。   If such columnar protrusions 31 are provided, a bonding material such as a conductive paste (shown by an oblique broken line region in the enlarged view) accommodated in the bottomed recess 12 crawls up along the columnar protrusions 31 by capillary action. The wettability of the inner surface of the bottomed recess 12 can be promoted, and the side surface integral of the columnar protrusion 31 is increased as the bonding area, so that the bonding strength can be improved.

次に、上記のようなＣＳＰ１０，２０，３０に使用される絶縁配線基板１０３の製造方法の一例を、図５，図６を参照して説明する。尚、図５，図６は製造フローを示す断面図である。   Next, an example of the manufacturing method of the insulated wiring board 103 used for the CSPs 10, 20, and 30 will be described with reference to FIGS. 5 and 6 are cross-sectional views showing the manufacturing flow.

先ず、図５（ａ）に示すように、表面側に所定の表面配線パターン１０３ａと、それと電気接続され、裏面の所定位置に露出する内部配線１０３ｂとが形成された絶縁性基板１０３−１を準備し、その裏面に、外部接続電極（有底凹部）を形成する予定領域を開口部とする樹脂パターンが形成されるような凹凸パターンを有するモールド金型２に、溶融した絶縁性樹脂３を充填して、絶縁性基板１０３−１の裏面に重ねて硬化させ溶融接着する。   First, as shown in FIG. 5A, an insulating substrate 103-1 having a predetermined surface wiring pattern 103a on the front surface side and an internal wiring 103b electrically connected to the surface and exposed at a predetermined position on the back surface is formed. The molten insulating resin 3 is prepared on a mold die 2 having a concavo-convex pattern in which a resin pattern having an opening in a region where an external connection electrode (bottom recessed portion) is to be formed is formed. It is filled and cured on the back surface of the insulating substrate 103-1, being cured and melt bonded.

これにより、絶縁性基板１０３−１の裏面側には所定厚さ（有底凹部１２の深さ）の樹脂パターンが貼り合わせられた格好となる。   As a result, a resin pattern having a predetermined thickness (depth of the bottomed recess 12) is bonded to the back surface side of the insulating substrate 103-1.

次に、図５（ｂ）に示すように、絶縁性基板１０３−１の裏面全面に導電膜１３、例えば、下地金属としての銅膜の上に形成された錫膜をスパッタ法およびメッキ法を併用して形成する。   Next, as shown in FIG. 5B, a conductive film 13, for example, a tin film formed on a copper film as a base metal, is sputtered and plated on the entire back surface of the insulating substrate 103-1. Formed in combination.

次に、図６（ｃ）に示すように、樹脂パターンの開口部の底部および内側面をレジスト４で埋め込んだレジストマスクを形成する。   Next, as shown in FIG. 6C, a resist mask is formed in which the bottom and the inner surface of the opening of the resin pattern are filled with a resist 4.

次に、図６（ｄ）に示すように、そのレジストマスクをエッチングマスクとして不要な導電膜１３をエッチング除去した後、レジストマスクを除去する。   Next, as shown in FIG. 6D, after the unnecessary conductive film 13 is removed by etching using the resist mask as an etching mask, the resist mask is removed.

このようにして、有底凹部１２の底面および内側面に、内部配線１０３ｂと電気接続した導電膜１３で成る外部接続電極１１を有する絶縁配線基板１０３が完成する。   In this way, the insulated wiring board 103 having the external connection electrode 11 made of the conductive film 13 electrically connected to the internal wiring 103b on the bottom surface and the inner side surface of the bottomed recess 12 is completed.

尚、通気溝２１や柱状突起３１を形成する場合は、モールド金型２の凹凸パターンを、通気溝２１や柱状突起３１が形成できるような凹凸パターンとしておく。   When forming the ventilation grooves 21 and the columnar protrusions 31, the uneven pattern of the mold 2 is set to be an uneven pattern that allows the ventilation grooves 21 and the columnar protrusions 31 to be formed.

また、上記では、有底凹部１２を形成する方法として、絶縁配線基板１０３裏面に樹脂パターンを溶融接着することで説明したが、絶縁配線基板１０３裏面をフォトリソグラフィ法とエッチング法を用いて加工して有底凹部１２を形成してもよく、特に限定するものではない。   In the above description, the bottomed recess 12 is formed by melting and bonding a resin pattern to the back surface of the insulating wiring substrate 103. However, the back surface of the insulating wiring substrate 103 is processed using a photolithography method and an etching method. The bottomed recess 12 may be formed without any particular limitation.

次に、本発明の半導体パッケージの実装方法の一例として、実施例１に係るＣＳＰ１０の実装方法を図７を参照して説明する。尚、実施例２、実施例３に係るＣＳＰ２０，３０については、実施例１に係るＣＳＰ１０の実装方法と同様であるため説明を省略する。また、図１と同一部分には同一符号を付す。   Next, as an example of the semiconductor package mounting method of the present invention, a mounting method of the CSP 10 according to the first embodiment will be described with reference to FIG. Since the CSPs 20 and 30 according to the second and third embodiments are the same as the mounting method of the CSP 10 according to the first embodiment, the description thereof is omitted. The same parts as those in FIG.

図７において、１０は本発明の実施例１に係るＣＳＰ、４１は外部基板、４１ａは外部基板４１の表面に形成された配線パッド、４２は接合材としての導電性ペーストである。     In FIG. 7, 10 is a CSP according to the first embodiment of the present invention, 41 is an external substrate, 41a is a wiring pad formed on the surface of the external substrate 41, and 42 is a conductive paste as a bonding material.

先ず、図７（ａ）に示すように、ＣＳＰ１０の有底凹部１２の形成面（裏面）を上向きにして、シリンジ（図示せず）あるいはマスク印刷（図示せず）を用いて、有底凹部１２の内部に導電性ペースト４２を充填する。   First, as shown in FIG. 7A, the bottomed concave portion is formed using a syringe (not shown) or mask printing (not shown) with the formation surface (back surface) of the bottomed concave portion 12 of the CSP 10 facing upward. 12 is filled with a conductive paste 42.

その後、図７（ｂ）に示すように、ＣＳＰ１０の有底凹部１２の形成面（裏面）を下向きにして外部基板４１の表面に隙間なく当接させる。そして、導電性ペースト４２が配線パッド４１ａ表面上に自重で流れて馴染んだ後、加熱などして硬化させ接合する。   After that, as shown in FIG. 7B, the formation surface (back surface) of the bottomed recess 12 of the CSP 10 is faced down and brought into contact with the surface of the external substrate 41 without any gap. Then, after the conductive paste 42 flows and adjusts on the surface of the wiring pad 41a by its own weight, it is cured by heating or the like and bonded.

尚、上記では、接合材として、有底凹部１２の内部に導電性ペースト４２を充填し、硬化させて接合することで説明したが、導電性ペースト４２の代わりに、有底凹部１２の内部に、予め、バンプ（図示せず）を形成しておき加熱溶融接合させてもよい。   In the above description, the conductive paste 42 is filled in the inside of the bottomed recess 12 as the bonding material, and is cured and bonded. However, instead of the conductive paste 42, the inside of the bottomed recess 12 is provided. Alternatively, bumps (not shown) may be formed in advance and heat-melt bonded.

このようにすると、ＣＳＰ１０と外部基板４１とを隙間なく当接させた状態で接合させることができるため、外部基板４１に対するＣＳＰ１０の水平度を悪化させる心配がない。   In this way, since the CSP 10 and the external substrate 41 can be joined in a state where they are in contact with each other without any gap, there is no fear that the level of the CSP 10 with respect to the external substrate 41 is deteriorated.

本発明は、半導体パッケージと外部基板との接合強度を増大させ、かつ、外部基板に対する半導体パッケージの水平度を悪化させることのない半導体パッケージおよびその実装方法、ならびにその半導体パッケージに使用する絶縁配線基板およびその製造方法に適用できる。   The present invention relates to a semiconductor package that increases the bonding strength between the semiconductor package and the external substrate and does not deteriorate the level of the semiconductor package with respect to the external substrate, a mounting method thereof, and an insulated wiring substrate used for the semiconductor package. And its manufacturing method.

本発明の半導体パッケージの実施例１に係るＣＳＰの概略構成を模式的に示す縦断面図および部分平面図（裏面側）BRIEF DESCRIPTION OF THE DRAWINGS The longitudinal cross-sectional view and partial top view (back side) which show typically schematic structure of CSP which concerns on Example 1 of the semiconductor package of this invention 本発明の実施例１の変形例の概略構成を模式的に示す縦断面図および部分平面図（裏面側）The longitudinal cross-sectional view which shows schematic structure of the modification of Example 1 of this invention typically, and a partial top view (back side) 本発明の半導体パッケージの実施例２に係るＣＳＰの概略構成を模式的に示す縦断面図および部分平面図（裏面側）The longitudinal cross-sectional view and partial top view (back side) which show typically schematic structure of CSP which concerns on Example 2 of the semiconductor package of this invention 本発明の半導体パッケージの実施例３に係るＣＳＰの概略構成を模式的に示す縦断面図および部分平面図（裏面側）The longitudinal cross-sectional view and partial top view (back side) which show typically schematic structure of CSP which concerns on Example 3 of the semiconductor package of this invention 本発明の半導体パッケージに使用する絶縁配線基板の製造方法の一例を示す断面図Sectional drawing which shows an example of the manufacturing method of the insulated wiring board used for the semiconductor package of this invention 本発明の半導体パッケージに使用する絶縁配線基板の製造方法の一例を示す断面図Sectional drawing which shows an example of the manufacturing method of the insulated wiring board used for the semiconductor package of this invention 本発明の半導体パッケージの実装方法の一例を示す縦断面図The longitudinal cross-sectional view which shows an example of the mounting method of the semiconductor package of this invention 従来の半導体パッケージの一例としてのＣＳＰの概略構成を模式的に示す断面斜視図および縦断面図Sectional perspective view and longitudinal sectional view schematically showing a schematic configuration of a CSP as an example of a conventional semiconductor package 従来の他のＣＳＰの縦断面図Vertical sectional view of another conventional CSP

符号の説明Explanation of symbols

２ モールド金型
３ 絶縁性樹脂
４ レジスト
１０ 本発明の半導体パッケージの実施例１に係るＣＳＰ
１１ 外部接続電極
１２ 有底凹部
１３ 導電膜
１２ａ 開口部周辺
２０ 本発明の半導体パッケージの実施例２に係るＣＳＰ
２１ 通気溝
３０ 本発明の半導体パッケージの実施例３に係るＣＳＰ
３１ 柱状突起
３１ａ 導電膜
３１ｂ 絶縁物
４１ 外部基板
４１ａ 配線パッド
４２ 導電性ペースト
１０１ 従来の半導体パッケージの一例としてのＣＳＰ
１０２，２０１ 半導体チップ
１０２ａ 表面電極
１０３，２０６ 絶縁配線基板
１０３ａ 表面配線パターン
１０３ｂ 内部配線
１０３ｃ 外部接続電極
１０３−１ 絶縁性基板
１０４，１０５，２０３ 半田ボール
１０６，２０５ 封止樹脂
２００ 従来の他の例のＣＳＰ
２０２ 接続電極
２０４ 貫通孔
２０７ 配線
２０８ 金バンプ
２０９ バンプ電極
２１０ アンダーフィル 2 Mold Die 3 Insulating Resin 4 Resist 10 CSP according to Example 1 of Semiconductor Package of the Present Invention
DESCRIPTION OF SYMBOLS 11 External connection electrode 12 Bottomed recessed part 13 Conductive film 12a Around opening part 20 CSP concerning Example 2 of semiconductor package of this invention
21 Ventilation groove 30 CSP according to Example 3 of semiconductor package of the present invention
31 columnar protrusion 31a conductive film 31b insulator 41 external substrate 41a wiring pad 42 conductive paste 101 CSP as an example of a conventional semiconductor package
DESCRIPTION OF SYMBOLS 102,201 Semiconductor chip 102a Surface electrode 103,206 Insulated wiring board 103a Surface wiring pattern 103b Internal wiring 103c External connection electrode 103-1 Insulating board 104,105,203 Solder ball 106,205 Sealing resin 200 Other conventional examples CSP
202 Connection electrode 204 Through hole 207 Wiring 208 Gold bump 209 Bump electrode 210 Underfill

Claims (9)

表面側に表面配線パターン、裏面側に前記表面配線パターンと内部配線で電気接続された外部接続電極が形成された絶縁配線基板と、
前記絶縁配線基板の表面側に搭載され、前記表面配線パターンと電気接続された半導体チップと、を備えた半導体パッケージにおいて、
前記外部接続電極は、前記絶縁配線基板の裏面に設けられた有底凹部の底面および側面に形成された導電膜でなり、
前記有底凹部の内部に、表面を導電膜で被覆した絶縁物でなる柱状突起が設けられたことを特徴とする半導体パッケージ。 An insulating wiring board on which a front surface wiring pattern is formed on the front surface side and an external connection electrode electrically connected to the front surface wiring pattern and the internal wiring is formed on the back surface side;
Wherein mounted on the surface side of the insulating wiring board, a semiconductor package and a semiconductor chip that is electrically connected to the surface wiring pattern,
The external connection electrode is a conductive film formed on the bottom and side surfaces of a bottomed recess provided on the back surface of the insulated wiring board ,
A semiconductor package characterized in that a columnar protrusion made of an insulator whose surface is covered with a conductive film is provided inside the bottomed recess . 前記導電膜を前記有底凹部の開口部周辺まで延在させたことを特徴とする請求項１に記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the conductive film is extended to the periphery of the opening of the bottomed recess. 前記絶縁配線基板の裏面に、前記有底凹部の各々と前記絶縁配線基板の側面とを通気可能に連通する通気溝が形成されたことを特徴とする請求項１または２に記載の半導体パッケージ。   3. The semiconductor package according to claim 1, wherein a ventilation groove is formed on the back surface of the insulated wiring board so as to allow each of the bottomed recesses and the side surface of the insulated wiring board to communicate with each other. 請求項１から３のいずれかに記載の半導体パッケージ、の実装方法であって、前記有底凹部に導電性ペーストを充填した後、前記絶縁配線基板の裏面を外部基板に隙間なく当接させて、前記導電性ペーストで接合する半導体パッケージの実装方法。 The semiconductor package according to any one of claims 1 to 3, a mounting method of the after filling the conductive paste into the bottomed recess, and no gap contact is not a back surface of the insulating wiring board on the external substrate A method for mounting a semiconductor package to be joined with the conductive paste. 請求項１から３のいずれかに記載の半導体パッケージ、の実装方法であって、前記有底凹部の内部にバンプを形成し、前記絶縁配線基板の裏面を外部基板に隙間なく当接させて、前記バンプで溶融接合する半導体パッケージの実装方法。 A method for mounting a semiconductor package according to any one of claims 1 to 3 , wherein bumps are formed inside the bottomed recesses, and the back surface of the insulated wiring board is brought into contact with an external board without any gaps. A semiconductor package mounting method in which the bumps are melt-bonded. 表面側に表面配線パターン、裏面側に前記表面配線パターンと内部配線で電気接続された外部接続電極が形成された絶縁配線基板であって、
前記外部接続電極は、その裏面に設けられた有底凹部の底面および側面に形成された導電膜でなり、
前記有底凹部の内部に、表面を導電膜で被覆した絶縁物でなる柱状突起が設けられたことを特徴とする絶縁配線基板。 A surface wiring pattern on the front surface side, an insulating wiring board on which an external connection electrode electrically connected with the surface wiring pattern and internal wiring is formed on the back surface side,
The external connection electrode is a conductive film formed on the bottom and side surfaces of the bottomed recess provided on the back surface ,
An insulating wiring board, wherein a columnar protrusion made of an insulator whose surface is covered with a conductive film is provided inside the bottomed recess. 前記導電膜を前記有底凹部の開口部周辺まで延在させたことを特徴とする請求項６に記載の絶縁配線基板。 The insulated wiring board according to claim 6 , wherein the conductive film is extended to the periphery of the opening of the bottomed recess. その裏面に、前記有底凹部の各々と前記絶縁配線基板の側面とを通気可能に連通する通気溝が形成されたことを特徴とする請求項６または７に記載の絶縁配線基板。 8. The insulated wiring board according to claim 6 , wherein a ventilation groove is formed on the back surface thereof so as to allow each of the bottomed recesses and the side surface of the insulated wiring board to communicate with each other. 請求項６から８のいずれかに記載の絶縁配線基板、の製造方法であって、
表面側に所定の表面配線パターンと、それと電気接続され、裏面の所定位置に露出する内部配線とが形成された絶縁性基板を準備し、その裏面に、外部接続電極を形成する予定領域を開口部とする樹脂パターンを形成するステップと、
前記絶縁性基板の裏面全面に導電膜を形成するステップと、
前記樹脂パターンの開口部の底部および内側面をレジストで埋め込んだレジストマスクを形成するステップと、
前記レジストマスクをエッチングマスクとして前記導電膜をエッチングするステップと、
前記レジストマスクを除去するステップと、を備えたことを特徴とした絶縁配線基板の製造方法。 A method for manufacturing the insulated wiring board according to claim 6 , comprising:
Prepare an insulating substrate that has a predetermined surface wiring pattern on the front side and internal wiring that is electrically connected to it and exposed at a predetermined position on the back side, and opens an area for forming external connection electrodes on the back side. Forming a resin pattern as a part;
Forming a conductive film on the entire back surface of the insulating substrate;
Forming a resist mask in which a bottom and an inner surface of the opening of the resin pattern are embedded with a resist;
Etching the conductive film using the resist mask as an etching mask;
Manufacturing method of the insulating wiring board characterized by comprising the steps of: removing the resist mask.
JP2006119241A 2006-04-24 2006-04-24 SEMICONDUCTOR PACKAGE AND ITS MOUNTING METHOD, AND INSULATED WIRING BOARD USED FOR THE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD Expired - Fee Related JP4828997B2 (en)

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