JP4826074B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor (FET), and more particularly to a field effect transistor in which a channel region is composed of an organic semiconductor material layer.

  In a thin film transistor (TFT) which is a kind of a conventional field effect transistor (FET), an inorganic semiconductor material such as Si, GaAs, InGaAs or the like is used as a semiconductor layer constituting a channel region. In the manufacturing process of the TFT using the above, a high temperature process of 400 ° C. or higher is required. Therefore, it is extremely difficult to manufacture a TFT using an inorganic semiconductor material on a light support (substrate) that is soft and difficult to break, such as plastics.

  On the other hand, a TFT whose channel region is composed of an organic semiconductor material layer (hereinafter referred to as an organic TFT) can be manufactured at a temperature lower than the heat resistance temperature of plastics. Moreover, since it can be manufactured based on the material which can be apply | coated, it is anticipated as a semiconductor element suitable for low cost and a large area.

  By the way, in the conventional organic TFT, when the conductivity type of the organic semiconductor material layer is p-type, the source / drain electrodes are made of gold (Au), platinum in order to form a good ohmic junction with the organic semiconductor material layer. (Pt), palladium (Pd), or a poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS] or an impurity doped polyaniline, or It is composed of carbon nanotubes. The thickness of the source / drain electrode is typically 50 nm or more.

JP2003-229579 JP 2004-103905 A

  In general, an organic semiconductor material may be oxidized by oxygen in the atmosphere, dissolved oxygen present in water, or impurities in a solvent. When oxidized, the organic semiconductor material is doped with holes. And the increase of the background carrier based on this hole increases off current. This tendency becomes more prominent as the source / drain electrodes are thicker. This state is schematically shown in FIG. That is, when a gate voltage is applied to the gate electrode 112, the channel region 115 is formed in the organic semiconductor material layer 114 between the source / drain electrodes 121 and in the vicinity of the gate insulating layer 113. Note that the current flowing from one source / drain electrode 121 to the other source / drain electrode 121 via the channel region 115 is indicated by an arrow in FIG. When the thickness of the source / drain electrode 121 is large, the off-state of the portion 114A away from the channel region 115 of the organic semiconductor material layer 114 that cannot be controlled by the gate electrode 112 due to the increase of background carriers is turned off. The current (in FIG. 7, the flow is schematically indicated by a dotted line) increases. In FIG. 7, reference numeral 111 denotes a support.

  Organic TFTs having a structure in which a source / drain electrode made of a metal material and an organic semiconductor material layer constituting a channel region are not in direct contact are known from, for example, Japanese Patent Application Laid-Open Nos. 2003-229579 and 2004-103905. It is.

  In the technique disclosed in Japanese Patent Application Laid-Open No. 2003-229579, the source / drain electrode is composed of a metal portion and a metal compound portion in contact with the organic conductive compound layer constituting the channel region. Here, examples of the metal compound include compounds containing a metal atom belonging to Groups 6 to 11 of the periodic table, and among these, iridium, rhodium, ruthenium, platinum, gold, silver, samarium, osmium, palladium, nickel Further, metal compounds such as cobalt and europium are preferable, or salts of these metals are preferable, or they can be selected from complexes of these metals (paragraph of JP2003-229579) Number [0023]).

  In the technique disclosed in Japanese Patent Application Laid-Open No. 2004-103905, oxidation of a metal such as ITO, IZO, tin oxide, or zinc oxide is performed between a source / drain electrode and an organic semiconductor layer constituting a channel region. A buffer layer made of an oxide, a nitride, an oxide, a metal, an alloy, or an organic compound is formed (see paragraph number [0012] of JP-A-2004-103905).

  However, in the organic TFT disclosed in these patent publications, there is no description or suggestion regarding reduction of off-current due to background carriers.

  Accordingly, an object of the present invention is to provide a field effect transistor having a structure that can reduce off-state current due to background carriers.

In order to achieve the above object, a field effect transistor according to the first aspect of the present invention provides:
(A) a gate electrode,
(B) a gate insulating layer;
(C) source / drain electrodes, and
(D) an organic semiconductor material layer located between the source / drain electrodes, facing the gate electrode through the gate insulating layer, and having a channel region induced by application of a gate voltage to the gate electrode in a part thereof;
A field effect transistor comprising:
The source / drain electrodes are
(A) a first conductive material layer made of a first conductive material in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region and capable of injecting charges into the channel region; and
(B) a second conductive material layer made of a second conductive material that is in contact with a portion of the organic semiconductor material layer that does not constitute a channel region and has a lower charge injection efficiency into the organic semiconductor material layer than the first conductive material;
It is characterized by comprising.

In order to achieve the above object, a field effect transistor according to the second aspect of the present invention provides:
(A) a gate electrode,
(B) a gate insulating layer;
(C) source / drain electrodes, and
(D) an organic semiconductor material layer located between the source / drain electrodes, facing the gate electrode through the gate insulating layer, and having a channel region induced by application of a gate voltage to the gate electrode in a part thereof;
A field effect transistor comprising:
The source / drain electrodes are
(A) a first conductive material layer in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region, and
(B) a second conductive material layer in contact with a portion of the organic semiconductor material layer that does not constitute the channel region;
Consisting of
A contact resistance value between the first conductive material layer and the organic semiconductor material layer is lower than a contact resistance value between the second conductive material layer and the organic semiconductor material layer.

The field effect transistor according to the third aspect of the present invention for achieving the above object is a so-called bottom gate type field effect transistor,
(A) a gate electrode formed on a support;
(B) a gate insulating layer formed on the gate electrode and on the support;
(C) source / drain electrodes formed on the gate insulating layer, and
(D) A channel region that is located on a portion of the gate insulating layer between the source / drain electrodes, faces the gate electrode through the gate insulating layer, and is induced by application of a gate voltage to the gate electrode. An organic semiconductor material layer having,
A field effect transistor comprising:
The source / drain electrodes are
(A) a first conductive material layer made of a first conductive material in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region and capable of injecting charges into the channel region; and
(B) a second conductive material layer made of a second conductive material that is in contact with a portion of the organic semiconductor material layer that does not constitute a channel region and has a lower charge injection efficiency into the organic semiconductor material layer than the first conductive material;
It is characterized by comprising.

The field effect transistor according to the fourth aspect of the present invention for achieving the above object is a so-called bottom gate type field effect transistor,
(A) a gate electrode formed on a support;
(B) a gate insulating layer formed on the gate electrode and on the support;
(C) source / drain electrodes formed on the gate insulating layer, and
(D) A channel region that is located on a portion of the gate insulating layer between the source / drain electrodes, faces the gate electrode through the gate insulating layer, and is induced by application of a gate voltage to the gate electrode. An organic semiconductor material layer having,
A field effect transistor comprising:
The source / drain electrodes are
(A) a first conductive material layer in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region, and
(B) a second conductive material layer in contact with a portion of the organic semiconductor material layer that does not constitute the channel region;
Consisting of
A contact resistance value between the first conductive material layer and the organic semiconductor material layer is lower than a contact resistance value between the second conductive material layer and the organic semiconductor material layer.

The field effect transistor according to the fifth aspect of the present invention for achieving the above object is a so-called top gate type field effect transistor,
(A) source / drain electrodes formed on a support;
(B) an organic semiconductor material layer formed on the portion of the support located between the source / drain electrodes;
(C) a gate insulating layer formed on the organic semiconductor material layer, and
(D) a gate electrode formed on the gate insulating layer;
A field effect transistor comprising:
The organic semiconductor material layer is opposed to the gate electrode through the gate insulating layer, and has a channel region induced in part by application of a gate voltage to the gate electrode,
The source / drain electrodes are
(A) a first conductive material layer made of a first conductive material in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region and capable of injecting charges into the channel region; and
(B) a second conductive material layer made of a second conductive material that is in contact with a portion of the organic semiconductor material layer that does not constitute a channel region and has a lower charge injection efficiency into the organic semiconductor material layer than the first conductive material;
It is characterized by comprising.

The field effect transistor according to the sixth aspect of the present invention for achieving the above object is a so-called top gate type field effect transistor,
(A) source / drain electrodes formed on a support;
(B) an organic semiconductor material layer formed on the portion of the support located between the source / drain electrodes;
(C) a gate insulating layer formed on the organic semiconductor material layer, and
(D) a gate electrode formed on the gate insulating layer;
A field effect transistor comprising:
The organic semiconductor material layer is opposed to the gate electrode through the gate insulating layer, and has a channel region induced in part by application of a gate voltage to the gate electrode,
The source / drain electrodes are
(A) a first conductive material layer in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region, and
(B) a second conductive material layer in contact with a portion of the organic semiconductor material layer that does not constitute the channel region;
Consisting of
A contact resistance value between the first conductive material layer and the organic semiconductor material layer is lower than a contact resistance value between the second conductive material layer and the organic semiconductor material layer.

  In the field effect transistor according to the first to sixth aspects of the present invention, the first conductive material layer and the second conductive material layer may be laminated. Alternatively, in the field effect transistor according to the first to fourth aspects of the present invention, the second conductive material layer is located farther from the channel region than the first conductive material layer. It can be set as the structure arrange | positioned in parallel with the electrically-conductive material layer.

  In the field effect transistor according to the third and fourth aspects of the present invention, it is preferable that an adhesion layer is formed between the gate insulating layer and the first conductive material layer. In this case, the thickness of the adhesion layer is desirably 1 nm or more and 5 nm or less.

The field effect transistors according to the first to sixth aspects of the present invention including the preferred modes and configurations described above (hereinafter, these may be collectively referred to simply as the field effect transistors of the present invention). In this case, it is preferable that 1 ≦ t ₁ / t _C ≦ 10 is satisfied, where t _C is the average thickness of the channel region and t ₁ is the thickness of the first conductive material layer. In the field effect transistor of the present invention including these forms, the thickness of the first conductive material layer is preferably 1 nm or more and 10 nm or less.

  In the field effect transistor according to the second aspect, the fourth aspect, or the sixth aspect of the present invention, the first conductive material layer is alternatively in ohmic contact with the organic semiconductor material layer. The first conductive material may be selected from such materials, and the second conductive material may be selected from materials in which the second conductive material layer is non-ohmically bonded to the organic semiconductor material layer.

Alternatively, in the field effect transistor according to the second aspect, the fourth aspect, or the sixth aspect of the present invention, the sheet resistance value of the channel region is R, and the organic semiconductor material does not constitute the channel region. When the specific resistance value of the layer portion is ρ,
ρ / t ₂ > R · t _C / t ₁
It is desirable to satisfy

  In the field effect transistor of the present invention including the preferred embodiment and configuration described above, when the conductivity type of the organic semiconductor material constituting the organic semiconductor material layer is p-type, the first conductive material is gold (Au), Name one material selected from the group consisting of metal materials having a high work function such as platinum (Pt) and palladium (Pd), polyethylene dioxythiophene doped with polyethylene sulfonic acid, and polyaniline doped with dodecylbenzene sulfonic acid. As the second conductive material, one material selected from the group consisting of titanium (Ti), chromium (Cr), aluminum (Al), copper (Cu), and lithium (Li) can be cited. . When the first conductive material is gold, platinum, or palladium, the adhesion layer can be made of chromium (Cr) or titanium (Ti), and when the first conductive material is gold. The adhesion layer can be composed of a self-assembled monolayer of a mercapto-based silane coupling agent (for example, mercaptopropyltrimethoxysilane).

  On the other hand, when the conductivity type of the organic semiconductor material constituting the organic semiconductor material layer is n-type, the first conductive material is titanium (Ti), chromium (Cr), aluminum (Al), copper (Cu), lithium ( One material selected from the group consisting of Li) can be mentioned, and the second conductive material is polyethylene dioxy doped with gold (Au), platinum (Pt), palladium (Pd), polyethylene sulfonic acid. Mention may be made of one material selected from the group consisting of thiophene, polyaniline doped with dodecylbenzenesulfonic acid.

In the field effect transistor of the present invention including the preferred embodiments and configurations described above, as a material constituting the organic semiconductor material layer, specifically, 2,3,6,7-dibenzoanthracene (also referred to as pentacene), C ₉ S ₉ (benzo [1,2-c; 3,4-c ′; 5,6-c ″] tris [1,2] dithiol-1,4,7-trithione), C ₂₄ H ₁₄ S ₆ (Alpha-sexithiophene), phthalocyanine represented by copper phthalocyanine, fullerene (C ₆₀ ), tetrathiotetracene (C ₁₈ H ₈ S ₄ ), tetraselenotetracene (C ₁₈ H ₈ Se ₄ ), tetratellur tetracene ( C ₁₈ H ₈ Te _4), poly (3-hexylthiophene), polyfluorene (C ₁₃ H _10), conductivity type is p-type poly (3,4-ethylenedioxythiophene) / Police In addition, the structural formula (1) of poly (3,4-ethylenedioxythiophene) and the structural formula (2) of polystyrene sulfonic acid are shown in FIG. In general, whether the organic semiconductor material layer has an n-type or p-type polarity depends on conditions for producing and forming the organic semiconductor material layer.

Alternatively, for example, a heterocyclic conjugated conductive polymer and a heteroatom-containing conductive polymer exemplified below can be used as the organic semiconductor material layer. In the structural formula, “R” and “R ′” mean an alkyl group (C _n H _{2n + 1} ).

[Heterocyclic conjugated conductive polymer]
Polypyrrole [see structural formula (3) in FIG. 4]
Polyfuran [see structural formula (4) in FIG. 4]
Polythiophene [see structural formula (5) in FIG. 4]
Polyselenophene [see structural formula (6) in FIG. 4]
Polytellophene [see structural formula (7) in FIG. 4]
Poly (3-alkylthiophene) [see structural formula (8) in FIG. 4]
Poly (3-thiophene-β-ethanesulfonic acid) [see structural formula (9) in FIG. 4]
Poly (N-alkylpyrrole) [see structural formula (10) in FIG. 5]
Poly (3-alkylpyrrole) [see structural formula (11) in FIG. 5]
Poly (3,4-dialkylpyrrole) [see structural formula (12) in FIG. 5]
Poly (2,2′-thienylpyrrole) [see structural formula (13) in FIG. 5]

[Containing heteroatom-containing conductive polymer]
Polyaniline [see structural formula (14) in FIG. 5]
Poly (dibenzothiophene sulfide) [see structural formula (15) in FIG. 5]

Alternatively, the organic semiconductor molecule constituting the organic semiconductor material layer is an organic semiconductor molecule having a conjugated bond, and a thiol group (SH), an amino group (—NH ₂ ), an isocyano group (—NC) at both ends of the molecule. It is desirable to have a thioacetyl group (—SCOCH ₃ ) or a carboxy group (—COOH), and more specifically, examples of organic semiconductor molecules include the following materials.

4,4′-biphenyldithiol [see structural formula (16) in FIG. 6]
4,4′-Diisocyanobiphenyl [see the structural formula (17) in FIG. 6]
4,4′-Diisocyano-p-terphenyl [see structural formula (18) in FIG. 6]
2,5-bis (5′- thioacetyl- 2′-thiophenyl) thiophene [see the structural formula (19) in FIG. 6]

  As a method for forming the organic semiconductor material layer, although depending on the material constituting the organic semiconductor material layer, physical vapor deposition method (PVD method) exemplified by vacuum deposition method and sputtering method; (CVD method); spin coating method; various printing methods such as screen printing method, ink jet printing method, offset printing method, gravure printing method; air doctor coater method, blade coater method, rod coater method, knife coater method, squeeze coater method , Reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calender coater method, dipping method, and any of the spray methods Can be mentioned.

  Materials constituting the gate electrode include platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), molybdenum (Mo), niobium (Nb), neodymium (Nd), rubidium ( Rb), rhodium (Rh), aluminum (Al), silver (Ag), tantalum (Ta), tungsten (W), titanium (Ti), copper (Cu), indium (In), tin (Sn), and other metals Or alloys containing these metal elements, conductive particles made of these metals, conductive particles of alloys containing these metals, polysilicon, amorphous silicon, tin oxide, indium oxide, indium / tin oxide ( ITO) or a laminated structure of layers containing these elements. Furthermore, as a material constituting the gate electrode, an organic material such as poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS] can be exemplified.

  As a method for forming a gate electrode or a source / drain electrode (first conductive material layer and second conductive material layer), a material constituting the gate electrode or source / drain electrode (first conductive material layer and second conductive material layer) is used. Although it depends, PVD method exemplified by vacuum deposition method and sputtering method; Various CVD methods including MOCVD method; Spin coating method; Various printing methods using various conductive pastes; Various coating methods described above; Lift-off A shadow mask method; a spray method; and a plating method such as an electrolytic plating method, an electroless plating method, or a combination thereof, or a combination with a patterning technique as necessary. . In addition, as the PVD method, (a) various vacuum deposition methods such as electron beam heating method, resistance heating method, flash deposition, (b) plasma deposition method, (c) bipolar sputtering method, direct current sputtering method, direct current magnetron sputtering method Various sputtering methods such as high-frequency sputtering method, magnetron sputtering method, ion beam sputtering method, bias sputtering method, (d) DC (direct current) method, RF method, multi-cathode method, activation reaction method, electric field evaporation method, high-frequency method Various ion plating methods such as an ion plating method and a reactive ion plating method can be given.

As a material constituting the gate insulating layer, not only a silicon oxide material, silicon nitride (SiN _Y ), Al ₂ O ₃ , HfO ₂ , a metal oxide high dielectric insulating film, but also an inorganic insulating material can be used. Illustrated with methyl methacrylate (PMMA), polyvinyl phenol (PVP), polyvinyl alcohol (PVA), polyethylene terephthalate (PET), polyoxymethylene (POM), polyvinyl chloride, polyvinylidene fluoride, polysulfone, polycarbonate (PC), polyimide An organic insulating material can be used, and a combination of these can also be used. As silicon oxide materials, silicon dioxide (SiO _x ), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin on glass), low dielectric constant SiO ₂ materials (for example, polyaryl) And ether, cycloperfluorocarbon polymer and benzocyclobutene, cyclic fluororesin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon, and organic SOG). As a method of forming the gate insulating layer, PVD method exemplified by vacuum deposition method and sputtering method; various CVD methods; spin coating method; various printing methods described above; various coating methods described above; immersion method; casting method; Any of the laws can be mentioned.

  Examples of the support include various glass substrates, various glass substrates having an insulating layer formed on the surface, a quartz substrate, a quartz substrate having an insulating layer formed on the surface, and a silicon substrate having an insulating layer formed on the surface. it can. Furthermore, as a support, polyethersulfone (PES), polyimide, polycarbonate (PC), polyethylene terephthalate (PET), polymethyl methacrylate (polymethyl methacrylate, PMMA), polyvinyl alcohol (PVA), polyvinylphenol (PVP) And a plastic film, a plastic sheet, and a plastic substrate made of a polymer material exemplified in the above. If a support made of such a flexible polymer material is used, for example, A field effect transistor can be incorporated or integrated into a display device or electronic device having a curved surface. Other examples of the support include a conductive substrate (a substrate made of a metal such as gold or highly oriented graphite). Further, depending on the configuration and structure of the field effect transistor, the field effect transistor is provided on the support member, but this support member can also be formed of the above-described materials.

  When the field effect transistor of the present invention is applied to and used in a display device or various electronic devices, it may be a monolithic integrated circuit in which a number of field effect transistors are integrated on a support, or each field effect transistor may be cut. It may be individualized and used as a discrete part. Further, an electronic device or a field effect transistor may be sealed with resin.

  In the present invention, the source / drain electrodes are in contact with (a) the portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region, and the first conductive material made of the first conductive material capable of injecting charge into the channel region. A second conductive material that is in contact with the material layer and (b) the portion of the organic semiconductor material layer that does not constitute the channel region, and has a lower efficiency of charge injection into the organic semiconductor material layer than the first conductive material. The contact resistance value between the first conductive material layer and the organic semiconductor material layer is lower than the contact resistance value between the second conductive material layer and the organic semiconductor material layer. Accordingly, the first conductive material constituting the other source / drain electrode is passed through the channel region induced by the application of the gate voltage to the gate electrode from the first conductive material layer constituting the one source / drain electrode. To the layer, current flows easily. Here, the channel region is a portion of the organic semiconductor material layer located between the source / drain electrodes, and is induced in a portion near the gate insulating layer. However, the portion of the organic semiconductor material layer away from the channel region from the second conductive material layer constituting one of the source / drain electrodes (this portion is located far from the gate insulating layer, which cannot be controlled by the gate electrode). ), The current hardly flows to the second conductive material layer constituting the other source / drain electrode. As a result, it is possible to reliably avoid the occurrence of a phenomenon in which off current increases due to an increase in background carriers in a portion of the organic semiconductor material layer that cannot be controlled by the gate electrode, away from the channel region. . In addition, since the source / drain electrode is composed of the first conductive material layer and the second conductive material layer, the resistance of the source / drain electrode can be reduced.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Example 1 relates to the field effect transistor according to the first, second, third, and fourth aspects of the present invention. A schematic partial sectional view of the field-effect transistor of Example 1 is shown in FIG.

The field effect transistor of Example 1 is
(A) Gate electrode 12,
(B) the gate insulating layer 13;
(C) source / drain electrode 21, and
(D) An organic semiconductor located between the source / drain electrodes 21, facing the gate electrode 12 through the gate insulating layer 13, and having a channel region 15 induced in part by application of a gate voltage to the gate electrode 12. Material layer 14,
It has.

Alternatively, the field effect transistor of Example 1 is a so-called bottom gate (/ bottom contact) type thin film transistor (TFT),
(A) a gate electrode 12 formed on the support 11;
(B) a gate insulating layer 13 formed on the gate electrode 12 and the support 11;
(C) a source / drain electrode 21 formed on the gate insulating layer 13, and
(D) A channel that is located on the portion of the gate insulating layer 13 between the source / drain electrodes 21, faces the gate electrode 12 through the gate insulating layer 13, and is induced by application of a gate voltage to the gate electrode 12. An organic semiconductor material layer 14 having a region 15 in part thereof,
It has.

The source / drain electrode 21 is
(A) a first conductive material layer 22 made of a first conductive material in contact with the gate insulating layer 13 and the organic semiconductor material layer 14 constituting the channel region 15 and capable of injecting charges into the channel region 15;
(B) a second conductive material made of a second conductive material that is in contact with the portion of the organic semiconductor material layer 14 that does not constitute the channel region 15 and has a lower charge injection efficiency into the organic semiconductor material layer than the first conductive material. Layer 23,
Consists of.

Alternatively, the source / drain electrode 21 is
(A) a first conductive material layer 22 in contact with a portion of the organic semiconductor material layer 14 constituting the gate insulating layer 13 and the channel region 15, and
(B) a second conductive material layer 23 in contact with a portion of the organic semiconductor material layer 14 that does not constitute the channel region 15;
Consisting of
The contact resistance value R _C1 between the first conductive material layer 22 and the organic semiconductor material layer 14 is lower than the contact resistance value R _C2 between the second conductive material layer 23 and the organic semiconductor material layer 14.

  In the field effect transistor of Example 1, the first conductive material layer 22 and the second conductive material layer 23 are laminated.

In Example 1, the support 11 is composed of a glass substrate on the surface of which a laminated film (not shown) of a SiN _x layer and a SiO _y layer is formed as a buffer layer. The gate electrode 12 is made of copper, the gate insulating layer 13 is made of SiO ₂ , and the organic semiconductor material layer 14 is made of pentacene having a conductivity type of p-type.

The first conductive material constituting the first conductive material layer 22 having a thickness t ₁ of 5 nm is gold (Au), and the second conductive material layer 23 constituting the second conductive material layer 23 having a thickness t ₂ of 50 nm is used. The conductive material is chromium (Cr). The average thickness t _C of the channel region 15 is 3 nm. Here, the contact resistance value R _C1 between the first conductive material layer 22 and the organic semiconductor material layer 14 is 100 kΩ / □, while the contact resistance between the second conductive material layer 23 and the organic semiconductor material layer 14. The value R _C2 is 1 GΩ · cm. Further, when the sheet resistance value of the channel region 15 is R and the specific resistance value of the portion of the organic semiconductor material layer 14 that does not constitute the channel region 15 is ρ, ρ / t ₂ > R · t _C / t ₁ is satisfied. ing. Here, R = 100 MΩ / □ and ρ = 10 GΩ · cm.

  Hereinafter, an outline of a manufacturing method of the bottom gate (/ bottom contact) type TFT of Example 1 will be described.

[Step-100]
First, the gate electrode 12 is formed on a support 11 made of a glass substrate having a SiO ₂ layer (not shown) formed on the surface based on a screen printing method using a copper paste.

[Step-110]
Next, a gate insulating layer 13 made of SiO _{2 is} formed on the gate electrode 12 and the support 11 based on a sputtering method.

[Step-120]
Thereafter, a first conductive material layer 22 and a second conductive material layer 23 are sequentially formed on the gate insulating layer 13 based on a vacuum deposition method. Note that by covering part of the gate insulating layer 13 with a hard mask, the first conductive material layer 22 and the second conductive material layer 23 can be formed without a photolithography process.

  Alternatively, a patterned first conductive material made of a first conductive material based on a printing technique such as a sputtering method, a lift-off method, an etching method, a plating method, an inkjet printing method, a screen printing method, an offset printing method, or a gravure printing method. After the material layer 22 is formed on the gate insulating layer 13, the patterned second conductive material layer 23 made of the second conductive material is formed on the basis of sputtering, lift-off, etching, plating, and various printing techniques. It may be formed on the first conductive material layer 22.

  Alternatively, the first conductive material layer 22 and the second conductive material layer 23 may be formed based on a lift-off method. That is, after a region where the first conductive material layer 22 and the second conductive material layer 23 are to be formed is exposed and the other region is covered with a resist layer, the resist material is used to obtain a state by lithography, The first conductive material layer 22 and the second conductive material layer 23 are sequentially formed on the entire surface based on various methods, and then the resist layer and the first conductive material layer 22 and the second conductive material layer 23 thereon are removed. Thus, the source / drain electrode 21 having a structure in which the first conductive material layer 22 and the second conductive material layer 23 are stacked can be obtained.

  Alternatively, a layer made of the first conductive material and a layer made of the second conductive material are sequentially formed on the gate insulating layer 13, and then the layer made of the second conductive material and the first conductive material are used. By sequentially patterning the layers, the source / drain electrode 21 having a structure in which the first conductive material layer 22 and the second conductive material layer 23 are stacked can be obtained.

[Step-130]
Next, the organic semiconductor material layer 14 is formed on the entire surface. Specifically, the organic semiconductor material layer 14 made of pentacene is formed on the source / drain electrode 21 and the gate insulating layer 13 based on the vacuum deposition method illustrated in Table 1 below. When the organic semiconductor material layer 14 is formed, the organic semiconductor material layer 14 can be formed without a photolithography process by covering part of the source / drain electrodes 21 and the gate insulating layer 13 with a hard mask. .

[Table 1]
Support temperature: 60 ° C
Deposition rate: 3 nm / min Pressure: 5 × 10 ⁻⁴ Pa

  Alternatively, for example, the organic semiconductor material layer 14 made of polythiophene or polyfluorene can be formed on the source / drain electrode 21 and the gate insulating layer 13 based on a screen printing method or a spin coating method.

[Step-140]
Finally, an insulating layer (not shown) as a passivation film is formed on the entire surface, an opening is formed in the insulating layer above the source / drain electrode 21, and a wiring material layer is formed on the entire surface including the inside of the opening. By patterning the wiring material layer, the field effect transistor of Example 1 in which the wiring (not shown) connected to the source / drain electrode 21 is formed on the insulating layer can be completed.

  1 (B), (C), and FIGS. 2 (A), (B), (C) are modified examples of the field effect transistor [bottom gate (/ bottom contact) type TFT] of the first embodiment. The typical partial sectional view of is shown.

  In the modification shown in FIG. 1B, the size of the first conductive material layer 22 is larger than the size of the second conductive material layer 23.

  In FIG. 1C, the second conductive material layer 23 is located farther from the channel region 15 than the first conductive material layer 22, and the second conductive material layer 23 is the first conductive material layer 22. (That is, provided adjacent to the first conductive material layer 22), and the first conductive material layer 22 and the second conductive material layer 23 are in contact with the gate insulating layer 13.

  2A, 2B, and 2C, the first conductive material layer 22 in the field effect transistor shown in FIGS. 1A, 1B, and 1C. An adhesion layer 24 made of titanium (Ti) or chromium (Cr) having a thickness of 1 to 3 nm is formed between the gate insulating layer 13 and the gate insulating layer 13.

  Example 2 relates to the field effect transistor according to the first to second and fifth to sixth aspects of the present invention. A schematic partial cross-sectional view of the field-effect transistor of Example 2 is shown in FIG.

The field effect transistor of Example 2 is
(A) Gate electrode 12,
(B) the gate insulating layer 13;
(C) source / drain electrode 21, and
(D) An organic semiconductor located between the source / drain electrodes 21, facing the gate electrode 12 through the gate insulating layer 13, and having a channel region 15 induced in part by application of a gate voltage to the gate electrode 12. Material layer 14,
It has.

Alternatively, the field effect transistor of Example 2 is a so-called top gate (/ bottom contact) type thin film transistor (TFT),
(A) a source / drain electrode 21 formed on a support;
(B) an organic semiconductor material layer 14 formed on the portion of the support located between the source / drain electrodes 21;
(C) a gate insulating layer 13 formed on the organic semiconductor material layer 14, and
(D) a gate electrode formed on the gate insulating layer 13;
With
The organic semiconductor material layer 14 is opposed to the gate electrode with the gate insulating layer 13 interposed therebetween, and has a channel region 15 that is induced by application of a gate voltage to the gate electrode.

The source / drain electrode 21 is the same as in the first embodiment.
(A) a first conductive material layer 22 made of a first conductive material in contact with the gate insulating layer 13 and the organic semiconductor material layer 14 constituting the channel region 15 and capable of injecting charges into the channel region 15;
(B) a second conductive material made of a second conductive material that is in contact with the portion of the organic semiconductor material layer 14 that does not constitute the channel region 15 and has a lower charge injection efficiency into the organic semiconductor material layer than the first conductive material. Layer 23,
Consists of.

Alternatively, the source / drain electrode 21 is the same as in the first embodiment.
(A) a first conductive material layer 22 in contact with a portion of the organic semiconductor material layer 14 constituting the gate insulating layer 13 and the channel region 15, and
(B) a second conductive material layer 23 in contact with a portion of the organic semiconductor material layer 14 that does not constitute the channel region 15;
Consisting of
The contact resistance value R _C1 between the first conductive material layer 22 and the organic semiconductor material layer 14 is lower than the contact resistance value R _C2 between the second conductive material layer 23 and the organic semiconductor material layer 14.

  Also in the field effect transistor of Example 2, the first conductive material layer 22 and the second conductive material layer 23 are laminated.

Since the material constituting each part of the field effect transistor of Example 2 can be the same as the material constituting each part of the field effect transistor described in Example 1, detailed description thereof is omitted. . The thickness t ₁ of the first conductive material layer 22, the thickness t ₂ of the second conductive material layer 23, the average of the channel region 15 thickness t _C, the first conductive material layer 22 and the organic semiconductor material layer 14 The contact resistance value R _C1 between them, the contact resistance value R _C2 between the second conductive material layer 23 and the organic semiconductor material layer 14, the sheet resistance value R of the channel region 15, and the organic semiconductor material layer 14 that does not constitute the channel region 15. Each value of the specific resistance value ρ of the portion is also the same value as described in the first embodiment.

  The outline of the method for manufacturing the top gate (/ bottom contact) type TFT of Example 2 will be described below.

[Step-200]
First, the second conductive material layer 23 and the first conductive material layer 22 are sequentially formed on a support 11 made of a glass substrate having a SiO ₂ layer (not shown) formed on the surface, based on a lift-off method. That is, after the region where the second conductive material layer 23 and the first conductive material layer 22 are to be formed is exposed and the other regions are covered with the resist layer, the resist material is used to obtain the state by lithography, A second conductive material layer 23 and a first conductive material layer 22 are sequentially formed on the entire surface by sputtering. Next, by removing the resist layer and the second conductive material layer 23 and the first conductive material layer 22 thereon, the source / drain having a structure in which the second conductive material layer 23 and the first conductive material layer 22 are stacked. The electrode 21 can be formed on the support 11. In addition, as a method of forming the source / drain electrode 21 having a structure in which the second conductive material layer 23 and the first conductive material layer 22 are laminated, the method described in [Step-120] of Example 1 (however, The film formation order of the first conductive material layer 22 and the second conductive material layer 23 may be reversed).

[Step-210]
Thereafter, for example, an organic semiconductor material layer 14 made of polythiophene or polyfluorene is formed on the portion of the support 11 between the source / drain electrodes 21 based on a screen printing method.

[Step-220]
Next, the gate insulating layer 13 is formed on the entire surface. Specifically, the gate insulating layer 13 made of SiO ₂ is formed on the entire surface (specifically, on the organic semiconductor material layer 14 and the source / drain electrode 21) by sputtering.

[Step-230]
Thereafter, the gate electrode 12 is formed on the gate insulating layer 13 based on a screen printing method using a copper paste.

[Step-240]
Finally, an insulating layer (not shown) as a passivation film is formed on the entire surface, an opening is formed in the insulating layer above the source / drain electrode 21, and a wiring material layer is formed on the entire surface including the inside of the opening. By patterning the wiring material layer, the field effect transistor of Example 2 in which the wiring (not shown) connected to the source / drain electrode 21 is formed on the insulating layer can be completed.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. The structure and configuration of the field-effect transistor, manufacturing conditions, and materials used are examples, and can be changed as appropriate. When the field effect transistor (TFT) obtained by the present invention is applied to and used in a display device or various electronic devices, a monolithic integrated circuit in which a large number of TFTs are integrated on a support or a support member may be used. The TFT may be cut and individualized and used as a discrete component.

FIGS. 1A, 1 </ b> B, and 1 </ b> C are schematic partial cross-sectional views of the field-effect transistor of the first embodiment and a modification thereof. 2A, 2B, and 2C are schematic partial cross-sectional views of modifications of the field-effect transistor of Example 1. FIG. FIG. 3 is a schematic partial cross-sectional view of the field effect transistor according to the second embodiment. FIG. 4 illustrates the structural formula of an organic semiconductor material suitable for use in the present invention. FIG. 5 illustrates the structural formula of an organic semiconductor material suitable for use in the present invention. FIG. 6 illustrates the structural formula of an organic semiconductor material suitable for use in the present invention. FIG. 7 is a schematic partial cross-sectional view of an organic TFT for explaining a problem in a conventional organic TFT.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Support body, 12 ... Gate electrode, 13 ... Gate insulating layer, 14 ... Organic-semiconductor material layer, 15 ... Channel region, 21 ... Source / drain electrode, 22 ... First conductive material layer, 23 ... second conductive material layer, 24 ... adhesion layer

Claims (8)

(A) a gate electrode,
(B) a gate insulating layer;
(C) source / drain electrodes, and
(D) an organic semiconductor material layer located between the source / drain electrodes, facing the gate electrode through the gate insulating layer, and having a channel region induced by application of a gate voltage to the gate electrode in a part thereof;
A field effect transistor comprising:
The source / drain electrodes are
(A) a first conductive material layer made of a first conductive material in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region and capable of injecting charges into the channel region; and
(B) a second conductive material layer made of a second conductive material that is in contact with a portion of the organic semiconductor material layer that does not constitute a channel region and has a lower charge injection efficiency into the organic semiconductor material layer than the first conductive material;
Consisting of
The field effect transistor in which the second conductive material layer is arranged in parallel with the first conductive material layer at a position farther from the channel region than the first conductive material layer. (A) a gate electrode,
(B) a gate insulating layer;
(C) source / drain electrodes, and
(D) an organic semiconductor material layer located between the source / drain electrodes, facing the gate electrode through the gate insulating layer, and having a channel region induced by application of a gate voltage to the gate electrode in a part thereof;
A field effect transistor comprising:
The source / drain electrodes are
(A) a first conductive material layer in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region, and
(B) a second conductive material layer in contact with a portion of the organic semiconductor material layer that does not constitute the channel region;
Consisting of
The contact resistance value between the first conductive material layer and the organic semiconductor material layer is lower than the contact resistance value between the second conductive material layer and the organic semiconductor material layer ,
The field effect transistor in which the second conductive material layer is arranged in parallel with the first conductive material layer at a position farther from the channel region than the first conductive material layer. (A) a gate electrode formed on a support;
(B) a gate insulating layer formed on the gate electrode and on the support;
(C) source / drain electrodes formed on the gate insulating layer, and
(D) A channel region that is located on a portion of the gate insulating layer between the source / drain electrodes, faces the gate electrode through the gate insulating layer, and is induced by application of a gate voltage to the gate electrode. An organic semiconductor material layer having,
A field effect transistor comprising:
The source / drain electrodes are
(A) a first conductive material layer made of a first conductive material in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region and capable of injecting charges into the channel region; and
(B) a second conductive material layer made of a second conductive material that is in contact with a portion of the organic semiconductor material layer that does not constitute a channel region and has a lower charge injection efficiency into the organic semiconductor material layer than the first conductive material;
Consisting of
The field effect transistor in which the second conductive material layer is arranged in parallel with the first conductive material layer at a position farther from the channel region than the first conductive material layer. (A) a gate electrode formed on a support;
(B) a gate insulating layer formed on the gate electrode and on the support;
(C) source / drain electrodes formed on the gate insulating layer, and
(D) A channel region that is located on a portion of the gate insulating layer between the source / drain electrodes, faces the gate electrode through the gate insulating layer, and is induced by application of a gate voltage to the gate electrode. An organic semiconductor material layer having,
A field effect transistor comprising:
The source / drain electrodes are
(A) a first conductive material layer in contact with a portion of the organic semiconductor material layer constituting the gate insulating layer and the channel region, and
(B) a second conductive material layer in contact with a portion of the organic semiconductor material layer that does not constitute the channel region;
Consisting of
The contact resistance value between the first conductive material layer and the organic semiconductor material layer is lower than the contact resistance value between the second conductive material layer and the organic semiconductor material layer ,
The field effect transistor in which the second conductive material layer is arranged in parallel with the first conductive material layer at a position farther from the channel region than the first conductive material layer. The field effect transistor according to claim 3 or 4 , wherein an adhesion layer is formed between the gate insulating layer and the first conductive material layer. The field effect transistor according to claim 5 , wherein the adhesion layer has a thickness of 1 nm to 5 nm. 5. The device according to claim ₁ , wherein 1 ≦ t ₁ / t _C ≦ 10 is satisfied, where t _C is an average thickness of the channel region and t ₁ is a thickness of the first conductive material layer. The field effect transistor described in 1. 5. The field-effect transistor according to claim 1 , wherein the thickness of the first conductive material layer is 1 nm or more and 10 nm or less.

Images