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JP4818287B2 - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device Download PDF

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Publication number
JP4818287B2
JP4818287B2 JP2008029857A JP2008029857A JP4818287B2 JP 4818287 B2 JP4818287 B2 JP 4818287B2 JP 2008029857 A JP2008029857 A JP 2008029857A JP 2008029857 A JP2008029857 A JP 2008029857A JP 4818287 B2 JP4818287 B2 JP 4818287B2
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Prior art keywords
semiconductor device
lead
resin
lead frame
semiconductor chip
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JP2008124510A (en
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智之 青山
敏行 福田
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

本発明は、リードフレームに半導体チップを搭載した樹脂封止型半導体装置に関するものである。 The present invention relates to a resin-encapsulated semiconductor device in which a semiconductor chip is mounted on a lead frame.

近年、携帯電話などを中心に電子機器の小型化の要望が強くなってきており、それらの電子機器に搭載される半導体装置を高密度化することで対応してきている。特に、製品の多機能化を図りながら、小型化、低コスト化の実現のために、複数の半導体チップが搭載された半導体装置が出現してきている。   In recent years, there has been a strong demand for downsizing electronic devices such as mobile phones, and the semiconductor devices mounted on these electronic devices have been addressed by increasing the density. In particular, semiconductor devices on which a plurality of semiconductor chips are mounted have emerged in order to realize miniaturization and cost reduction while achieving multi-functionality of products.

以下、従来の単体あるいは複数の半導体チップが搭載された樹脂封止型半導体装置について、図面を参照しながら説明する。
図１４および図１５は、従来の樹脂封止型半導体装置を示す図である。図１４（ａ）、図１５（ａ）は、それぞれ図１４（ｂ）、図１５（ｂ）に対応する断面図である。 Hereinafter, a conventional resin-encapsulated semiconductor device on which a single semiconductor chip or a plurality of semiconductor chips are mounted will be described with reference to the drawings.
14 and 15 are diagrams showing a conventional resin-encapsulated semiconductor device. 14 (a) and 15 (a) are cross-sectional views corresponding to FIGS. 14 (b) and 15 (b), respectively.

図１４（ａ）および図１４（ｂ）に示すように、リードフレーム１のダイパッド２と半導体チップ３の裏面とが接着され、半導体チップ３の電極４とリード５とが金属細線６により電気的に接続されている。そして、半導体チップ３、ダイパッド２および金属細線６が封止樹脂７により封止されている。   As shown in FIGS. 14A and 14B, the die pad 2 of the lead frame 1 and the back surface of the semiconductor chip 3 are bonded, and the electrode 4 and the lead 5 of the semiconductor chip 3 are electrically connected by the thin metal wire 6. It is connected to the. The semiconductor chip 3, the die pad 2, and the fine metal wire 6 are sealed with a sealing resin 7.

また、図１５（ａ）および図１５（ｂ）に示すように、リードフレーム８のダイパッド９と第１の半導体チップ１０の裏面とが接着され、第１の半導体チップ１０上の周辺部に形成された電極１１を除く部分と第２の半導体チップ１２とが接着され、第１の半導体チップ１０および第２の半導体チップ１２のそれぞれの電極とリード１３とが金属細線１４により電気的に接続されている。そして、第１の半導体チップ１０、第２の半導体チップ１２、ダイパッド９および金属細線１４が封止樹脂１５により封止されている。
特開昭６１−１１７８５８号公報 特開２００１−１２７１９９号公報 Further, as shown in FIGS. 15A and 15B, the die pad 9 of the lead frame 8 and the back surface of the first semiconductor chip 10 are bonded to each other and formed on the peripheral portion on the first semiconductor chip 10. The portion excluding the formed electrode 11 and the second semiconductor chip 12 are bonded, and the respective electrodes of the first semiconductor chip 10 and the second semiconductor chip 12 and the lead 13 are electrically connected by the metal thin wire 14. ing. The first semiconductor chip 10, the second semiconductor chip 12, the die pad 9, and the fine metal wire 14 are sealed with a sealing resin 15.
Japanese Patent Laid-Open No. 61-117858 JP 2001-127199 A

しかしながら、前記従来の樹脂封止型半導体装置は、半導体チップの電極数が増加し、複数の半導体チップが１つのリードフレームのダイパッドに搭載された場合、リードフレームのリードも多数設ける必要があるため、リードフレームのサイズが大きくなって半導体装置が大型化してしまうという問題があった。   However, in the conventional resin-encapsulated semiconductor device, the number of electrodes of the semiconductor chip increases, and when a plurality of semiconductor chips are mounted on the die pad of one lead frame, it is necessary to provide a large number of leads of the lead frame. There is a problem that the size of the lead frame increases and the semiconductor device becomes larger.

また、複数の半導体チップを金属配線パターンが形成された絶縁性の配線基板に搭載したＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）タイプの半導体装置が実現されており、この場合は、半導体チップの電極数が増加してもサイズは大きくなり難いが、一般に、リードフレームを用いた半導体装置よりも高コストであるという問題点がある。   In addition, a CSP (Chip Size Package) type semiconductor device in which a plurality of semiconductor chips are mounted on an insulating wiring board on which a metal wiring pattern is formed has been realized. In this case, the number of electrodes of the semiconductor chip increases. However, it is difficult to increase the size, but generally there is a problem that the cost is higher than that of a semiconductor device using a lead frame.

前記従来の課題を解決するために、本発明の樹脂封止型半導体装置は、ダイパッドの上面と第１の半導体チップの裏面とが接着され、前記第１の半導体チップの電極と第１のリードとが第１の金属細線により電気的に接続され、前記第１の半導体チップの上方に、コイルが設けられ、前記コイルの内方部と第２のリードとが前記コイルの一部を介して接続され、前記コイルの中央領域が周辺領域よりも高くなっており、前記第１の半導体チップ、前記第１の金属細線、前記第１のリードの上面および前記第２のリードの上面が、封止樹脂により封止されている。   In order to solve the above-described conventional problems, in the resin-encapsulated semiconductor device of the present invention, the upper surface of the die pad and the back surface of the first semiconductor chip are bonded, and the electrode and the first lead of the first semiconductor chip are bonded. Are electrically connected by a first thin metal wire, a coil is provided above the first semiconductor chip, and an inward portion of the coil and a second lead are interposed through a part of the coil. The central region of the coil is higher than the peripheral region, and the first semiconductor chip, the first metal wire, the upper surface of the first lead, and the upper surface of the second lead are sealed. It is sealed with a stop resin.

本発明の樹脂封止型半導体装置は、第１の半導体チップの上方に、コイルが設けられているので、高周波特性に優れた半導体装置を実現できる。   Since the coil is provided above the first semiconductor chip, the resin-encapsulated semiconductor device of the present invention can realize a semiconductor device having excellent high frequency characteristics.

以下、本発明の樹脂封止型半導体装置およびその製造方法の実施の形態について、図面を参照しながら説明する。
まず、半導体装置の第１の実施形態について説明する。 Hereinafter, embodiments of a resin-encapsulated semiconductor device and a method for manufacturing the same according to the present invention will be described with reference to the drawings.
First, a first embodiment of a semiconductor device will be described.

図１および図２は、本発明の実施形態である樹脂封止型半導体装置を示す図である。
図１（ａ）、図１（ｂ）および図２に示すように、第１のリードフレーム１６のダイパッド１７に、第１の半導体チップ１８の裏面が接着され、第１の半導体チップ１８の電極１９と第１のリード（図示せず）とが第１の金属細線２０により電気的に接続され、第１の半導体チップ１８、第１の金属細線２０および第１のリードの上面が第１の封止樹脂２１により封止され、第１の封止樹脂２１の上面に第２のリードフレーム２２の第２のダイパッド２３が接着され、第２のダイパッド２３の上面と第２の半導体チップ２４の裏面とが接着され、第２の半導体チップ２４の電極２５と第２のリード（図示せず）とが第２の金属細線２６により電気的に接続され、第２のダイパッド２３の上方で第２の半導体チップ２４、第２の金属細線２６および第２のリードの上面が第２の封止樹脂２７により封止されている。なお、各半導体チップの電極と各リードとはバンプにより直接接続したフリップチップ接続であってもよい。 1 and 2 are views showing a resin-encapsulated semiconductor device according to an embodiment of the present invention.
As shown in FIG. 1A, FIG. 1B, and FIG. 2, the back surface of the first semiconductor chip 18 is bonded to the die pad 17 of the first lead frame 16, and the electrodes of the first semiconductor chip 18 are bonded. 19 and a first lead (not shown) are electrically connected by a first fine metal wire 20, and the first semiconductor chip 18, the first fine metal wire 20, and the top surface of the first lead are the first metal wires 20. The second die pad 23 of the second lead frame 22 is bonded to the upper surface of the first sealing resin 21, and the upper surface of the second die pad 23 and the second semiconductor chip 24 are bonded. The back surface is bonded, the electrode 25 of the second semiconductor chip 24 and the second lead (not shown) are electrically connected by the second thin metal wire 26, and the second die pad 23 is over the second die pad 23. Semiconductor chip 24, second metal thin wire 26 Beauty upper surface of the second leads are sealed with the second sealing resin 27. Note that the electrodes of each semiconductor chip and each lead may be flip-chip connected directly by bumps.

また、図１（ｃ）および図１（ｄ）に示すように、第１のリードの先端および第２のリードの先端は、それぞれ第１の外部電極２８および第２の外部電極２９として各封止樹脂から突出している。第１の外部電極２８は、封止樹脂２１の底面に配列されている。本実施形態の半導体装置では、第２のリードが半導体装置の側面を経由して半導体装置の底面で曲がった、いわゆるガルウィング形状である。   In addition, as shown in FIGS. 1C and 1D, the tip of the first lead and the tip of the second lead are sealed as a first external electrode 28 and a second external electrode 29, respectively. It protrudes from the stop resin. The first external electrodes 28 are arranged on the bottom surface of the sealing resin 21. In the semiconductor device of this embodiment, the second lead has a so-called gull wing shape in which the second lead is bent at the bottom surface of the semiconductor device via the side surface of the semiconductor device.

次に、リードの形状として、本実施形態の変形例について説明する。
なお、前記した内容と同一の内容については省略し、同一の構成要件には同一の符号を付す。 Next, a modification of the present embodiment will be described as the lead shape.
In addition, about the same content as above-mentioned content, it abbreviate | omits and attaches | subjects the same code | symbol to the same component.

図３および図４は、半導体装置の変形例を示す図である。
図３（ａ）に示すように、第１のリードフレーム１６および第２のリードフレーム２２の各リードが封止樹脂の側面から突出している。 3 and 4 are diagrams illustrating modifications of the semiconductor device.
As shown in FIG. 3A, each lead of the first lead frame 16 and the second lead frame 22 protrudes from the side surface of the sealing resin.

また、図３（ｂ）に示すように、封止樹脂２７の側面で、図３（ａ）に示す状態から、第１の外部電極２８および第２の外部電極２９を成形することで、樹脂封止型半導体装置の側面を経由し、樹脂封止型半導体装置の底面でＪ字状に曲がった第２の外部電極２９を配置できる。また、第１の外部電極２８は樹脂封止型半導体装置の底面に露出している。   Further, as shown in FIG. 3B, the first external electrode 28 and the second external electrode 29 are formed on the side surface of the sealing resin 27 from the state shown in FIG. The second external electrode 29 bent in a J-shape can be arranged on the bottom surface of the resin-encapsulated semiconductor device via the side surface of the encapsulated semiconductor device. The first external electrode 28 is exposed on the bottom surface of the resin-encapsulated semiconductor device.

図３（ｃ）および図３（ｄ）は、本実施形態の樹脂封止型半導体装置を底面から見た平面図であり、第１の外部端子２８が樹脂封止型半導体装置の底面の周囲に配置されている場合（図３（ｃ））、第１の外部端子２８が樹脂封止型半導体装置の底面の周囲を除く部分に配置されている場合（図３（ｄ））がある。   FIG. 3C and FIG. 3D are plan views of the resin-encapsulated semiconductor device of this embodiment as viewed from the bottom, and the first external terminal 28 is around the bottom of the resin-encapsulated semiconductor device. In some cases, the first external terminal 28 is disposed in a portion other than the periphery of the bottom surface of the resin-encapsulated semiconductor device (FIG. 3D).

次に、第１のリードの外部端子が、樹脂封止型半導体装置の底面の周囲を除く部分に配列されている場合について説明する。
図４（ａ）に示すように、第１のリードフレーム１６および第２のリードフレーム２２の各リードが封止樹脂の側面から突出している。 Next, the case where the external terminals of the first lead are arranged in a portion excluding the periphery of the bottom surface of the resin-encapsulated semiconductor device will be described.
As shown in FIG. 4A, each lead of the first lead frame 16 and the second lead frame 22 protrudes from the side surface of the sealing resin.

また、図４（ｂ）に示すように、封止樹脂２７の側面で、図４（ａ）に示す状態から、第１の外部電極２８および第２の外部電極２９を成形することで、第１の外部電極２８と略同一の高さで、第２の外部電極２９を配置できる。また、第１のリード２８は樹脂封止型半導体装置の底面に露出している。なお、第１の外部電極２８の形状は円形でもよく（図４（ｃ））、四角形でもよい（図４（ｄ））。   Further, as shown in FIG. 4B, the first external electrode 28 and the second external electrode 29 are formed on the side surface of the sealing resin 27 from the state shown in FIG. The second external electrode 29 can be arranged at substantially the same height as the first external electrode 28. The first lead 28 is exposed on the bottom surface of the resin-encapsulated semiconductor device. The shape of the first external electrode 28 may be circular (FIG. 4C) or quadrangular (FIG. 4D).

以上、本実施形態の樹脂封止型半導体装置は、リードフレームが上下方向に配置された樹脂封止型半導体装置であるので、異種混合プロセス、例えば、ＤＲＡＭ混載、高周波特性に優れかつＧａＡｓ，ＳｉＧｅプロセスとＣＭＯＳデバイスなどの複数のチップを内蔵でき、半導体装置の平面方向の大型化を抑制することで、樹脂封止型半導体装置の小型化を実現できる。   As described above, since the resin-encapsulated semiconductor device of this embodiment is a resin-encapsulated semiconductor device in which lead frames are arranged in the vertical direction, it is excellent in heterogeneous mixed processes, for example, mixed DRAM, high frequency characteristics, and GaAs, SiGe. A plurality of chips, such as a process and a CMOS device, can be incorporated, and miniaturization of the resin-encapsulated semiconductor device can be realized by suppressing the enlargement of the semiconductor device in the planar direction.

次に、半導体装置の第２の実施形態について説明する。
なお、前記した半導体装置の実施形態と共通する内容については省略し、同一の構成要件には同一の符号を付す。 Next, a second embodiment of the semiconductor device will be described.
The contents common to the above-described embodiments of the semiconductor device are omitted, and the same constituent elements are denoted by the same reference numerals.

図５〜図７は、別の樹脂封止型半導体装置を示す図である。図６は図５に対応する斜視図である。
図５（ａ）および図５（ｂ）に示すように、第２のリードフレーム２２の中央部（第２のダイパッド）には、図５（ｃ）に示すような、周囲が吊りリードと接続するコイル３０が形成されている。 5 to 7 are diagrams showing other resin-encapsulated semiconductor devices. FIG. 6 is a perspective view corresponding to FIG.
As shown in FIGS. 5A and 5B, the periphery (the second die pad) of the second lead frame 22 is connected to the suspension leads as shown in FIG. 5C. A coil 30 is formed.

さらに、図６（ａ）および図６（ｂ）に示すように、前記構成の２つのリードフレームが上下方向に配置され、樹脂封止型半導体装置が構成されている。コイル３０は、第１のリードフレーム１６、第２のリードフレーム２２および第１のリードフレーム１６と第２のリードフレーム２２とを接続するフレーム３７を介して電気的に接続されている。そして、第１の外部電極２８は封止樹脂の底面に配列されており、配列された第１の外部電極２８は樹脂封止型半導体装置の底面の周囲に配列されていてもよく、樹脂封止型半導体装置の周囲を除く部分に配列されていてもよい。また第２の外部電極２９は、その先端部が第１の外部電極２８と略同一面に配列され、第２の封止樹脂２７から突出した第２の外部電極２９はガルウイング状やＪリード形状に成形されている。なお、第２のダイパッドがコイル形状になっている場合、コイル形状の第２のダイパッドの上面に第２の半導体チップを搭載しなくてもよい。   Further, as shown in FIGS. 6A and 6B, the two lead frames having the above-described configuration are arranged in the vertical direction to constitute a resin-encapsulated semiconductor device. The coil 30 is electrically connected via the first lead frame 16, the second lead frame 22, and the frame 37 that connects the first lead frame 16 and the second lead frame 22. The first external electrodes 28 are arranged on the bottom surface of the sealing resin, and the arranged first external electrodes 28 may be arranged around the bottom surface of the resin-encapsulated semiconductor device. You may arrange in the part except the circumference | surroundings of a stationary semiconductor device. The second external electrode 29 has a tip arranged on the same plane as the first external electrode 28, and the second external electrode 29 protruding from the second sealing resin 27 has a gull wing shape or a J lead shape. It is molded into. In the case where the second die pad has a coil shape, the second semiconductor chip may not be mounted on the upper surface of the coil-shaped second die pad.

また、図７に示すように、コイル３０は複数個形成されていてもよい。
以上、本実施形態の樹脂封止型半導体装置は、積層されたリードフレームを用いて上部となる第２のリードフレームにはコイルが形成されているので、高周波特性に優れた半導体装置を実現することができる。 As shown in FIG. 7, a plurality of coils 30 may be formed.
As described above, the resin-encapsulated semiconductor device according to the present embodiment realizes a semiconductor device having excellent high-frequency characteristics because a coil is formed on the second lead frame that is an upper portion using the stacked lead frames. be able to.

次に、半導体装置の第３の実施形態について説明する。
なお、第１の実施形態と同一の内容は省略し、同一の構成要件には同一の符号を付す。
図８および図９は、本実施形態の半導体装置を示す図である。 Next, a third embodiment of the semiconductor device will be described.
In addition, the same content as 1st Embodiment is abbreviate | omitted, and the same code | symbol is attached | subjected to the same component.
8 and 9 are diagrams showing the semiconductor device of the present embodiment.

図８に示すように、第２のリードフレーム２２の中央には、網目形状のシールド３１が形成されている。
そして、図９（ａ）に示すように、第１の外部電極２８は樹脂封止型半導体装置の底面に配列されている。また、図９（ｂ）に示すように、第２の外部電極２９は封止樹脂で覆われた領域の４角のコーナー部分より突出している場合もある。なお、シールド３１の１つの格子の形状（網目形状）は、四角形や楕円形であってもよい。 As shown in FIG. 8, a mesh-shaped shield 31 is formed at the center of the second lead frame 22.
Then, as shown in FIG. 9A, the first external electrodes 28 are arranged on the bottom surface of the resin-encapsulated semiconductor device. Further, as shown in FIG. 9B, the second external electrode 29 may protrude from the four corners of the region covered with the sealing resin. Note that the shape (mesh shape) of one lattice of the shield 31 may be a quadrangle or an ellipse.

本実施形態の樹脂封止型半導体装置は、第２のリードフレーム側には網目形状のシールドを形成しているので、電磁波による特性変動を防御でき、かつ平面形状の大型化を抑え、より小型の樹脂封止型半導体装置を実現できるものである。   In the resin-encapsulated semiconductor device of this embodiment, since the mesh-shaped shield is formed on the second lead frame side, it is possible to prevent fluctuations in characteristics due to electromagnetic waves, suppress the increase in size of the planar shape, and reduce the size. The resin-encapsulated semiconductor device can be realized.

次に、本実施形態の半導体装置の製造方法について説明する。
まず、半導体装置の製造方法の第１の実施形態について説明する。なお、各リードフレームの形状については前述したので省略する。 Next, a method for manufacturing the semiconductor device of this embodiment will be described.
First, a first embodiment of a method for manufacturing a semiconductor device will be described. Since the shape of each lead frame has been described above, it will be omitted.

図１０および図１１は、本実施形態の半導体装置の製造方法の各工程を示す断面図である。
まず、図１０（ａ）に示すように、上金型３２、下金型３３および上金型３２と下金型３３との間に設けられた中間金型３４を備えた封止金型を用意する。 10 and 11 are cross-sectional views showing the respective steps of the semiconductor device manufacturing method of the present embodiment.
First, as shown in FIG. 10A, a sealing mold including an upper mold 32, a lower mold 33, and an intermediate mold 34 provided between the upper mold 32 and the lower mold 33 is provided. prepare.

次に、図１０（ｂ）に示すように、第１の半導体チップ１８が接着された第１のリードフレーム１６を下金型３３の上面に載置し、第１のリードフレーム１６の周囲の上面に中間金型３４を載置する。   Next, as shown in FIG. 10B, the first lead frame 16 to which the first semiconductor chip 18 is bonded is placed on the upper surface of the lower mold 33, and the periphery of the first lead frame 16 is An intermediate mold 34 is placed on the upper surface.

次に、図１０（ｃ）に示すように、中間金型３４の上面に、第２の半導体チップ２４が接着された第２のリードフレーム２２を載置する。
次に、図１１（ａ）に示すように、第２のリードフレーム２２の上方から上金型３２を下降させて、上金型３２の周囲を第２のリードフレーム２２の上面に接触させる。 Next, as shown in FIG. 10C, the second lead frame 22 with the second semiconductor chip 24 bonded is placed on the upper surface of the intermediate mold 34.
Next, as shown in FIG. 11A, the upper mold 32 is lowered from above the second lead frame 22, and the periphery of the upper mold 32 is brought into contact with the upper surface of the second lead frame 22.

次に、図１１（ｂ）に示すように、上金型３２または下金型３３に設けた封止樹脂注入口から、上金型３２と下金型３３とによって囲まれた領域内に封止樹脂を注入し、封止金型を２００〜２５０[℃]に加熱することにより、熱硬化性の封止樹脂を硬化させる。そして、封止金型から封止された半導体装置を搬出して、封止樹脂から突出した第１のリードおよび第２のリードを成形する。   Next, as shown in FIG. 11 (b), the sealing resin injection port provided in the upper mold 32 or the lower mold 33 is sealed in a region surrounded by the upper mold 32 and the lower mold 33. A thermosetting sealing resin is cured by injecting a stop resin and heating the sealing mold to 200 to 250 [° C.]. Then, the semiconductor device sealed from the sealing mold is taken out, and the first lead and the second lead protruding from the sealing resin are formed.

次に、半導体装置の製造方法の第２の実施形態について説明する。なお、前述した半導体装置の製造方法の第１の実施形態と同一の内容については省略し、同一の符号には同一の符号を付す。   Next, a second embodiment of the semiconductor device manufacturing method will be described. Note that the same contents as those of the first embodiment of the semiconductor device manufacturing method described above are omitted, and the same reference numerals are given to the same reference numerals.

図１２および図１３は、本実施形態の半導体装置の製造方法の各工程を示す断面図である。
まず、図１２（ａ）に示すように、上金型３２、下金型３３および上金型３２と下金型３３との間に設けられた中間金型３４を備えた封止金型を用意する。 12 and 13 are cross-sectional views showing the respective steps of the semiconductor device manufacturing method of the present embodiment.
First, as shown in FIG. 12A, a sealing mold including an upper mold 32, a lower mold 33, and an intermediate mold 34 provided between the upper mold 32 and the lower mold 33 is used. prepare.

次に、第１のリードフレームに設けられた第１のリードと第１の半導体チップの電極とを突起電極により電気的に接続する。
次に、図１２（ｂ）に示すように、第１の半導体チップ１８が接着された第１のリードフレーム１６を下金型３３の上面に載置し、第１のリードフレーム１６の周囲の上面に中間金型３４を載置する。ここで、第１のリードフレーム１６の第１のリードの上面には、中間金型３４と同じ厚みのスペーサー３５が設けられている。 Next, the first lead provided on the first lead frame and the electrode of the first semiconductor chip are electrically connected by the protruding electrode.
Next, as shown in FIG. 12B, the first lead frame 16 to which the first semiconductor chip 18 is bonded is placed on the upper surface of the lower mold 33, and the periphery of the first lead frame 16 is An intermediate mold 34 is placed on the upper surface. Here, a spacer 35 having the same thickness as that of the intermediate mold 34 is provided on the upper surface of the first lead of the first lead frame 16.

次に、図１２（ｃ）に示すように、中間金型３４の上面に、第２の半導体チップ２４が接着された第２のリードフレーム２２を中間金型３４の上面に載置する。
次に、図１３（ａ）に示すように、第２のリードフレーム２２の上方から、カシメピン３６が設けられた上金型３２を下降させて、上金型３２の周囲を第２のリードフレーム２２の上面に接触させる。ここで、カシメピン３６はスペーサ３５と垂直方向で同じ位置に設けられているので、スペーサー３５とカシメピン３６とにより第２のリードフレーム２２を挟むことができる。 Next, as shown in FIG. 12C, the second lead frame 22 to which the second semiconductor chip 24 is bonded is placed on the upper surface of the intermediate mold 34.
Next, as shown in FIG. 13A, the upper die 32 provided with the crimping pin 36 is lowered from above the second lead frame 22, and the second lead frame is surrounded by the upper die 32. 22 is brought into contact with the upper surface. Here, since the caulking pin 36 is provided at the same position in the vertical direction as the spacer 35, the second lead frame 22 can be sandwiched between the spacer 35 and the caulking pin 36.

次に、図１３（ｂ）に示すように、上金型３２または下金型３３に設けた封止樹脂注入口（図示せず）から、上金型３２と下金型３３によって囲まれた領域内に封止樹脂を注入し、封止金型を２００〜２５０[℃]に加熱することにより、熱硬化性の封止樹脂を硬化させる。そして、封止金型から封止された半導体装置を搬出して、封止樹脂から突出した第１の外部電極および第２の外部電極を成形する。   Next, as shown in FIG. 13B, the upper mold 32 and the lower mold 33 are surrounded by a sealing resin injection port (not shown) provided in the upper mold 32 or the lower mold 33. The thermosetting sealing resin is cured by injecting the sealing resin into the region and heating the sealing mold to 200 to 250 [° C.]. Then, the semiconductor device sealed from the sealing mold is taken out, and the first external electrode and the second external electrode protruding from the sealing resin are formed.

本実施形態の半導体装置の製造方法は、上金型にカシメピンを設けて、上金型と下金型とを合わせることによって、カシメピンとスペーサーとにより第２のリードフレームの第２のリードの金属細線が接合した部分近傍をかしめて、第２のリードフレームのそり等が発生しないようにしているので、第２のリードと第２の金属細線との接合性が向上する。   In the method of manufacturing a semiconductor device according to the present embodiment, a caulking pin is provided in an upper die, and the upper die and the lower die are combined to form a metal of the second lead of the second lead frame by the caulking pin and the spacer. Since the second lead frame is warped in the vicinity of the portion where the thin wire is joined, the joining property between the second lead and the second metal thin wire is improved.

本発明の一実施形態の半導体装置を示す図The figure which shows the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置の製造工程を示す斜視図The perspective view which shows the manufacturing process of the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置を示す図The figure which shows the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置を示す図The figure which shows the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置を示す図The figure which shows the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置を示す図The figure which shows the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置を示す図The figure which shows the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置を示す図The figure which shows the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置を示す図The figure which shows the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置の製造方法の各工程を示す断面図Sectional drawing which shows each process of the manufacturing method of the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置の製造方法の各工程を示す断面図Sectional drawing which shows each process of the manufacturing method of the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置の製造方法の各工程を示す断面図Sectional drawing which shows each process of the manufacturing method of the semiconductor device of one Embodiment of this invention 本発明の一実施形態の半導体装置の製造方法の各工程を示す断面図Sectional drawing which shows each process of the manufacturing method of the semiconductor device of one Embodiment of this invention 従来の半導体装置を示す図The figure which shows the conventional semiconductor device 従来の半導体装置を示す図The figure which shows the conventional semiconductor device

符号の説明Explanation of symbols

１ リードフレーム
２ ダイパッド
３ 半導体チップ
４ 電極
５ リード
６ 金属細線
７ 封止樹脂
８ リードフレーム
９ ダイパッド
１０ 第１の半導体チップ
１１ 電極
１２ 第２の半導体チップ
１３ リード
１４ 金属細線
１５ 封止樹脂
１６ 第１のリードフレーム
１７ ダイパッド
１８ 第１の半導体チップ
１９ 電極
２０ 第１の金属細線
２１ 第１の封止樹脂
２２ 第２のリードフレーム
２３ 第２のダイパッド
２４ 第２の半導体チップ
２５ 電極
２６ 第２の金属細線
２７ 第２の封止樹脂
２８ 第１の外部電極
２９ 第２の外部電極
３０ コイル
３１ シールド
３２ 上金型
３３ 下金型
３４ 中間金型
３５ スペーサー
３６ カシメピン
３７ フレーム DESCRIPTION OF SYMBOLS 1 Lead frame 2 Die pad 3 Semiconductor chip 4 Electrode 5 Lead 6 Metal fine wire 7 Sealing resin 8 Lead frame 9 Die pad 10 First semiconductor chip 11 Electrode 12 Second semiconductor chip 13 Lead 14 Metal fine wire 15 Sealing resin 16 1st Lead frame 17 die pad 18 first semiconductor chip 19 electrode 20 first metal fine wire 21 first sealing resin 22 second lead frame 23 second die pad 24 second semiconductor chip 25 electrode 26 second metal Thin wire 27 Second sealing resin 28 First external electrode 29 Second external electrode 30 Coil 31 Shield 32 Upper mold 33 Lower mold 34 Intermediate mold 35 Spacer 36 Caulking pin 37 Frame

Claims (1)

ダイパッドの上面と第１の半導体チップの裏面とが接着され、前記第１の半導体チップの電極と第１のリードとが第１の金属細線により電気的に接続され、前記第１の半導体チップの上方に、コイルが設けられ、前記コイルの内方部と第２のリードとが前記コイルの一部を介して接続され、前記コイルの中央領域が周辺領域よりも高くなっており、前記第１の半導体チップ、前記第１の金属細線、前記第１のリードの上面および前記第２のリードの上面が、封止樹脂により封止されていることを特徴とする樹脂封止型半導体装置。 The upper surface of the die pad and the back surface of the first semiconductor chip are bonded, the electrode of the first semiconductor chip and the first lead are electrically connected by a first thin metal wire, A coil is provided above, the inner portion of the coil and the second lead are connected via a part of the coil, and the central region of the coil is higher than the peripheral region, the first A resin-encapsulated semiconductor device, wherein the semiconductor chip, the first metal thin wire, the upper surface of the first lead, and the upper surface of the second lead are encapsulated with an encapsulating resin.
JP2008029857A 2008-02-12 2008-02-12 Resin-sealed semiconductor device Expired - Fee Related JP4818287B2 (en)

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JPH01278052A (en) * 1988-04-30 1989-11-08 Nec Corp Resin sealed semiconductor device
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