JP4814034B2 - Electron beam drawing device - Google Patents

Description

  The present invention relates to an electron beam drawing apparatus, and more particularly to an electron beam drawing apparatus that creates (generates) a master disk of an information recording medium by irradiating the master disk of the information recording medium on a rotational drive mechanism.

  In recent years, with the miniaturization of information recording media such as magnetic disks and optical disks, an electron beam drawing apparatus (EB mastering apparatus; EBR) is used to form pits (information pits) on the master (master). There is a case. In this case, the rotary stage on which the master is placed is rotated by a motor, while the electron beam (EB) is irradiated to the master with a certain intensity, the rotary stage is moved in the radial direction, and the electron beam is Block (blanking) at a predetermined timing. Thereby, a pit pattern shown in FIG. 6A or 6B is formed on the master according to the irradiation point of the electron beam. FIG. 6A shows an example of a master disk such as an optical disk on which concentric (or spiral) pit patterns are formed. FIG. 6B shows an example of a master disk such as a magnetic disk on which an arc-shaped pit pattern is formed in the radial direction.

  In the present invention, a magnetic disk pattern as shown in FIG. 6B is drawn by an electron beam drawing apparatus. Drawing the pattern as shown in FIG. 6 requires an alignment pit creation technique for aligning pits in the radial direction of the master by forming pits at the same circumferential position on the master, but the electron beam writing device Then there are the following problems. In this electron beam lithography system, when the rotation speed of the motor is constant and the region (irradiation point) irradiated with the electron beam on the master is moved from the inner periphery side to the outer periphery side, the irradiation point becomes closer to the outer periphery side. The linear velocity (speed at which the irradiation point moves on the master) gradually increases. For this reason, the energy per unit area given to the master by the irradiation point of the electron beam becomes smaller toward the outer peripheral side. On the other hand, an electron beam lithography apparatus can only irradiate an electron beam with a constant intensity (it cannot change or intensify). For the above reasons, there is a problem that the width of the pit formed by the irradiation point differs between the inner peripheral side and the outer peripheral side of the master.

  Therefore, the present inventor has previously proposed an electron beam drawing apparatus including a control signal generating circuit shown in FIG. 7 (see Patent Document 1). In FIG. 7, the first clock generating circuit 53 generates and outputs a write clock using a first DDS (Direct Digital synthesizer) circuit 57 based on the reference clock Fr from the reference clock generating circuit 52, and this The write clock is counted by the counter 552 of the first frequency update circuit 55. In the comparison circuit 553, when the count value coincides with the setting value of the pulse number N (n) setting register 554, the setting value of the next frequency data D (n + 1) setting register 551 is set to the frequency setting data (hereinafter referred to as frequency data). That is, D is set in the first DDS circuit 57 as D, and the frequency of the write clock is updated. Further, the control processor 59 loads the next frequency setting data into the next frequency data D (n + 1) setting register 551. The second clock generating circuit 54 has the same configuration as the first clock generating circuit 53, generates and outputs a spindle clock (motor clock), and counts this to update its frequency. Although the control processor 59 is shown as a part of the first clock generation circuit 53 in FIG. 7B, only one control processor 59 is provided as common to the first and second clock generation circuits 53 and 54. .

According to the technique described in Patent Document 1, when the irradiation point of the electron beam moves from the inner periphery side to the outer periphery side of the master, the write clock frequency that becomes the reference for the exposure timing is increased as it goes to the outer periphery side. The spindle clock frequency is also lowered by synchronizing the spindle clock with the write clock. Therefore, the rotation speed of the motor gradually decreases as the irradiation point of the electron beam goes to the outer peripheral side. As a result, the linear velocity of the irradiation point becomes constant on the inner peripheral side and the outer peripheral side, so that the electron beam has a constant strong intensity. Even if irradiated, the energy per unit area applied to the master from the irradiation point can be kept constant, and pits having the same width can be formed over the entire surface of the master. Further, the write clock and the spindle clock are synchronized by counting them. Therefore, the cycle for turning on / off the blocking of the electron beam can be changed in accordance with the change in the rotation speed of the motor. As a result, even if the rotational speed of the motor changes, the position in the circumferential direction for turning on / off the blocking of the electron beam can be made constant, so that pits can be formed at the same position in the circumferential direction on the master disk. Pits can be aligned in the radial direction of the master.
JP 2006-119484 A

  According to the study of the present inventor, it has been found that the technique described in Patent Document 1 has the following problems.

  The output clocks (write clock and spindle clock) of the first and second clock generation circuits 53 and 54 are synchronized by counting the output clocks (that is, two asynchronous clocks) themselves. Therefore, it is impossible to eliminate the possibility of an error caused by a timing shift that always exists between asynchronous output clocks, and the first and second clocks cannot be completely synchronized. is there.

  In addition, commercially available DDS ICs used as the DDS circuits 57 and 58 have a slight delay from when the frequency setting data is set according to the frequency setting command from the control processor 59 until the frequency of the output clock is switched ( Hereinafter, response delay). Response delay time varies and cannot be predicted. The response delay time is determined depending on the number of reference clocks Fr and corresponds to several clocks when converted to an output clock. Therefore, if the response delay is ignored, a slight error occurs in the timing between the write clock and the spindle clock, and the output clock including this error is counted by the counter 552 to determine the next frequency switching timing. Become. As a result, there is a problem that errors are accumulated (accumulated in the same direction) by repeating switching, and a large error is finally generated.

  For this reason, actually, the control processor 59 measures the period of the output clock using a timer circuit (not shown), and loads the next frequency setting data in advance at the timing when the response delay time is expected. As a result, there is a problem that the circuit becomes large-scaled by the timer circuit and the control becomes complicated. The response delay time includes a delay time by the filter circuits included in the DDS circuits 57 and 58 in addition to the time determined by the number of reference clocks Fr. If the delay due to the filter circuit is also corrected, there is a problem that the circuit becomes larger (complex).

  Furthermore, even if various corrections as described above are performed, the reference clock and the output clock are basically asynchronous, and thus an error in the range of ± 1 reference clock is inevitable. For this reason, there is a problem that there is a possibility that this error is accumulated by repeating the switching.

  Furthermore, the frequency switching timing is independent (asynchronous) in each of the write clock and the spindle clock. For this reason, the switching timing is relatively shifted and integrated. Here, since the control processor 59 is common to the first and second clock circuits 53 and 54, the coincidence signals (interrupt signals) from the comparison circuit 553 reach the control processor 59 separately at different timings. . For this reason, if the frequency calculation is performed a plurality of times per rotation in order to increase the accuracy of the frequency calculation and avoid the integration, the control program operating on the control processor 59 becomes extremely complicated. For this reason, there is a problem that the frequency calculation cannot be performed a plurality of times per one rotation.

  The present invention relates to an electron beam drawing apparatus for creating an information recording medium master by irradiating an information recording medium master on a rotational drive mechanism, which is realized by a simpler control signal creation circuit and control program. An object of the present invention is to provide an electron beam drawing apparatus capable of setting a clock frequency with high accuracy.

  The electron beam drawing apparatus of the present invention exposes a master disk of a recording medium by irradiating the master disk placed on the rotational drive mechanism with an electron beam. The electron beam drawing apparatus of the present invention has a first clock generation circuit for generating a write clock having a first clock frequency based on a reference clock and serving as a reference for exposure timing, and a first clock generation circuit based on the reference clock. As a common clock to a second clock generating circuit that has a 2-clock frequency and generates a spindle clock that serves as a reference for the rotational speed of the motor included in the rotation drive mechanism, and the first and second clock generating circuits When the reference clock generation circuit that supplies the reference clock and the first and second clock generation circuits are provided in common, the number of the reference clocks is counted and the count value becomes a predetermined value, The first and second clock frequencies in the first and second clock generation circuits are updated. And a frequency update circuit.

  Preferably, in one embodiment of the present invention, the first clock generating circuit generates the write clock using a first direct digital synthesizer circuit, and the second clock generating circuit is a second direct digital synthesizer circuit. Is used to create the spindle clock.

  Preferably, in one embodiment of the present invention, the frequency update circuit updates the frequency for each predetermined number of reference clocks, and updates the first and second clock frequencies within a period of one rotation of the motor. Perform multiple times.

  Preferably, in an embodiment of the present invention, the electron beam drawing apparatus further includes an N frequency dividing circuit that is provided in a preceding stage of the frequency update circuit and divides the reference clock by N. The frequency update circuit counts the number of reference clocks divided by N by the N divider circuit. Each of the first and second clock generation circuits includes an internal N divider circuit that divides the supplied reference clock by N, and operates with the reference clock divided by N by the internal N divider circuit.

  Preferably, in one embodiment of the present invention, the frequency update circuit counts the number of the reference clocks, and the first clock frequency to be updated when the count value in the counter reaches a predetermined value. Write clock frequency data setting register for outputting frequency setting data corresponding to the first clock generation circuit, and a frequency corresponding to the second clock frequency to be updated when the count value in the counter reaches a predetermined value A spindle clock frequency data setting register for outputting setting data to the second clock generating circuit.

  According to the electron beam drawing apparatus of the present invention, the number of reference clocks that are common reference clocks to the first and second clock generation circuits is counted, and when the predetermined number is counted, the first and second clock generations are performed. The first and second clock frequencies in the circuit are simultaneously switched (ie, updated) to their next frequency. That is, in the present invention, the reference clock is counted instead of the output clocks (that is, the write clock and the spindle clock) of the first and second clock generation circuits themselves to determine the frequency switching timing. Two clocks (write clock and spindle clock) are switched at the same timing. Therefore, without adding a complicated switching timing prediction circuit, the possibility of an error due to the output clock can be eliminated, and the first and second clocks can be synchronized.

  Furthermore, since the reference clock is counted, an error in the range of ± 1 reference clock does not occur. Therefore, it is possible to eliminate the accumulation of the error even if the frequency switching is repeated.

  Furthermore, since the first and second clocks are switched (synchronized) at the same timing, the switching timing does not relatively shift between them. Therefore, it is possible to prevent errors from being accumulated between the two due to the switching timing. Further, since the switching timing is common, the processing can be simplified as compared with the case where the timing is separate, and for example, frequency calculation can be performed a plurality of times per one rotation.

  In the present invention, since only the reference clock is counted, not the output clock which is a different signal, the counters (and other circuits) in the first and second clock generating circuits can be shared. Therefore, it is possible to prevent the circuit from becoming large and complicated.

  According to an embodiment of the present invention, the first and second clock generation circuits generate a write clock and a spindle clock by each direct digital synthesizer circuit (hereinafter referred to as a DDS circuit). Thus, the first and second clock generation circuits can be configured using a commercially available LSI (LSI for DDS circuit) without newly designing the first and second clock generation circuits.

  In this case, since the reference clock is counted as described above, even if a commercially available DDS IC is used as the DDS circuit of the first and second clock generation circuits, the response delay time of the DDS IC is affected. There is nothing. Accordingly, it is possible to eliminate the possibility of a slight error between the first and second clocks resulting from this, and it is possible to prevent a large error from finally occurring due to error integration. Further, since it is not necessary to load the next frequency setting data at the timing when the response delay time is anticipated, it is possible to avoid complicated control and a large circuit. Furthermore, since it is not necessary to consider the delay caused by the filter circuit included in the DDS circuit, it is possible to avoid further increasing the scale of the circuit in order to eliminate this delay.

  According to an embodiment of the present invention, the frequency is updated for each predetermined number of reference clocks, the first and second clock frequencies are updated a plurality of times within one rotation period of the motor, and the resolution of the DDS circuit is changed. First and second clock frequencies to be updated are calculated using the generated quantization error. As a result, the first and second clocks can be effectively changed continuously by switching the frequency of the first and second clocks more times. As a result, for example, by rotating the spindle clock smoothly, the rotation speed of the motor can be controlled without deteriorating the rotation accuracy.

  According to an embodiment of the present invention, the frequency update circuit counts the number of reference clocks divided by N by the N divider circuit, and the first and second clock generating circuits divide by N by the internal N divider circuit. It operates with the specified reference clock. Thus, the first and second clock generation circuits can be configured using a commercially available LSI (DDS circuit) that operates at an extremely high frequency.

  According to one embodiment of the present invention, when the comparison result between the reference clock count value and the set value matches, the first and second clock frequencies to be updated are output to the first and second clock generation circuits. To do. Thus, both the write clock and the spindle clock can be switched at the same timing with a preset count value.

  FIG. 1 is a block diagram showing an example of an electron beam drawing apparatus of the present invention. In particular, FIG. 1A shows an outline of the cross-sectional structure of the electron beam lithography apparatus of the present invention, and FIG.

  The electron beam drawing apparatus has a well-known configuration and includes an electron optical system 100 and a stage system 200 as shown in FIG. The electron optical system 100 includes an electron gun 101 that generates an electron beam, an electron optical system (100) that focuses the electron beam on the master 300, a blanker 102 that performs on / off of the electron beam, and a main surface of the master 300. It comprises a deflection control system 103 that changes the position of the irradiated electron beam. The stage system 200 is provided in a vacuum chamber 201 provided in the lower part of the electron optical system 100, and includes a linear motion (direct drive or linear drive) stage 203 and a rotary stage (rotary drive mechanism) 202 mounted thereon. It consists of. As shown in FIG. 1B, the rotary stage 202 includes a turntable 204 on which the master 300 is placed and a motor (spindle motor or rotary motor) 207.

  As is well known, the electron beam lithography apparatus exposes the master 300 of the recording medium by irradiating the master 300 placed on the rotary stage 202 (the turntable 204) rotated by the motor 207 with an electron beam. In brief, while the master 300 coated with resist is fixed on the turntable 204, the electron beam is intermittently irradiated from the electron optical system 100 to the master 300 by the blanker 102 while rotating the motor 207. Is done. At the same time, the entire rotary stage 202 including the motor 207 is moved in the radial direction (left or right in FIG. 1A) by the linear motion stage 203. Thus, as shown in FIG. 6, concentric or arc-shaped pits are drawn on the entire surface of the recording area.

  As is well known, the positioning error of the linear motion stage 203 and the rotation unevenness of the motor 207 are corrected by the deflection control system 103 to enable drawing with higher accuracy. Since the deflection control system 103 is not directly related to the present invention, its description is omitted. Since the deflection control is open control, it is necessary to improve the positioning of the linear motion stage 203 and the rotation accuracy of the motor 207 as much as possible. Therefore, as is well known, the motor 207 supported by the air bearing (air spindle) 206 is vacuumed as shown in FIG. After being sealed by a seal 205 and a magnetic seal (not shown), it is provided in the vacuum chamber 201.

  The rotation control of the motor 207 is performed by the PLL control circuit 210. For this purpose, a rotary encoder 208 and an encoder data detector 209 are attached to the motor 207. The rotary encoder 208 generates a pulse train proportional to the number of revolutions of the motor 207, for example, hundreds to thousands of pulse trains per revolution. The encoder data detector 209 detects the pulse train generated by the rotary encoder 208, creates an encoder signal based on the pulse train, and inputs the encoder signal to the PLL control circuit 210. The PLL control circuit 210 feedback-controls the motor 207 (a drive circuit thereof, not shown) so that the encoder signal matches the spindle clock. Therefore, when the frequency of the spindle clock is increased, the rotational speed of the motor 207 is increased, and when the frequency is decreased, the rotational speed of the motor 207 is also decreased.

  FIG. 2 is a block diagram showing an example of a control signal generation circuit of the electron beam drawing apparatus of the present invention. In particular, FIG. 2A shows the overall configuration of the control signal generation circuit, and FIG. 2B mainly shows the configuration of the first and second clock generation circuits.

  The control signal generation circuit includes a formatter 1 that generates data for actually exposing the master 300 and a spindle control circuit 6 that generates a spindle clock. The formatter 1 includes a reference clock generation circuit 2, first and second clock generation circuits 3 and 4, and a data generator 5.

  The reference clock generating circuit 2 supplies a common reference clock (reference clock signal) Fr to the first and second clock generating circuits 3 and 4. The reference clock Fr is a reference clock for generating an output clock by the first and second DDS circuits 7 and 8, as will be described later. The reference clock Fr is also supplied to the frequency update circuit 9 in order to count the number thereof. The reference clock generation circuit 2 is composed of, for example, a known oscillation circuit, and generates and outputs a clock having a frequency of about 180 MHz, for example.

  The first clock generation circuit 3 generates a write clock (write clock signal) having a first clock frequency and serving as a reference for exposure timing based on the reference clock Fr. The write clock is supplied to the data generator 5. The first clock generation circuit 3 mainly uses the first DDS circuit 7 to generate a write clock.

  The data generator 5 creates data (blanker control data) for actually exposing the master 300 based on the drawing data using the write clock, and controls the blanker 102 (a blanker control circuit). The drawing data is given (inputted) to the data generator 5 in advance, for example. When the blanker 102 performs on / off control of the electron beam according to the blanker control data, information pits corresponding to the data are created on the main surface of the master 300. For example, while the electron beam is on, the electron beam is irradiated on the master 300, and pits corresponding to the electron beam are formed. Since the write clock and the spindle clock are synchronized, the blanker control data generated from the write clock is also synchronized with the spindle clock.

  The second clock generation circuit 4 generates a spindle clock (spindle clock signal) having a second clock frequency different from the first clock frequency and serving as a reference for the rotation speed of the motor 207 based on the reference clock Fr. The spindle clock is supplied to the spindle control circuit 6. The second clock generation circuit 4 mainly uses the second DDS circuit 8 to generate a spindle clock.

  The spindle control circuit 6 creates data for controlling the number of revolutions of the motor 207 using the spindle clock. By controlling the rotation stage (rotation drive mechanism) 202 (motor 207) in accordance with this data, the rotation stage 202 on which the master 300 is placed synchronizes with the on / off of the electron beam based on the write clock in a predetermined manner. It rotates at the rotation speed.

  The frequency update circuit 9 counts the number of reference clocks Fr supplied to the first and second clock generation circuits 3 and 4, and when the count value reaches a predetermined value, the first and second clocks The first and second clock frequencies in the creation circuits 3 and 4 are updated. That is, the frequencies of the output clocks (write clock and spindle clock) of the first and second clock generation circuits 3 and 4 are changed.

  The frequency update circuit 9 is provided in common to the first and second clock generation circuits 3 and 4. That is, the first clock generation circuit 3 includes a first DDS circuit 7 and a frequency update circuit 9, and the second clock generation circuit 4 includes a second DDS circuit 8 and a frequency update circuit 9. Therefore, the formatter 1 includes at least two DDS circuits 7 and 8 and one frequency update circuit 9. As can be seen from the comparison between FIG. 2B and FIG. 7A, according to the present invention, the circuit for one frequency update circuit 9 is reduced.

  The frequency update circuit 9 includes a counter 91, a comparison circuit 92, a pulse number N (n) setting register (hereinafter referred to as a pulse number register) 93, which is a clock number setting register for setting the number of reference clocks Fr, and a write clock. Write clock next frequency data setting register (hereinafter also referred to as write clock register) 94 for setting frequency setting data Dw, and spindle clock next frequency data setting register (hereinafter also referred to as spindle clock register) for setting spindle clock frequency setting data Dsp. 95) and a control processor 96. In the following description, the number of reference clocks Fr that are currently processed is expressed as Fr (n), the number of reference clocks Fr that are processed next is expressed as Fr (n + 1), and frequency setting data Dw and Similarly, Dsp is also expressed.

  The pulse number register 93 is set with the number Fr (n) of the reference clocks Fr corresponding to the timing in order to determine the switching timing of the first and second clock frequencies. Corresponding to this, Dw (n) and Dsp (n) are already set in the first and second DDS circuits 7 and 8.

  The write clock register 94 is a register for setting the write clock frequency (first clock frequency) setting data Dw of the next step. The first clock frequency next frequency setting data (frequency setting data used at the next switching). ) Dw (n + 1) is set. The spindle clock register 95 is also a register for setting the spindle clock frequency (second clock frequency) setting data Dsp of the next step, and is set with the next frequency setting data Dsp (n + 1) of the second clock frequency. These settings are made each time the frequency is switched.

  The counter 91 counts the number of supplied reference clocks Fr. The comparison circuit 92 compares the count value in the counter 91 with the set value Fr (n) in the pulse number register 93. When the comparison results match, the following processing is performed.

  First, the comparison circuit 92 transmits a load signal to the two next frequency data setting registers 94 and 95, transmits a clear signal to the counter 91, and transmits an interrupt signal (interrupt signal) to the control processor 96. These signals may be the same signal. The clock frequency output from the DDS circuit is changed to one corresponding to Dw (n + 1) and Dsp (n + 1) by the load signal, the counter 91 is cleared by the clear signal, and the updated frequency setting data Dw (n + 1) and The count of the reference clock Fr is newly started in the first and second frequency periods corresponding to Dsp (n + 1).

  On the other hand, the control processor 96 calculates Fr (n + 1), Dw (n + 2), and Dsp (n + 2) by an operation described later, and transmits them to the pulse number register 93 and the next frequency data setting registers 94 and 95. The pulse number register 93 stores these in the storage area as predetermined data. The value of Fr (n + 1) is selected so that these operations are completed sufficiently earlier than the required timing. Note that the values of Fr (n), Dw (n), and Dsp in the case of n = 0 (initial value), 1 and 2 can be easily known and are set in advance.

When the frequency setting data Dw and Dsp are input as described above, the first and second DDS circuits 7 and 8 are based on the frequency setting data D (Dw and Dsp) and the reference clock Fr, as is well known. ,
Fo = Fr × (D / 2 ³² ) (1),
A clock (output clock) having a frequency Fo determined by is output. Here, Fr is 100 MHz, for example, and D is 32 bit data, for example. In this case, the frequency resolution (frequency change per 1 bit) is 0.23 Hz, and an extremely high resolution can be obtained. The maximum frequency of Fo is limited to about 1/3 of Fr. In this case, the maximum frequency is about 30 MHz.

  The first and second DDS circuits 7 and 8 include an interface for setting a frequency from the control processor 96. Using this, the frequency setting data Dw and Dsp are received from the write clock register 94 and the spindle clock register 95.

Here, for example, the number of write clocks per rotation of the motor 207 is Nw, and the number of spindle clocks is Nsp. When the drawing point is present at a radius R (mm) at that time, the rotational speed f (Hz) of the motor 207 (spindle) for obtaining a desired rotational speed (circumferential speed or linear speed) V (mm / s) )
f = V / 2πR (2),
It is. Therefore, the frequency Fsp of the spindle clock is Fsp = f × Nsp (3),
The spindle clock frequency setting data Dsp is set so that Similarly, the frequency Fw of the write clock is Fw = f × Nw (4),
The write clock frequency setting data Dw is set so that

  As described above, the frequency switching timing, the timing at which the comparison result of the comparison circuit 92 matches next, the number of write clocks and spindle clocks (output clocks) output between this time and the next interrupt, and what phase It is possible to know exactly whether the condition has been reached. The phase state corresponds to a fraction of the output clock. Actually, there is a delay time of the filter circuit described above, but since this time is constant, no error is accumulated in the next step. Therefore, in practice, the delay time of the filter circuit can be ignored. Therefore, for example, based on the number of reference clocks Fr for one turn of the motor 207, the necessary frequency setting data D (Dw or Dsp) is calculated by calculating the number of clocks that must be output during that time, including the fraction. Can be calculated. In addition, since the synchronization timing of the write clock and the spindle clock can be changed by a minute time, as shown in the servo pattern of the magnetic disk in FIG. 6B, the entire recording area (the entire radial direction) is obtained. It is possible to accurately draw the arc-shaped alignment pits (pits having the same pit edge positions in the circumferential direction).

  As described above, in the present invention, since the frequencies of the write clock and the spindle clock are switched based on the count value of the reference clock Fr, they can be synchronized. Therefore, it is possible to eliminate an error caused by the asynchronousness of the write clock and the spindle clock, and to prevent the errors from being integrated. In FIG. 7, since the frequencies are switched based on the count values of the output clocks (write clock and spindle clock) of the first and second DDS circuits 57 and 58, the output clocks are completely synchronized. I can't.

  In the present invention, since the reference clock Fr is counted, the frequency setting data D can be set in the DDS circuits 7 and 8 in units of one clock. Unlike the write clock and the spindle clock, the reference clock Fr is stable and the timing thereof can be predicted, so that stable frequency control can be performed. In FIG. 7, since the frequency setting data D is set in the first and second DDS circuits 7 and 8 in units of one clock of the write clock and the spindle clock, the setting timing (accordingly, the frequency) It is unavoidable that the timing of switching) fluctuates due to these clocks.

  In the present invention, since the reference clock Fr is counted, the counter 91 and the like can be shared. Therefore, since the interrupt to the control processor 96 based on the count value of the reference clock Fr is generated only from one frequency update circuit 9, the processing (processing program) in the control processor 96 may be simplified. it can. In FIG. 7, since the output clocks of the first and second DDS circuits 57 and 58 are counted, the counter 552 and the like cannot be shared, and the interrupt to the control processor 96 is complicated.

  FIG. 3 is a block diagram showing another example of the control signal generation circuit of the electron beam lithography apparatus of the present invention. In this example, the configuration of the frequency update circuit 9 is simplified, and the first and second clock frequencies are updated a plurality of times within one rotation period of the motor 207. The frequency update circuit 9 has the same configuration as the frequency update circuit 9 of FIG. 2 except that the comparison circuit 92 and the pulse number N (n) setting register 93 are omitted.

  In the frequency update circuit 9, the counter 91 counts the number of supplied reference clocks Fr, and outputs a clear signal and an interrupt signal when the count value reaches a predetermined value (counts up). In response to the clear signal, the counter 91 is cleared. The control processor 96 that has received the interrupt signal causes the write clock register 94 to output the frequency setting data Dw (n + 1) to the first clock generation circuit 3, and the spindle clock register 95 generates the frequency setting data Dsp (n + 1) to the second clock. Output to circuit 4. The control processor 96 that has received the interrupt signal transmits (loads) Dw (n + 2) and Dsp (n + 2) to the write clock register 94 and the spindle clock register 95 as the next frequency setting data. Further, the control processor 96 calculates Dw (n + 3) and Dsp (n + 3) by calculation.

  According to the example of FIG. 3, the counter 91 is simplified so as to generate a count-up output for each predetermined number of reference clocks Fr, that is, for each predetermined (constant) number of pulses. Thereby, the comparison circuit 92 and the like can be reduced, and all frequencies can be updated every predetermined time. Thereby, the process (processing program) in the control processor 96 can also be simplified. Here, the predetermined time only needs to be longer than the time when the calculation of all frequencies is finished, and is determined by the calculation processing speed of the control processor 96. Normally, it can be completed in 1 ms or less.

  Therefore, in the example of FIG. 3, the count-up value of the counter 91 is set sufficiently shorter than the cycle of one rotation of the motor 207 (for example, 1 / N, N is an integer of 10 or less, for example). As a result, the first and second clock frequencies are updated a plurality of times (N times) within one rotation period of the motor 207. As a result, the frequency of the write clock and the spindle clock can be switched more smoothly (effectively continuously).

Further, in the example of FIG. 3, the control processor 96 calculates the first and second clock frequencies to be updated in consideration of the quantization error caused by the resolution of the first and second DDS circuits 7 and 8. That is, the resolutions of the first and second DDS circuits 7 and 8 are finite, and in a 32-bit DDS circuit, a fraction less than (1/2) ³² is an error. This is because a quantization error occurs between the write clock frequency Fw and the frequency setting data Dw. When Fw is slightly higher than the expression (4), the alignment pits gradually shift to the upstream side, and when Fw is lower, the alignment pits shift to the downstream side. However, the degree of shift can be predicted, and the pits can be aligned in an arc shape by adjusting the frequency (that is, frequency setting data Dw).

  Therefore, in the example of FIG. 3, the control processor 96 performs double precision calculation (64 bits) on the frequency setting data Dw (n). Thereby, the error is estimated, and the estimated error is transferred to the next frequency setting data Dw (n + 1). As a result, it is possible to compensate for the resolution error of the first and second DDS circuits 7 and 8 and to output a more accurate output clock.

  FIG. 4 is a block diagram showing still another example of the control signal generation circuit of the electron beam drawing apparatus of the present invention. In this example, the electron beam drawing apparatus includes the N frequency dividing circuit 10, thereby operating the control signal generating circuit using the high-speed (high frequency) reference clock Fr. The control signal generation circuit in FIG. 4 has the same configuration as the control signal generation circuit in FIG. 2 except for the N frequency divider circuit 10 (and the internal N frequency divider circuits 73 and 83, and the control circuits 72 and 82).

  The N divider circuit 10 is provided before the input of the reference clock Fr of the frequency update circuit 9, and divides the reference clock Fr by N (the frequency is set to 1 / N). The frequency of the reference clock Fr is, for example, several hundred MHz to 1 GHz, and N is, for example, 8 (or an integer such as 4, 16). The frequency update circuit 9 counts the number of reference clocks (N reference clocks) Fr ′ divided by N by the N divider circuit 10. That is, by dividing the reference clock Fr by N, the counter 91 can count the N reference clock Fr ′. As a result, the frequency update circuit 9 can be operated using the N reference clock Fr ′ having a relatively low frequency instead of the high frequency reference clock Fr as a reference clock.

  In the first DDS circuit 7 in the first clock generating circuit 3, the clock generating circuit 71 is operated by the supplied reference clock Fr. As a result, the write clock can be created using the high-frequency reference clock Fr as it is. On the other hand, the first DDS circuit 7 in the first clock generating circuit 3 includes an internal N frequency dividing circuit 73 that divides the supplied reference clock Fr by N. Internal N divider circuit 73 has the same configuration as N divider circuit 10, and the value of N in internal N divider circuit 73 is the same as the value of N in N divider circuit 10. As a result, the control circuit 72 can be operated using the N reference clock Fr ′ having a relatively low frequency instead of the high frequency reference clock Fr as a reference clock, and can be synchronized with the frequency update circuit 9. . The same applies to the second DDS circuit 8 in the second clock generation circuit 4.

  According to the above, since a very high frequency can be used as the reference clock Fr, a commercially available high-speed DDS circuit IC that operates at the frequency can be used as the clock generation circuits 71 and 81. In the circuit of FIG. 4, the initial phase of the write clock and the spindle clock output from the clock generation circuits 71 and 81 varies within the range of the N reference clock Fr ′, so that an initial error occurs. However, since this initial error is not integrated, it can be ignored in practice.

  In the control signal generating circuit of FIG. 4, the internal N frequency dividing circuits 73 and 83 may be omitted, and the N reference clock Fr ′ from the N frequency dividing circuit 10 may be used instead. As a result, the internal N frequency dividing circuits 73 and 83 can be reduced.

  FIG. 5 is a block diagram showing still another example of the control signal generation circuit of the electron beam lithography apparatus of the present invention. In this example, the electron beam drawing apparatus includes a third clock generation circuit, and thereby generates a stage clock based on the reference clock Fr. The third clock generation circuit includes a third DDS circuit 11 and a frequency update circuit 9. Therefore, the frequency update circuit 9 is not only common to the first and second clock generation circuits 3 and 4, but is also provided in common to the third clock generation circuit. The control signal generating circuit of FIG. 5 has the same configuration as the control signal generating circuit of FIG. 2 except for the third clock generating circuit (and the stage clock register 97).

  The reference clock generation circuit 2 supplies the reference clock Fr to the third clock generation circuit. The third clock generation circuit generates a stage clock (stage clock signal) based on the reference clock Fr. The stage clock has a third clock frequency different from the first and second clock frequencies, and serves as a reference for the moving speed in the linear direction (radial direction) of the rotation drive mechanism (rotation stage 202). That is, it becomes a reference for the moving speed of the linear motion stage 203 in a predetermined moving direction (left or right direction in FIG. 1A). The stage clock is supplied to a drive circuit (not shown) for the linear motion stage 203. The drive circuit receives the stage clock, and moves the linear motion stage 203 by (movement amount per clock) × (number of clocks) based on the stage clock.

  The frequency update circuit 9 includes a stage clock next frequency setting data setting register (stage clock register) 97 for setting the stage clock frequency setting data Dst. Since the stage clock register 97 functions in the same manner as the write clock register 94 and the spindle clock register 95, a detailed description thereof is omitted.

  As described above, the same effects as those in the creation of the write clock and the spindle clock can be obtained in the creation of the stage clock. That is, the feed speed (stage clock frequency) of the linear motion stage 203 can be changed in accordance with the change in the rotation speed (spindle clock frequency). Thereby, the moving amount of the linear motion stage 203 per one rotation of the motor 207 can be made constant, and the exposure amount per unit area can be made constant in addition to the constant peripheral speed.

  As can be seen from the above, the features of the embodiment of the present invention are grasped as follows.

(Additional remark 1) In the electron beam drawing apparatus which exposes the original disk of a recording medium by irradiating the original disk mounted on the rotational drive mechanism with an electron beam,
A first clock generating circuit having a first clock frequency based on a reference clock and generating a write clock serving as a reference for exposure timing;
A second clock generating circuit that generates a spindle clock having a second clock frequency based on the reference clock and serving as a reference for the rotational speed of the motor included in the rotation driving mechanism;
A reference clock generating circuit for supplying the reference clock common to the first and second clock generating circuits to the first and second clock generating circuits;
The first and second clock generation circuits are provided in common and the first and second clock generation circuits in the first and second clock generation circuits when the count value reaches a predetermined value when the number of the reference clocks is counted. And a frequency update circuit for updating the second clock frequency. An electron beam drawing apparatus, comprising:
(Appendix 2) The first clock generation circuit generates the write clock using a first direct digital synthesizer circuit,
The electron beam drawing apparatus according to appendix 1, wherein the second clock generation circuit generates the spindle clock using a second direct digital synthesizer circuit.
(Supplementary Note 3) The frequency update circuit updates the frequency for each predetermined number of reference clocks, and updates the first and second clock frequencies a plurality of times within a period of one rotation of the motor. The electron beam drawing apparatus according to Supplementary Note 1.
(Supplementary note 4) The electron beam drawing apparatus further comprises:
An N divider circuit provided before the frequency update circuit, for dividing the reference clock by N;
The frequency update circuit counts the number of reference clocks divided by N by the N divider circuit;
Each of the first and second clock generation circuits includes an internal N divider circuit that divides the supplied reference clock by N, and operates with a reference clock divided by N by the internal N divider circuit. The electron beam lithography apparatus according to appendix 1, characterized by:
(Supplementary Note 5) The frequency update circuit includes a counter for counting the number of the reference clocks, and frequency setting data corresponding to the first clock frequency to be updated when the count value in the counter reaches a predetermined value. Write clock frequency data setting register to be output to the first clock generating circuit, and frequency setting data corresponding to the second clock frequency to be updated when the count value in the counter reaches a predetermined value. The electron beam drawing apparatus according to appendix 1, further comprising: a spindle clock frequency data setting register that outputs to a creating circuit.
(Supplementary Note 6) The frequency update circuit further includes a counter that counts the number of reference clocks, a clock number setting register that presets the number of predetermined clocks, a count value in the counter, and a clock number setting register A comparison circuit for comparing the set value,
When the comparison results in the comparison circuit match, the write clock frequency data setting register outputs frequency setting data corresponding to the first clock frequency to be updated to the first clock generation circuit, and sets spindle clock frequency data. The electron beam drawing apparatus according to appendix 5, wherein the register outputs frequency setting data corresponding to the second clock frequency to be updated to the second clock generating circuit.
(Supplementary note 7) The electron beam drawing apparatus according to supplementary note 5, wherein the frequency update circuit updates the set value in the clock number setting register when the count value in the counter reaches a predetermined value.
(Supplementary note 8) The electron beam drawing apparatus further comprises:
A third clock generating circuit having a third clock frequency based on the reference clock and generating a stage clock serving as a reference for a linear moving speed of the rotary drive mechanism;
The electron beam drawing apparatus according to appendix 1, wherein the reference clock generating circuit supplies the reference clock to the third clock generating circuit.

  As described above, according to the present invention, in the electron beam drawing apparatus, the frequencies of the output clocks (that is, the write clock and the spindle clock) of the first and second clock generation circuits are not based on the output clock. Based on the count value of the reference clock, the next frequency is simultaneously switched. Therefore, an error due to the output clock can be eliminated without adding a complicated switching timing prediction circuit, and the first and second clocks can be synchronized.

  In particular, since the reference clock is counted, an error in the range of ± 1 reference clock can be prevented, and the counters and the like in the first and second clock generation circuits are made common so that the circuit is large. Scale-up and complexity can be prevented.

  Further, since the first and second clocks are switched at the same timing, it is possible to prevent errors from being accumulated between the two due to the switching and to simplify the switching process once. As a result, the output clock frequency can be changed continuously by switching more and more, for example, by changing the spindle clock smoothly, the rotational speed of the motor can be controlled without degrading its rotational accuracy. can do.

  Further, when a commercially available DDS IC is used as the DDS circuit of the first and second clock generation circuits, errors and delays in the output clock caused by the IC are eliminated, and the control becomes complicated and the circuit becomes difficult. A large scale can be avoided.

It is a block diagram which shows an example of the electron beam drawing apparatus of this invention. It is a block diagram which shows an example of the control signal preparation circuit of the electron beam drawing apparatus of this invention. It is a block diagram which shows another example of the control signal production circuit of the electron beam drawing apparatus of this invention. It is a block diagram which shows another example of the control signal preparation circuit of the electron beam drawing apparatus of this invention. It is a block diagram which shows another example of the control signal preparation circuit of the electron beam drawing apparatus of this invention. It is explanatory drawing of drawing of the master for information recording. It is a block diagram which shows the control signal preparation circuit of the conventional electron beam drawing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Formatter 2 Reference clock creation circuit 3 1st clock creation circuit 4 2nd clock creation circuit 5 Data generator 6 Spindle control circuit 7 1st DDS circuit 8 2nd DDS circuit 9 Frequency update circuit 91 Counter 92 Comparison circuit 93 Number of pulses N (n) Setting register 94 Write clock next frequency data setting register 95 Spindle clock next frequency data setting register 96 Control processor

Claims (5)

In an electron beam lithography apparatus that exposes a master disk of a recording medium by irradiating an electron beam onto a master disk placed on a rotational drive mechanism,
A first clock generating circuit having a first clock frequency based on a reference clock and generating a write clock serving as a reference for exposure timing;
A second clock generating circuit that generates a spindle clock having a second clock frequency based on the reference clock and serving as a reference for the rotational speed of the motor included in the rotation driving mechanism;
A reference clock generating circuit for supplying the reference clock as a common clock to the first and second clock generating circuits;
The first and second clock generation circuits are provided in common and the first and second clock generation circuits in the first and second clock generation circuits when the count value reaches a predetermined value when the number of the reference clocks is counted. And a frequency update circuit for updating the second clock frequency. An electron beam drawing apparatus, comprising: The first clock generation circuit generates the write clock using a first direct digital synthesizer circuit;
The electron beam drawing apparatus according to claim 1, wherein the second clock generation circuit generates the spindle clock using a second direct digital synthesizer circuit. The frequency update circuit updates the frequency for each predetermined number of reference clocks, and updates the first and second clock frequencies a plurality of times within a period of one rotation of the motor. The electron beam drawing apparatus described in 1. The electron beam drawing apparatus further includes:
An N divider circuit provided before the frequency update circuit, for dividing the reference clock by N;
The frequency update circuit counts the number of reference clocks divided by N by the N divider circuit;
Each of the first and second clock generation circuits includes an internal N divider circuit that divides the supplied reference clock by N, and operates with a reference clock divided by N by the internal N divider circuit. The electron beam drawing apparatus according to claim 1. A counter for counting the number of reference clocks; and frequency setting data corresponding to a first clock frequency to be updated when a count value in the counter reaches a predetermined value. Write clock frequency data setting register to be output to the generating circuit, and output frequency setting data corresponding to the second clock frequency to be updated when the count value in the counter reaches a predetermined value to the second clock generating circuit The electron beam drawing apparatus according to claim 1, further comprising: a spindle clock frequency data setting register for performing the operation.

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