JP4803775B2 - Body grabbing switch - Google Patents

Description

[0001]
(Field of Invention)
The present invention relates to the field of CMOS switches. More particularly, the present invention relates to a circuit that eliminates a body effect in a CMOS switch.
[0002]
(Background technology)
Integrated circuit (IC) chips are used and incorporated in almost all modern electronic and computer products. For example, modern products such as computers, telephones, electronic merchandise, etc. typically include one or more IC chips. As is well known to those skilled in the art, IC chips often include a switched capacitor circuit, which includes many analog and mixed signal circuits (including filters, data converters, communication circuits, etc.) Used to realize mixed-signal circuits).
[0003]
One of the main elements of a switch capacitor circuit is a switch. In IC chip settings, complementary MOS (CMOS) switches are often used to take advantage of their high speed, small size, and zero turn-on voltage drop. FIG. 1 illustrating the prior art illustrates a conventional CMOS switch 100 that can be used in an IC chip. The conventional CMOS switch 100 includes an n-channel MOS (NMOS) transistor M1 and a p-channel MOS (PMOS) transistor M2. The NMOS transistor M1 and the PMOS transistor M2 are connected in parallel to each other at the common source node 102 and the common drain node 104. In operation, the CMOS switch 100 receives the input signal V at node 102. _in Received, V _in Output signal V at node 104 _out Communicate as
[0004]
In order to operate the CMOS switch 100, the gate of the NMOS transistor M1 is connected to the supply voltage rail V _dd The gate of the PMOS transistor M2 is connected to the ground potential. The body of transistor M2 is the supply voltage V _dd When coupled to, the body (eg, substrate or bulk) of transistor M1 is coupled to ground potential. Transistors M 1 and M 2 are connected to each other at source node 102 and drain node 104.
[0005]
If designed with standard transistor components, the CMOS switch 100 has a supply voltage V of 5V or greater. _dd Works properly. However, since today's IC chips are constantly shrinking in dimensions, the number of IC chips that use a supply voltage lower than 5V (for example, 3V) is increasing. The use of the low supply voltage saves power, which is advantageous in many applications including mobile computing and communication fields.
[0006]
Unfortunately, the use of a low supply voltage such as 3V in the CMOS switch setting results in a permanent body effect (eg, back gate bias effect) that can adversely affect the switching of transistors M1 and M2. In particular, at low supply voltages, the transistors M1 and M2 of the CMOS switch 100 may not turn on properly due to the low gate overdrive combined with the body effect in the transistors M1 and M2. When the body is at a different potential than the source / drain, a body effect occurs in the MOS transistor and a reverse biased junction is formed between the source / drain and the body (ie, substrate) of the transistor. A reverse bias PN junction causes a depletion region to form around the associated drain or source.
[0007]
For example, when the substrate or body (eg, p-type silicon) of an NMOS transistor is formed negative with respect to the source or drain (eg, n-type silicon) of the transistor, the depletion region between the substrate and the source / drain is Exhibits a greater voltage drop, which results in a thicker. Thus, to turn on the transistor, a higher voltage must be applied to the gate of the NMOS transistor to overcome the large depletion region. The net result of the body effect is that the reverse bias between the substrate and the source or drain increases, resulting in an effective threshold voltage V of the NMOS transistor. _{TH, NMOS} However, it increases in appearance. Similarly, the effective threshold voltage of the PMOS transistor | V _{TH, PMOS} | Increases if its body (eg, n-type silicon) is at a higher potential than the source or drain (eg, p-type silicon).
[0008]
For example, the transistors M1 and M2 of the CMOS switch 100 having no body effect have the threshold voltage V _TH = V _{TH, NMOS} = | V _{TH, PMOS} Characterized by | = 0.8 volts. Assuming that the body effect is to add 0.5 volts, the apparent threshold voltage V of transistors M1 and M2 _TH Is 1.3 volts (0.8 + 0.5 volts). Supply voltage V _dd Is 3V and the voltage at the input and output nodes is about 1.5 volts (ie V _dd / 2), the apparent threshold voltage and the gate to source voltage V _gs The margin between (eg gate overdrive) is only 0.2 volts. In such a narrow margin, the CMOS switch 100 does not operate with high reliability. In addition, 3V rated supply voltage V _dd Can actually vary between 2.7 volts and 3.3 volts. When the supply voltage is 2.7V, the voltage margin is further reduced. Thus, transistors M1 and M2 may not turn on properly.
[0009]
One obvious solution to the switching problem caused by the body effect is to use a higher supply voltage. For example, a high supply voltage such as 5 volts overcomes the body effect by adding a high gate voltage that compensates for the body effect. Another approach is to use a special clock booster or charge pump circuit that provides larger gate overdrive for the affected transistors. Unfortunately, such a circuit produces an internal voltage that is higher than the supply voltage. Therefore, these circuits usually require a particularly high voltage transistor structure. However, standard submicron commercial silicon processes typically do not implement such structures due to high manufacturing costs. Furthermore, the small transistor size in such a process means that a normal transistor has a relatively low breakdown voltage.
[0010]
Another solution employs a low threshold transistor having a threshold voltage of, for example, 0.3 to 0.4 volts to overcome the body effect. However, such a solution is more costly because low threshold voltage transistors require extra processing steps. However, most commercial CMOS processes typically do not have this option. Furthermore, low threshold voltage transistors have significant leakage currents even when turned off.
[0011]
Therefore, what is needed is a circuit and method for switching a CMOS switch with a low supply voltage without the need for costly complex circuit structures. There is also a need for a circuit and method that eliminates the body effect of transistors used in CMOS switches.
[0012]
(Summary of the Invention)
Generally speaking, the present invention satisfies the aforementioned needs by providing a circuit that allows switch conduction at low supply voltages by eliminating body effects. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, apparatus, system, device or method. Several embodiments of the invention are described below.
[0013]
In one embodiment, the present invention provides a switch circuit. The switch circuit includes a switch and a first body grabbing circuit. The switch includes a first transistor and a second transistor. The first transistor has a body and is connected in parallel with the second transistor to form a common source and a common drain. The common source defines an input node, and the common drain defines an output node. The first body grabbing circuit is connected to the body of the first transistor. The first body grabbing circuit is arranged to connect the body of the first transistor to the input node when the first and second transistors receive the turn-on voltage signal. The first body effect in the transistor is eliminated.
[0014]
In another embodiment, the switch circuit includes first and second switching means and first body connecting means. The first and second switching means are arranged to transmit the input signal to the output node. The first switching means has a body. The switching means receives an input signal at an input node. The first and second switching means are connected at the input node and the output node. The first body grabbing circuit is arranged to connect the body of the first switching means to the input node when the first and second switching means receive the turn-on voltage signal. The first body effect in one switching means is substantially eliminated.
[0015]
In yet another embodiment, the present invention provides a method for eliminating the body effect in a first transistor comprising a body, a source, a drain, and a gate. The method includes: (a) receiving an input signal at a source; (b) applying a first voltage to a first transistor; (c) connecting a body of the first transistor to an input node; And (d) obtaining the output voltage at the drain of the first transistor.
[0016]
Conveniently, the present invention eliminates body effects in the transistor by coupling the body to the source and / or drain of the transistor when the CMOS switch is about to be turned on. This body coupling or grabbing to the source and / or drain easily turns on the transistor by allowing the switch to conduct even when the supply voltage is low. Furthermore, the body grabbing circuit of the present invention provides channel continuity for the entire range of supply voltages without the need for a clock booster or charge pump. In addition, body grabbing circuits do not require high gate overdrive voltages, thus reducing the risk of failure in modern sub-micron order silicon processes. Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
[0017]
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the text of the specification, serve to explain the principles of the invention.
[0018]
(Description of Preferred Embodiment)
In the following detailed description of the invention, a body grabbing circuit and method and numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure features of the present invention.
[0019]
The present invention provides a body grabbing switch in a CMOS switch circuit. A body grabbing switch removes the body effect of one or more MOS transistors in a CMOS switch by coupling the body to the source and / or drain of the transistor when the CMOS switch is about to be turned on. . This coupling or grabbing of the body to the source and / or drain facilitates the transistor by allowing the switch to conduct even when the channel of the transistor is close to the mid-supply voltage. To turn on.
[0020]
FIG. 2A illustrates a CMOS switch 200 with a body grabbing circuit that couples the bodies of transistors according to one embodiment of the present invention. The CMOS switch 200 includes an NMOS transistor M1 and a PMOS transistor M2. The transistors M1 and M2 are connected at the common source node 202 and the common drain node 204. Input voltage signal V _in Is provided at the common source node 202, which is also the input node. The CMOS switch 200 has an output voltage signal V at a common drain node 204 that is also an output node. _out Is output.
[0021]
The gate of NMOS transistor M1 receives input voltage signal CK1 when the body is coupled to ground potential. The gate of the PMOS transistor M2 receives the input voltage signal CK1B. The body of transistor M2 is the supply voltage rail V through transistor M4 in the body grabbing circuit. _dd Is bound to.
[0022]
The body grabbing circuit in FIG. 2A includes a pair of PMOS transistors M3 and M4. Transistor M4 has a transistor M2 body and supply voltage rail V _dd Connected between. More specifically, the drain of transistor M4 is connected to the body of transistor M2 at node 206 and the source is connected to supply voltage rail V _dd It is connected to the. The body and source of the transistor M4 are connected to each other and to the supply voltage rail V _dd It is connected to the. Transistor M4 receives input signal CK2 at its gate.
[0023]
The other transistor M3 of the body grabbing circuit is connected between the body of the transistor M2 at the node 206 and the input node 202. More specifically, the source and body of transistor M3 are connected to the body of transistor M2 at node 206, and the drain of transistor M3 is connected to input node 202. Transistor M3 receives input voltage signal CK2B at its gate.
[0024]
FIG. 2B shows a time chart 250 in the operating state of the CMOS switch 200. Transistors M1, M2, M3, and M4 operate in response to input gate voltages CK1, CK1B, CK2B, and CK2, respectively. It should be appreciated that the input gate voltages CK1, CK1B, CK2B and CK2 are measured and discussed with reference to ground potential.
[0025]
First, at time t1, the gate input voltage signal CK1 of the transistor M1 is low (eg, ground potential), and the gate input voltage signal CK1B of the transistor M2 is high (eg, supply voltage V _dd ). Further, the gate input voltage signal CK2B of the transistor M3 is high (for example, the supply voltage V _dd ). Thus, the transistors M1, M2, and M3 are off. The only transistor that is on is transistor M4 with low input voltage signal CK2. In this state, the transistor M4 supplies the voltage of the body node 206 to the supply voltage V _dd Attract to. The body of M1 is ground potential and the body of transistor M2 is the supply voltage V _dd Therefore, both the transistors M1 and M2 are off. Therefore, the CMOS switch 200 is also in the off state.
[0026]
At time t2, the CMOS switch 200 is turned on. The input gate voltage signal CK1 of the transistor M1 is the supply voltage V _dd When rising to (eg 3V), transistor M1 is turned on. On the other hand, the gate input voltage signal CK1B of the transistor M2 falls to the ground potential (for example, 0V). Thus, both transistors M1 and M2 are turned on. In this configuration, the body of the NMOS transistor M1 is at ground potential and the body of the PMOS transistor M2 is still at the supply voltage V _dd Is bound to. In this state, the transistors M1 and M2 are subjected to the body effect as in the conventional CMOS switch circuit.
[0027]
At time t3, the gate input voltage signal CK2 of the transistor M4 rises from low (eg, ground potential) to high (eg, supply voltage). This voltage transition turns off transistor M4. On the other hand, the input gate voltage of the transistor M3 in the body grabbing circuit falls from a high voltage to a low voltage (for example, from the supply voltage to the ground potential), thereby turning on the transistor M3. Switching of transistor M3 shorts body node 206 of transistor M2 to input node 202.
[0028]
Eventually, transistor M3 replaces the body of transistor M2 with supply voltage rail V _dd Instead of the input voltage V _in Are coupled or “grabbed” (ie, connected). As a result, the body, source and drain of transistor M2 have the same voltage. Therefore, the PN junction in transistor M2 is not reverse biased. The lack of a reverse bias junction means that no depletion region is formed in the transistor, thereby effectively eliminating the body effect. As a result, the effective threshold voltage V of the transistor M2 _TH Is reduced, thereby allowing the transistor to turn on more reliably and easily than conventional CMOS switch transistors.
[0029]
The preferred embodiment of the present invention provides a slight delay between times t2 and t3. In particular, the input signals CK2 and CK2B change at time t3 after the input signals CK1 and CK1B change at time t2. Preferably, such a delay is long enough to prevent latch-up that may be due to current from the drain to the body of transistor M2.
[0030]
In other embodiments, t2 and t3 are the same. That is, the signals CK1, CK1B, CK2, and CK2B change simultaneously without a delay between t2 and t3. In one embodiment, the input signal CK2B follows the input signal CK2 after a short delay.
[0031]
At time t4, the CMOS switch is turned off. In particular, the input gate voltage signals CK1, CK1B, CK2, and CK2B return to the original off state at time t1. In this state, transistor M3 is off and transistor M4 is on. Therefore, the body of the transistor M2 is the voltage supply rail V _dd Connected back to. Preferably, transistors M1 and M2 are turned off after the transition of transistors M3 and M4.
[0032]
According to another embodiment of the present invention, the body grabbing switch circuit is also connected to the body of the NMOS transistor in the CMOS switch. FIG. 3A illustrates a CMOS switch 300 with a body grabbing circuit that couples the bodies of NMOS transistors, according to one embodiment of the present invention. Similar to the CMOS switch 200 of FIG. 2A, the CMOS switch 300 includes an NMOS transistor M1 and a PMOS transistor M2. The transistors M1 and M2 are connected at the common source node 302 and the common drain node 304. Input voltage signal V _in Is provided at the common source node 302 which is an input node. The CMOS switch 300 has an output voltage signal V at a common drain node 304 as an output node. _out Is output.
[0033]
The gate of the NMOS transistor M1 receives the input voltage signal CK1. The body of the transistor M1 is connected to the ground potential via the transistor M6 in the body grabbing circuit. The gate of the PMOS transistor M2 receives the input voltage signal CK1B, while the body is the supply voltage rail V _dd Is bound to.
[0034]
The body grabbing circuit in FIG. 3A includes a pair of NMOS transistors M5 and M6. Transistor M6 is connected between the body of transistor M1 and the ground rail. That is, the drain of transistor M6 is connected to the body of transistor M1 at node 306, and the source of transistor M6 is connected to ground. The body and source of transistor M6 are connected to each other and to ground. Transistor M6 receives input signal CK3 at its gate.
[0035]
Another transistor M5 of the body grabbing circuit is connected between the body of the transistor M1 at the node 306 and the input node 302. More specifically, the source and body of transistor M5 are connected to the body of transistor M1 at node 306, and the drain of transistor M5 is connected to input node 302. Transistor M5 receives input voltage signal CK3B at its gate.
[0036]
FIG. 3B shows a time chart 350 in the operating state of the CMOS switch 300. Transistors M1, M2, M5, and M6 operate in response to input gate voltages CK1, CK1B, CK3B, and CK3, respectively. It should be appreciated that the input gate voltages CK1, CK1B, CK3B and CK3 are measured and discussed with reference to ground potential.
[0037]
First, at time t1, the gate input voltage signal CK1 of the transistor M1 is low (eg, ground potential), and the gate input voltage signal CK1B of the transistor M2 is high (eg, supply voltage V _dd ). Further, the gate input voltage signal CK3B of the transistor M5 is low (eg, ground potential). Therefore, the transistors M1, M2 and M5 are off. The only transistor that is on is a high input voltage signal CK3 (eg, supply voltage V _dd ). In this state, transistor M6 pulls the voltage at body node 306 to ground. The body of M1 is ground potential and the body of transistor M2 is the supply voltage V _dd Therefore, both the transistors M1 and M2 are off. Therefore, the CMOS switch 300 is also in the off state.
[0038]
At time t2, the CMOS switch 300 is turned on. The input gate voltage signal CK1 of the transistor M1 is the supply voltage V _dd When rising to (eg 3V), transistor M1 is turned on. On the other hand, the gate input voltage signal CK1B of the transistor M2 falls to the ground potential (for example, 0V). Thus, both transistors M1 and M2 are turned on. In this configuration, the body of the NMOS transistor M1 is still at ground potential and the body of the PMOS transistor M2 is at the supply voltage V _dd Is bound to. In this state, the transistors M1 and M2 are subjected to the body effect as in the conventional CMOS switch circuit.
[0039]
At time t3, the gate input voltage signal CK3 of the transistor M6 falls from high (for example, supply voltage) to low (for example, ground potential). This voltage transition turns off transistor M4. On the other hand, the input gate voltage signal CK3B of the transistor M5 in the body grabbing circuit rises from the low voltage to the high voltage (for example, from the ground potential to the supply voltage), thereby turning on the transistor M5. Switching of transistor M5 shorts body node 306 of transistor M1 to input node 302.
[0040]
Eventually, transistor M5 replaces the body of transistor M1 with supply voltage rail V _dd Instead of the input voltage V _in Bind or “grab”. As a result, the body, source and drain of transistor M1 have the same voltage. Therefore, the PN junction in transistor M1 is not reverse biased. The lack of a reverse bias junction means that no depletion region is formed in the transistor, thereby effectively eliminating the body effect. As a result, the effective threshold voltage V of the transistor M1 _TH Is reduced, thereby allowing the transistor to turn on more reliably and easily than conventional CMOS switch transistors.
[0041]
Similar to the CMOS switch 200 of FIG. 2A, the preferred embodiment of the CMOS switch 300 provides a slight delay between times t2 and t3. In particular, the input signals CK3 and CK3B change at time t3 after the input signals CK1 and CK1B change at time t2. Preferably, such a delay is long enough to prevent latch-up that may be due to electrons flowing from the drain of transistor M1 to the body.
[0042]
In other embodiments, t2 and t3 are the same. That is, the signals CK1, CK1B, CK3, and CK3B change simultaneously without a delay between t2 and t3. In one embodiment, the input signal CK3B follows the input signal CK3 after a short delay.
[0043]
At time t4, the CMOS switch 300 is turned off. In particular, the input gate voltage signals CK1, CK1B, CK3, and CK3B return to the original off state at time t1. In this state, transistor M5 is off and transistor M6 is on. Thus, the body of transistor M1 is coupled back to ground. Preferably, transistors M1 and M2 are turned off after the transition of transistors M5 and M6.
[0044]
According to another embodiment of the present invention, the body grabbing switch circuit is also connected to the body of each of the NMOS and PMOS transistors in the CMOS switch. FIG. 4A shows a CMOS switch 400 with a pair of body grabbing circuits that couple the bodies of NMOS and PMOS transistors according to one embodiment of the present invention. Similar to the CMOS switch 200 of FIG. 2A and the CMOS switch 300 of FIG. 3A, the CMOS switch 400 includes an NMOS transistor M1 and a PMOS transistor M2. The transistors M1 and M2 are connected at a common source node 402 and a common drain node 404. Input voltage signal V _in Is provided at the common source node 402, which is the input node. The CMOS switch 400 has an output voltage signal V at a common drain node 404 that is an output node. _out Is output.
[0045]
The gate of the PMOS transistor M2 receives the input voltage signal CK1B. The body of the transistor M2 is connected to the supply voltage rail V through a first body grabbing circuit comprising PMOS transistors M3 and M4. _dd Alternatively, it is connected to the node 402. The gate of the NMOS transistor M1 receives the input voltage signal CK1. The body of the transistor M1 is connected to the ground potential or the node 402 via a second body grabbing circuit including a pair of NMOS transistors M5 and M6.
[0046]
The first body grabbing circuit in FIG. 4A includes a pair of PMOS transistors M3 and M4. Transistor M4 has a transistor M2 body and supply voltage rail V _dd Connected between. More specifically, the drain of transistor M4 is connected to the body of transistor M2 at node 406 and the source is connected to supply voltage rail V _dd It is connected to the. The body and source of the transistor M4 are connected to each other and to the supply voltage rail V _dd It is connected to the. Transistor M4 receives input signal CK2 at its gate.
[0047]
Another transistor M 3 of the body grabbing circuit is connected between the body of the transistor M 2 at the node 406 and the input node 402. More specifically, the source and body of transistor M3 are connected to the body of transistor M2 at node 406, and the drain of transistor M3 is connected to input node 402. Transistor M3 receives input voltage signal CK2B at its gate.
[0048]
The second body grabbing circuit in FIG. 4A includes a pair of NMOS transistors M5 and M6. The transistor M6 is connected between the body of the transistor M1 and the earth rail. That is, the drain of transistor M6 is connected to the body of transistor M1 at node 408, and the source of transistor M6 is connected to ground. The body and source of transistor M6 are connected to each other and to ground. Transistor M6 receives input signal CK3 at its gate.
[0049]
Another transistor M5 of the body grabbing circuit is connected between the body of the transistor M1 at the node 408 and the input node 402. More specifically, the source and body of transistor M5 are connected to the body of transistor M1 at node 408, and the drain of transistor M5 is connected to input node 402. Transistor M5 receives input voltage signal CK3B at its gate.
[0050]
FIG. 4B shows a time chart 450 in the operating state of the CMOS switch 400. Transistors M1, M2, M3, M4, M5 and M6 operate in response to input gate voltages CK1, CK1B, CK2B, CK2, CK3B and CK3, respectively. Time chart 450 is a combination of the time charts described above with respect to FIGS. 2B and 3B. Accordingly, the CMOS switch 400 operates in the same manner as the CMOS switch 200 of FIG. 2A and the CMOS switch 300 of FIG. 3A.
[0051]
However, it should be noted that the time chart 450 shows that there is a delay between the time when the signals CK2 and CK3 change and the time when the signals CK2B and CK3B change. In particular, this time chart represents a delay between times t3 and t5 and a delay between times t6 and t7. Although the time chart shows these delays, it should be recognized that the CMOS switch 400 can operate without these delays.
[0052]
Conveniently, the present invention eliminates body effects in the transistor by coupling the body to the source and / or drain of the transistor when the CMOS switch is about to be turned on. This body coupling or grabbing to the source and / or drain easily turns on the transistor by allowing the switch to conduct even when the supply voltage is low. Furthermore, the body grabbing circuit of the present invention provides channel continuity for the entire range of supply voltages without the need for a clock booster or charge pump. In addition, body grabbing circuits do not require high gate overdrive voltages, thus reducing the risk of failure in modern sub-micron order silicon processes.
[0053]
While the invention has been described in terms of several preferred embodiments, there are alterations, permutations and equivalents that are within the scope of the invention. It should also be noted that there are alternative means of implementing both the method and apparatus of the present invention. Accordingly, the appended claims are intended to be construed to include all such modifications, alterations and equivalents that are within the true spirit and scope of the invention.
[Brief description of the drawings]
FIG. 1 relates to the prior art and shows a conventional CMOS switch that can be used in an IC chip.
FIG. 2A shows a CMOS switch with a body grabbing circuit that couples the bodies of PMOS transistors, according to one embodiment of the present invention.
FIG. 2B shows a time chart in the operating state of the CMOS switch of FIG. 2A.
FIG. 3A shows a CMOS switch 300 with a body grabbing circuit that couples the bodies of NMOS transistors, according to one embodiment of the present invention.
FIG. 3B shows a time chart in the operating state of the CMOS switch of FIG. 3A.
FIG. 4A shows a CMOS switch with a body grabbing circuit that couples the bodies of both transistors in the CMOS switch.
FIG. 4B shows a time chart in the operating state of the CMOS switch of FIG. 4A.

Claims (37)

A switch circuit comprising a switch and a first body grabbing circuit, the switch comprising a first transistor and a second transistor, the first transistor having a body, a common source, A common source is connected in parallel with the second transistor to form a common drain, the common source defines an input node, the common drain defines an output node, and the first body grabbing circuit includes a first transistor. And when the first and second transistors receive the turn-on voltage signal, the body of the first transistor is connected to the input node so that the first body effect is eliminated in the first transistor. arranged to connect to,
The first body grabbing circuit is further connected between a body of the first transistor and a third transistor connected between the first voltage level and a body of the first transistor and an input node. A fourth transistor, wherein the third transistor is arranged to connect the body of the first transistor to the first voltage level when the first transistor receives the turn-off voltage signal, The fourth transistor is arranged to connect the body of the first transistor to the input node when the first transistor receives the turn-on voltage signal;
The third transistor is turned off in response to the turn-off voltage signal after the first and second transistors receive the turn-on voltage signal;
When the third transistor is turned off in response to a turn-off voltage signal, the fourth transistor is turned on to connect the body of the first transistor to an input node. Switch circuit.   The second transistor has a body, and the switch circuit further includes a second body grabbing circuit connected to a body of the second transistor, and the second body grabbing circuit includes: The first and second transistors are arranged to connect the body of the second transistor to the input node when the first and second transistors receive the turn-on voltage signal, so that the body effect of 2 is missing in the second transistor. The switch circuit according to claim 1. The second body grabbing circuit further includes a fifth transistor connected between the bodies of the second transistors, and a sixth transistor connected between the body of the second transistors and the input node. And the fifth transistor is arranged to connect the body of the second transistor to the second voltage level when the second transistor receives the turn-off voltage signal, and the sixth transistor is 3. The switch circuit according to claim 2 , wherein the switch circuit is arranged to connect the body of the second transistor to the input node when the second transistor receives the turn-on voltage signal.   The switch circuit according to claim 1, wherein the switch circuit is a CMOS switch circuit.   2. The switch circuit according to claim 1, wherein the first and second transistors are MOS transistors.   2. The switch circuit according to claim 1, wherein the first transistor is an n-channel MOS transistor, and the second transistor is a p-channel MOS transistor.   2. The switch circuit according to claim 1, wherein the first transistor is a p-channel MOS transistor, and the second transistor is an n-channel MOS transistor. 2. The switch circuit according to claim 1 , wherein the third and fourth transistors are p-channel MOS transistors. 9. The switch circuit according to claim 8 , wherein the first transistor is a p-channel MOS transistor. The switch circuit according to claim 1 , wherein the third and fourth transistors are n-channel MOS transistors. The switch circuit according to claim 10 , wherein the first transistor is an n-channel MOS transistor.   The turn-on signal further comprises a first turn-on signal and a second turn-on signal, the first transistor receives a first turn-on signal, and the second transistor receives a second turn-on signal. The switch circuit according to claim 1, wherein the switch circuits receive simultaneously. The switch circuit according to claim 1 , wherein the fourth transistor is turned on after the third transistor is turned off. 14. The switch circuit according to claim 13 , wherein the first, second, third, and fourth transistors change state at the same time. 14. The switch circuit according to claim 13 , wherein the third and fourth transistors change their states at the same time.   The switch circuit according to claim 1, wherein the switch circuit is used in a switch capacitor circuit.   The switch circuit according to claim 1, wherein the switch circuit is a low voltage switch circuit. First and second switching means for transmitting an input signal to an output node, wherein the first switching means has a body, the first switching means receives the input signal at the input node, and the first and second switching means The first and second switching means, in which two switching means are connected at the input node and the output node, and the first body effect in the first switching means are eliminated. First switching means for connecting the body of the first switching means to the input node when the switching means receives the turn-on voltage signal ;
The first body connecting means further includes third switching means for connecting the body of the first switching means to the first voltage level when the first switching means receives a turn-off voltage signal; A fourth switching means for connecting the body of the first switching means to the input node when the first switching means receives the turn-on voltage signal;
The third switching means is turned off in response to a turn-off voltage signal after the first and second switching means receive the turn-on signal;
When the third switching means is turned off in response to a turn-off voltage signal, the fourth switching means is turned on to connect the body of the first switching means to an input node. Switch circuit. The second switching means has a body, and the switch circuit further comprises second body connecting means connected to the body of the second switching means, and the second body connecting means The body of the second switching means is used as an input node when the first and second switching means receive the turn-on voltage signal so that the second body effect in the second switching means is substantially eliminated. The switch circuit according to claim 18 , wherein the switch circuit is connected. The second body connecting means is further connected to the body of the second switching means, and when the second switching means receives the turn-off voltage signal, the body of the second switching means is connected to the second voltage. Fifth switching means arranged to be connected to the level, and sixth switching means connected between the body of the second switching means and the input node, the sixth switching means comprising: 20. The switch circuit according to claim 19 , wherein the second switching means is arranged to connect the body of the second switching means to the input node when receiving the turn-on voltage signal. The switch circuit according to claim 18 , wherein the switch circuit is a CMOS switch circuit. 19. The switch circuit according to claim 18 , wherein the first and second switching means are MOS transistors. 19. The switch circuit according to claim 18 , wherein the first switching means is an n-channel MOS transistor, and the second switching means is a p-channel MOS transistor. 19. The switch circuit according to claim 18 , wherein the first switching unit is a p-channel MOS transistor, and the second switching unit is an n-channel MOS transistor. 19. The switch circuit according to claim 18 , wherein the third and fourth switching means are p-channel MOS transistors. 26. The switch circuit according to claim 25 , wherein the first switching means is a p-channel MOS transistor. 19. The switch circuit according to claim 18 , wherein the third and fourth switching means are n-channel MOS transistors. 19. The switch circuit according to claim 18 , wherein the first switching means is an n-channel MOS transistor. The turn-on signal further comprises a first turn-on signal and a second turn-on signal, the first switching means receives a first turn-on voltage signal, and the second switching means has a second turn-on signal, 19. The switch circuit according to claim 18 , wherein turn-on is received simultaneously. 30. The switch circuit according to claim 29 , wherein the fourth switching means is turned on after the third switching means is turned on. 31. The switch circuit according to claim 30 , wherein the first, second, third and fourth switching means change states simultaneously. The switch circuit according to claim 30 , wherein the third and fourth switching means change the state at the same time. The switch circuit according to claim 18 , wherein the switch circuit is used in a switch capacitor circuit. A method for removing a body effect in a first transistor having a body, a source, a drain, and a gate, comprising:
Receive the input signal at the source,
Applying a first voltage to the first transistor;
When the first transistor receives the turn-off voltage signal, the first transistor body is connected to the first transistor using a second transistor arranged to connect the body of the first transistor to the first voltage level. Connect to the voltage level,
When the second transistor turns off in response to the turn-off voltage signal after the first transistor receives the turn-on voltage signal, the voltage at the body of the first transistor is the same voltage as the source of the first transistor. Using the third transistor connected between the body and the source of the first transistor, the body of the first transistor is connected to the source ,
A method comprising obtaining an output voltage at a drain of a first transistor. 35. The method of claim 34 , wherein the first transistor is used in a CMOS switch circuit. 35. The method of claim 34 , wherein the first transistor is a CMOS transistor. The CMOS switch circuit includes a fourth transistor connected in parallel with the first transistor to form a common source node and a common drain node, the common source node defining an input node, and the common drain node The method of claim 34 , wherein defining an output node.

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