JP4803756B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having both high speed and low power.

  Currently, CMOS integrated circuits are widely used to realize semiconductor integrated circuit devices such as microprocessors. The various power consumptions of CMOS circuits include dynamic power consumption due to charging and discharging during switching and static power consumption due to subthreshold leakage current. Of these, dynamic power consumption consumes a large amount of power in proportion to the square of the power supply voltage VDD, so it is effective to lower the power supply voltage to reduce power consumption. Is declining.

  On the other hand, some current low-power microprocessors have a power management mechanism, and a plurality of operation modes are provided in the processor, and the supply of the clock to the execution unit is stopped according to the operation mode accordingly.

  By stopping the clock supply, dynamic power consumption in unnecessary execution units can be reduced as much as possible. However, static power consumption due to subthreshold leakage current cannot be reduced and remains.

  Since the operation speed of the CMOS circuit decreases as the power supply voltage decreases, it is necessary to lower the threshold voltage of the MOS transistor in conjunction with the decrease of the power supply voltage in order to prevent the operation speed from deteriorating. However, as the threshold voltage is lowered, the subthreshold leakage current increases drastically, and as the power supply voltage decreases, static power consumption due to subthreshold leakage current, which was not so large in the past, becomes significant. It was. For this reason, there is a problem of realizing a semiconductor integrated circuit device such as a microprocessor that achieves both high speed and low power.

  As a method for solving the above problem, there is a method for controlling the threshold voltage of the MOS transistor by variably setting the substrate bias as disclosed in, for example, Japanese Patent Laid-Open No. 6-54396.

  In an active state where high speed operation of the CMOS circuit is required, the substrate bias is set to the power supply potential for the PMOS (P channel MOS transistor) and to the ground potential for the NMOS (N channel MOS transistor). On the other hand, in a standby state where the CMOS circuit does not need to operate at high speed, a substrate bias is applied with a higher potential than the power supply voltage for PMOS and a lower potential for NMOS (this operation is referred to as `` pull substrate '' hereinafter). Express).

  By pulling the substrate during standby, the threshold value of the MOS transistor constituting the CMOS circuit can be increased, and static power consumption due to the subthreshold leakage current can be reduced.

  In order to realize a semiconductor integrated circuit device such as a microprocessor that achieves both high speed and low power, the substrate bias control as described above is performed for the CMOS circuit, and the threshold voltage of the MOS transistor is set when active. It is necessary to reduce the subthreshold leakage current by maintaining the high speed by reducing the threshold and by increasing the threshold voltage of the MOS transistor during standby.

However, according to a study by the inventors, the following problems remain to control the substrate bias in an actual circuit device.
(1) Ensure testability of the substrate bias control circuit.
(2) Prevent malfunction of CMOS circuit by controlling substrate bias.
(3) Minimize the increase in circuit area due to substrate bias control.
(4) Prevent malfunction of the semiconductor integrated circuit device when switching the substrate bias.

  The main means presented in the present invention to solve the above problems are as follows.

  The circuit test was facilitated by outputting the output of the negative voltage generation circuit in the substrate bias control circuit to the pad. That is, it is necessary for the negative voltage generation circuit to check whether or not the level of the voltage that is the output signal is the set voltage. For this reason, it is convenient to provide a terminal that outputs the output as it is. .

  In addition, a plurality of substrate driving MOS transistors for driving the substrate bias in the active state are arranged in the main circuit to be subjected to substrate bias control to lower the substrate impedance. In this case, since the circuit in the main circuit operates in the active state, it is necessary to reduce the impedance, fix the substrate potential, and suppress the variation of the transistor threshold.

  At this time, the driving force in the active state is larger than that in the standby state. For example, a driving force of 5 times, ideally 10 times or more is desirable.

  Furthermore, in order to ensure the stability of the circuit when switching the substrate bias, the gate control signal for controlling the gate voltage of the substrate driving MOS transistor is returned to the substrate bias control circuit after being connected to the gate of the substrate driving MOS transistor. The gate control signal is wired so that the substrate bias control circuit can detect that the substrate bias of the main circuit is stabilized by the potential of the returned signal.

  The semiconductor integrated circuit device includes a power-on reset circuit. The power-on reset circuit detects that the main circuit is turned on, and the power-on reset circuit turns on the power of the main circuit for a certain period of time. In the meantime, the substrate driving MOS transistor is in an active state in which the substrate bias is driven shallowly.

  Further, the substrate bias control circuit controls the output impedance of the gate control signal in the process of transition from the standby state to the active state to be larger than the impedance after the transition to the active state completely.

  The semiconductor integrated circuit device also includes a negative voltage generation circuit, and the substrate bias control circuit controls the output impedance of the negative voltage generation circuit in the standby state to be smaller than the output impedance of the negative voltage generation circuit in the active state. To do.

  The main circuit is composed of a plurality of cells, the power supply nets of the plurality of cells are supplied with power by the first wiring layer, and further, the power supply net using the second wiring layer orthogonal to the first wiring layer is provided. Yes, a switch cell is arranged at the intersection of the power net by the first wiring layer and the power net by the second wiring layer, and the connection between the power net by the first wiring layer and the power net by the second wiring layer is within the switch cell. Further, the substrate driving MOS transistor is arranged in the switch cell.

  Further, the substrate bias supply line of the MOS transistor constituting the cell is performed by the first wiring layer in parallel with the power supply net by the first wiring layer, and the second wiring is also parallel by the power supply net by the second wiring layer. Similarly to the power supply net, the substrate bias supply line by the first wiring layer and the substrate bias supply line by the second wiring layer are connected in the switch cell, similarly to the power supply net, and the gate voltage of the substrate driving MOS transistor A gate control signal for controlling is supplied by the second wiring layer above the switch cell in parallel with the power supply net by the second wiring layer, and is connected to the gate terminal of the substrate driving MOS transistor in the switch cell.

  More specifically, the present invention relates to a main circuit composed of at least one transistor, a substrate bias control circuit for controlling a voltage applied to the substrate of the transistor, and a main circuit by controlling the substrate bias control circuit. A standby control circuit that switches between an active state with a large amount of subthreshold leakage current and a standby state with a small amount of subthreshold leakage current. A terminal for outputting a negative voltage generated by the voltage generation circuit to the outside of the apparatus;

  At this time, the semiconductor integrated circuit device has a semiconductor chip having an output pad, a package having the semiconductor chip and having an external pin, one of the output pads is used as a terminal, and the terminal is connected to the external pin. Not.

  In another example, a main circuit composed of at least one MOS transistor, a substrate bias control circuit for controlling a voltage applied to the substrate of the MOS transistor, and a substrate bias control circuit are controlled to flow to the main circuit. It has a standby control circuit that switches to at least two states, an active state with a large subthreshold leakage current and a standby state with a small subthreshold leakage current. The substrate bias is controlled shallowly in the active state, and the substrate bias is deepened in the standby state. The driving force for controlling and driving the substrate bias shallowly in the active state is 10 times or more larger than the driving force for driving the substrate bias deeply in the standby state.

  At this time, when the substrate bias is controlled deeply, it is desirable not to operate the main circuit composed of the transistor pulling the substrate. Since the impedance of the substrate is high when the substrate is being pulled, the substrate potential is likely to change due to the operation of the MOS transistor. This is because the MOS transistor may malfunction.

  As a device structure, there are at least two substrate drive MOS transistors for driving the substrate bias shallowly in the active state at a distance of 20 μm or more, and the gate potential of the substrate drive MOS transistor is controlled by a substrate bias control circuit.

  The gate control signal for controlling the gate voltage of the substrate driving MOS transistor is returned to the substrate bias control circuit after being connected to the gate of the substrate driving MOS transistor, and the substrate bias control circuit is connected to the main circuit by the potential of the returned signal. It can be detected that the substrate bias is stable.

  The threshold voltage of the substrate driving MOS transistor is preferably larger than the threshold voltage of the MOS transistor constituting the main circuit. In addition, when an I / O circuit that interfaces with the outside is provided, the oxide film thickness of at least one MOS transistor that constitutes the I / O circuit is the oxide film thickness of the MOS transistor that constitutes the main circuit. It is preferable to be thicker than the thickness. In this way, it is desirable to increase the breakdown voltage of the portion to which mainly a high voltage is applied.

  Further, a power-on reset circuit for detecting that the main circuit is turned on is provided, and the substrate driving MOS transistor is controlled to be in an active state in which the substrate bias is driven shallowly for a certain period after the main circuit is turned on.

  In another aspect of the system to which the present invention is applied, the semiconductor integrated circuit device has first (VDDQ) and second (VDD) power supply voltages, and the first power supply voltage has an absolute value higher than the second power supply voltage. The second power supply voltage is 2 V or less, the second power supply voltage (VDD) is supplied to the main circuit (LOG), and the first power supply voltage (VDDQ) is connected to the substrate bias control circuit (VBC). The first power supply voltage is supplied to the standby control circuit (VBCC) before the second power supply voltage, and the substrate bias control circuit is a main circuit for a fixed time after the second power supply voltage is supplied. Is controlled to be in an active state.

  In addition, the output impedance of the gate control signal of the substrate drive MOS transistor in the process of transitioning from the standby state to the active state is controlled to be larger than the impedance after completely transitioning to the active state, so that the active state is changed from the standby state. It is possible to control the inrush current during the transition process by adjusting the transition speed of transition to the state.

  Furthermore, by controlling the output impedance of the gate control signal of the substrate drive MOS transistor in the process of transitioning from the standby state to the active state to be larger than the impedance after completely transitioning to the active state, The transition speed for transitioning to the state is adjusted, the inrush current in the transition process is controlled to be small, and the complete transition to the active state can be detected by the returned signal described above.

  The amplitude of the gate control signal can be made larger than the gate breakdown voltage of the substrate driving transistor.

  Further, the semiconductor integrated circuit device includes a negative voltage generation circuit, and the substrate bias control circuit controls the output impedance of the negative voltage generation circuit in the standby state to be smaller than the output impedance of the negative voltage generation circuit in the active state. be able to.

  Further, the negative voltage generation circuit has a first charge pump circuit and a second charge pump circuit, and the substrate bias control circuit generates a negative voltage using the first charge pump circuit in the standby state, and is in an active state. The negative charge is generated by using the second charge pump circuit, and the capacity of the pumping capacitor of the first charge pump circuit is smaller than the capacity of the pumping capacitor of the second charge pump circuit. 14. A semiconductor integrated circuit device according to item 13.

  The negative power generation circuit generates a third power supply voltage, the first power supply voltage is higher than the second power supply voltage, and the second power supply voltage is 2 V or less. The main circuit is supplied with the second power supply voltage, and the substrate bias control circuit and the standby control circuit are supplied with at least the first power supply voltage. The substrate bias of the PMOS transistor is controlled to the second power supply voltage potential, the substrate bias of the NMOS transistor is controlled to the third power supply voltage potential, and (third power supply voltage) = (first power supply voltage) − It is good also as (2nd power supply voltage).

  Further, the negative voltage generation circuit includes at least one charge pump circuit, a comparator, a first reference voltage circuit that generates a potential half the second power supply voltage, a first power supply voltage, and a third power supply. A second reference voltage circuit for generating an intermediate potential of the voltage, and the comparator compares the output voltage of the first reference voltage circuit with the output voltage of the second reference voltage generation circuit, and At least one can be controlled to stabilize the third power supply voltage.

  The first and second reference voltage generation circuits each comprise a series circuit in which MOS transistors of the same conductivity type, each having a substrate terminal connected to a source terminal and a gate terminal connected to a drain terminal, are connected in series. A plurality of MOS transistors can be selected to operate in the saturation region. The device can also be configured to have Schmitt characteristics.

  The main circuit is composed of a plurality of cells, the power supply nets of the plurality of cells are supplied with power by the first wiring layer, and a second wiring layer that goes directly to them is used above the first wiring layer. The switch cell is arranged at the intersection of the power net by the first wiring layer and the power net by the second wiring layer, and the connection between the power net by the first wiring layer and the power net by the second wiring layer is It is performed in the switch cell, and further, a substrate driving MOS transistor is arranged in the switch cell.

  In the switch cell, a decoupling capacitor may be further disposed between the power source and the ground.

  Further, above the power net of the second wiring layer, there is a power net of the fourth wiring layer parallel to the power net of the second wiring layer, and the power net of the second wiring layer and the fourth net The connection of the power supply net by the wiring layer may be performed outside the switch cell.

  Further, there is a power supply net by the fifth wiring layer, and the connection of the power supply net by the fourth wiring layer and the power supply net by the fifth wiring layer is performed in the switch cell, and the power supply by the fourth wiring layer is provided. The power mesh composed of the net and the power net composed of the fifth wiring layer is rougher than the power mesh composed of the power net composed of the first wiring layer and the power net composed of the second wiring layer. The thickness of the wiring layer 5 may be larger than both the thickness of the first wiring layer and the thickness of the second wiring layer.

  The substrate bias supply line of the MOS transistor constituting the cell is performed by the first wiring layer in parallel with the power supply net by the first wiring layer, and also by the second wiring layer in parallel with the power supply net by the second wiring layer. As in the power supply net, the substrate bias supply line by the first wiring layer and the substrate bias supply line by the second wiring layer may be connected in the switch cell.

  A gate control signal for controlling the gate voltage of the substrate driving MOS transistor is supplied by the second wiring layer above the switch cell in parallel with the power supply net by the second wiring layer, and the gate of the substrate driving MOS transistor in the switch cell. It may be connected to a terminal.

  The substrate bias supply line wired by the second wiring layer above the switch cell and the gate control signal may be arranged between the power supply nets wired by the second wiring layer above the switch cell.

  The semiconductor integrated circuit device may include a data path circuit, and the data flow direction of the data path circuit may be parallel to the power supply net formed by the first wiring layers of the plurality of cells.

  The substrate bias can be set so that the threshold value of at least one MOS transistor becomes high when the semiconductor integrated circuit device is selected.

  Furthermore, in another aspect, the circuit includes a first pumping capacitor, a second pumping capacitor, first and second P-channel transistors, first and second N-channel transistors, and an oscillation circuit. In the charge pump circuit, when the output of the oscillation circuit is “H”, the charge of the first pumping capacitor is pumped using the first pumping capacitor, the first P-channel transistor, and the first N-channel transistor, When the output of the oscillation circuit is “L”, the charge of the second pumping capacitor is pumped using the second pumping capacitor, the second P-channel transistor, and the second N-channel transistor.

  In another aspect, it has a main circuit (LOG) including a transistor configured on a semiconductor substrate, and a substrate bias control circuit (VBC) that controls a voltage applied to the substrate, and the main circuit is applied to the substrate. So that the control signal output from the substrate bias control circuit is input to the gate of the switch transistor, and the control signal returns to the substrate bias control circuit. It is configured.

  In addition, it is preferable in terms of layout that the switch transistor is arranged in a rectangular switch cell, the transistor is arranged in a rectangular standard cell, and one switch cell and a plurality of standard cells are arranged in a line.

  Furthermore, the wiring of the drive power supply (VSS, VDD) that drives the transistors (MN2, MP2) of the main circuit and the wiring of the substrate bias power supply (vbp, vbn) supplied from the substrate bias control circuit are connected to the switch cell and a plurality of It is preferable that the standard cell is vertically cut in the cell arrangement direction.

  From the standpoint of transistor resistance, the threshold value of the switch transistor is preferably larger than the threshold value of the transistor.

  The switch transistors (MN1, MP1) are inserted between the drive power supply (VSS, VDD) for driving the main circuit transistors (MN2, MP2) and the substrate bias power supply (vbp, vbn) supplied from the substrate bias control circuit. It is not good from the layout.

  Furthermore, the source or drain of the transistor can be connected to the drive power supply (VSS, VDD), and the substrate potential of the transistor can be connected to the substrate bias power supply.

  After the substrate bias control circuit outputs the control signal (vbp, vbn), it detects that the control signal (vbpr, vbnr) returned through the main circuit has reached a predetermined voltage, and outputs the detection signal (vbbenbr). By forming, the operation of the main circuit can be stabilized.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, it is possible to realize a semiconductor integrated circuit device such as a microprocessor that satisfies both the following problems: high speed and low power.
(1) It is easy to test the substrate bias control circuit.
(2) The malfunction of the CMOS circuit can be prevented by controlling the substrate bias.
(3) Area increase by controlling substrate bias can be minimized.
(4) The malfunction of the semiconductor integrated circuit device at the time of switching the substrate bias can be prevented.

  FIG. 1 shows a conceptual diagram of a semiconductor integrated circuit device 100 using a substrate bias control circuit of the present invention. VBC is a substrate bias control circuit. LOG is a main circuit under substrate bias control, and is composed of a logic circuit and a memory circuit. VBCC represents a standby control circuit for controlling the substrate bias control circuit. The I / O is an I / O circuit that interfaces with the outside of the semiconductor integrated circuit device 100. Here, wirings between circuit blocks that are not particularly necessary for substrate control are omitted. Reference numerals 109a and 109b denote substrate driving circuits.

  There are three types of power supplies, indicated by VDDQ, VDD, and VWELL, respectively. VSS and VSSQ indicate ground potentials with respect to VDD and VDDQ, respectively. VDDQ and VSSQ are power supplies for the I / O circuit, VDD and VSS are power supplies for the main circuit, and VWELL is a power supply for the substrate bias control circuit VBC.

  As shown in FIG. 1, VDD and VSS are also supplied to the substrate bias control circuit VBC. The substrate bias control circuit VBC has a built-in negative voltage generation circuit, and generates a negative voltage VSUB having a polarity opposite to that of VDD or VDDQ. In the following, VDDQ = VWELL = 3.3V, VDD = 1.8V, VSUB = -1.5V, and two types of power supply voltages are assumed.

  Reference numerals 101, 102, 103, and 104 denote pads of the semiconductor integrated circuit device 100, where 102 is a 3.3V VWELL power supply, 103 is a 1.8V VDD power supply, and 104 is supplied with 0V VSS (ground). Reference numeral 101 denotes a VSUB pad, which is used as a pad for outputting a negative voltage generated inside the substrate bias control circuit VBC. By monitoring the voltage of the pad 101 during the wafer test of the semiconductor integrated circuit device 100, a defect in the negative voltage generation circuit in the substrate bias control circuit VBC can be detected. Usually, pads 102 to 104 are bonded to the external pins of the semiconductor integrated circuit device 100, but 101 is not bonded to the external pins. In this way, the number of external pins can be saved by this test method.

  vbbenb is a substrate bias control start signal, and vbbenbr is a substrate bias control signal. On the other hand, reset is a reset signal and is connected to the reset signal of the semiconductor integrated circuit device 100. vbp is a PMOS substrate bias line, vbn is an NMOS substrate bias line, cbp is a PMOS substrate control line, cbn is an NMOS substrate control line, cbpr is a PMOS substrate control return line, and cbnr is an NMOS substrate control return line. The board control return lines cbpr and cbnr are return signals after passing through the main circuit of the cbp and cbn signals, and the nets are the same net. That is, the cbp and cbn drive voltages appear at cbpr and cbnr, respectively, after some delay. (See Figure 2 below). The substrate driving circuits 109a and 109b are connected to cbp, vbp, cbn, and vbn, respectively.

  FIG. 2 shows a method for connecting the six substrate bias control lines from vbp to cbnr in the main circuit LOG. VBCR is a return cell that internally connects the PMOS substrate control line cbp and the PMOS substrate control return line cbpr, and connects the NMOS substrate control line cbn and the NMOS substrate control return line cbnr.

  ncell represents a standard cell. Here, for simplicity, all ncells are shown as CMOS inverters composed of PMOS MP2 and NMOS MN2. Of course, more complex cells such as NAND gates and latches may be used independently. As shown in FIG. 2, the substrate potential of the MOS transistor constituting the ncell is connected to vbp for the PMOS and vbn for the NMOS.

  A swcell is a switch cell, and is composed of a substrate driving circuit (corresponding to 109a and 109b in FIG. 1) composed of PMOS MP1, NMOS MN1, and decoupling capacitors CP1 and CP2. The gate of MP1 is connected to cbp, the drain is connected to VBP, and the source is connected to VDD. Therefore, when cbp is lower than VDD-Vthp (Vthp is the absolute value of the threshold voltage of MP1), MP1 is turned on and vbp is driven to the VDD potential (1.8V).

  On the other hand, the gate of MN1 is connected to cbn, the drain is connected to VBN, and the source is connected to VSS (0V). Therefore, when cbn is higher than Vthn (Vthn is the absolute value of the threshold voltage of MN1), MN1 is turned on and vbn is driven to the VSS potential (0 V).

  In general, one or more large numbers of ncells are arranged. In addition, as for the swcell, one or more swcells are arranged. More complex circuits can be integrated on the main circuit LOG by increasing the number of ncells. Also, by increasing the number of swcells, vbp and vbn can be driven to VDD and VSS, respectively, with lower impedance when MP1 and MN1 are turned on.

  In addition, a decoupling capacitor can be incorporated in the space cell independently of the decoupling capacitor incorporated in the switch cell swcell. A space cell is, for example, a cell inserted in a space generated for securing a wiring area when standard cells nsell are arranged side by side. By incorporating a decoupling capacitor in the space cell as well, the capacity of the decoupling capacitor in the entire chip is increased, and power supply noise can be further reduced. Originally, since the space cell is an empty space only for the wiring layer, the area can be increased by inserting a capacitor here.

  MP1 and MN1 in swcell need to have a higher threshold value than the MOS transistor in ncell. This is because the substrate potential of the MOS transistor in ncell (connected to vbp or vbn, respectively) is independent of its source potential, but the substrate potential of MP1 and MN1 in swcell is always the same as the drain potential. This is because the substrate bias effect cannot be expected and the subthreshold leakage current flows.

  For example, for NMOS transistors MN1 and MN2, assuming that vbp = 3.3V, vbn = -1.5V, VDD = 1.8V, VSS = 0V, the source potential S, drain potential D, and substrate potential B of MN2 in the ncell are S = 0.0V, D = 1.8V, B = -1.5V, the threshold voltage of MN2 increases due to the substrate bias effect, and the subthreshold leakage current decreases. However, the source potential S, drain potential D, and substrate potential B of MN1 in swcell are S = 0.0V, D = -1.5VV, and B = -1.5V, respectively, and the threshold voltage changes due to the substrate bias effect. Does not appear. Therefore, a large subthreshold leakage current flows between VSS and vbn in MN1.

  To make the threshold voltage of MP1 and MN1 in swcell higher than the MOS transistor in ncell, change the implantation amount, change the gate length (L) size, or change the gate oxide film thickness. Can be realized. This method is not particularly limited, but here it is realized by changing the L size and the gate oxide film thickness. By this method, a high voltage MOS transistor used for a circuit in an input / output portion with respect to the outside of the microcomputer (hereinafter referred to as I / O circuit) can be diverted.

  FIG. 3 shows an embodiment of the I / O circuit. Here, only one bit is shown. The input / output circuit performs internal and external signals via the input / output terminal PAD. When SEL is 'L', PAD is an input terminal, and when SEL is 'H', it is an output terminal. LC1 is a level conversion circuit that converts a signal having an amplitude of VDD into a signal having an amplitude of VDDQ having a large amplitude. Therefore, the transistor between the level conversion cell LC1 and the input / output terminal PAD is composed of a thick oxide film transistor driven by VDDQ. Here, when PULL needs to be pulled up, it is set to 'L' and pulled up with a PMOS pull-up transistor. This PMOS is also composed of a thick oxide transistor.

  On the input side, an externally input signal having VDDQ amplitude is converted to VDD amplitude by an inverter composed of 110P and 110N. Therefore, these two transistors handle signals before level conversion, and are therefore formed of thick oxide transistors. The resistor 111R, the diodes 111D1 and 111D2, and the transistor 111 are input protection circuits. The diodes 111D1 and 111D2 may be composed of MOS transistors. The transistors in this input protection circuit are constituted by thick oxide film transistors.

  Since the thick oxide film transistor described above does not require a very high switching speed and the handled voltage is higher than VDD, the threshold voltage can be set high. It can be higher than the transistor used in ncell. As a result, the subthreshold leakage current when these thick oxide film transistors are off can be kept small. This thick oxide film transistor can be used for MP1 and MN1 constituting the switch cell swsell of FIG. In this way, it becomes unnecessary to newly complicate the process for MP1 and MN1.

  FIG. 4 shows the internal configuration of the substrate bias control circuit VBC. VBC80 is supplied with VDD and VSS, VBC30 is supplied with VWELL and VSS, VBC85 is supplied with VDD and VSUB, and VSUBGEN is supplied with VWELL, VDD and VSS. Therefore, the power supply voltage applied to the internal circuits of VBC30, VBC85, and VSUBGEN is 3.3V at most. By setting VDDQ = VWELL in this way, the power supplied to the I / O circuit is also 3.3V at VDDQ and VSSQ, so it is used for the devices used in the I / O circuit and the substrate bias control circuit. Devices can be shared.

  On the other hand, the power supply of VBC80 is 1.8V. Therefore, the signal line from VBC80 to VBC30, VBC85 uses a dual rail signal (balance signal used in a pair using a positive logic signal and a negative logic signal), and level conversion inside the VBC30, VBC85 (1.8V amplitude signal is 3.3. Converted to V amplitude signal).

  VBC80 is an interface circuit block between input signals cbpr, cbnr, vbbenb, reset and VBC30, VBC85 from the outside of the substrate bias control circuit VBC, VBC30 is a circuit block for controlling the substrate bias of the PMOS, and VBC85 is a substrate bias of the NMOS VSUBGEN is a negative voltage generating circuit block.

  FIG. 5 shows an example of operation waveforms. After the power supply VDDQ for the power supply I / O circuit and the power supply VWELL for the substrate bias control circuit VBC are turned on, the power supply VDD for the main circuit is turned on. As a result, the negative voltage generation circuit block VSUBGEN is activated and the negative voltage VSUB is generated. On the other hand, when the power supply VDD is turned on, the d_reset signal is asserted for a certain time. When this signal is asserted, the substrate bias control circuit does not pull the substrate bias of the main circuit (hereinafter, pulling the substrate or substrate bias means that the substrate bias is set to the VDD potential for the PMOS and the substrate bias for the NMOS. In addition, pulling the substrate or substrate bias means that the substrate bias is set to a potential higher than the VDD potential for PMOS, and the substrate bias is set to a potential lower than the VSS potential for NMOS. ) State, that is, the active state.

  In this state, the PMOS substrate bias line vbp = 1.8V, the NMOS substrate bias line vbn = 0V, the PMOS substrate control line cbp = 0V, and the NMOS substrate control line cbn = 1.8V. Since the substrate control return lines cbpr and cbnr are return signals of cbp and cbn signals, cbpr = cbp = 0V and cbnr = cbn = 1.8V.

  When the d_reset signal is negated after a certain period of time since the power supply VDD is turned on, the substrate bias is controlled by the vbbenb signal. When vbbenb is 3.3V, transition is made to the standby state where the board is pulled, and when vbbenb is 0V, transition is made to the active state where the board is not pulled.

  That is, when vbbenb transits from 0V to 3.3V, it transits to vbp = cbp = 3.3V and vbn = cbn = −1.5V. After that, the transition is made to cbpr = cbp = 3.3V and cbnr = cbn = −1.5V. vbbenbr becomes 3.3V when cbpr = 3.3V and cbnr = 0V. Therefore, when vbbenb transitions from 0V to 3.3V, it becomes 3.3V after a certain time has elapsed (after cbp or cbn return signals cbpr and cbnr return).

  When vbbenb transits from 3.3V to 0V, it transits to vbp = 1.8V, cbp = 0V, vbn = 0V, cbn = 1.8V. Then, after a certain time has elapsed, the transition is made to cbpr = cbp = 0V, cbnr = cbn = 1.8V, and vbbenbr = 0V. In this way, vbbenbr serves as a return signal for vbbenb. Furthermore, since the substrate potential is determined by the cbp and cbn potentials as described with reference to FIG. 2, monitoring the vbbenbr obtained from the cbp and cbn potentials can be equivalent to detecting the potential state of the substrate.

  FIG. 6 shows another example of the operation waveform. Only the parts different from FIG. 5 are shown. When cbp and cbn are controlled as shown in Fig. 6, the control circuit becomes slightly complicated, but when active, the voltage applied to the source and gate terminals of MP1 and MN2 in Fig. 2 can be increased, resulting in lower impedance. Can drive vbp and vbn. In this case, the amplitudes of cbp and cbn corresponding to the gate control signal are larger than the gate breakdown voltage of the substrate driving transistors MP1 and MN1. However, as can be seen from Fig. 6, by slowly changing cbp and cbn, the voltage between the gate terminal and drain terminal of MP1 and MN1 and the voltage between the gate terminal and source terminal becomes 3.3V at most, and keep it below the gate breakdown voltage. Can do.

  The detailed circuit diagram example of each circuit block is shown below. For the sake of simplicity, the following example of each circuit block shows a circuit example for realizing the waveform of FIG.

  FIG. 7 is a circuit diagram of the VBC80. 120 represents a 2-input NAND, 121 represents a 2-input AND having Schmitt characteristics, 122 represents an inverter, 123 represents NOR, 124 represents a buffer having Schmitt characteristics, and 125 represents a buffer having a differential output. 126 is a power-on reset circuit, and its output 127 is gradually charged from 0V to 1.8V after the power supply VDD is turned on. Therefore, the output of 121 outputs 0V for a certain time, and outputs 1.8V after a certain time. With this output, as shown in FIG. 5, the d_reset signal is asserted for a certain time when the power supply VDD is turned on. In FIG. 7, the power-on reset circuit 126 is a simple circuit using a resistor and a capacitor, but another circuit system may be used. In short, any device capable of detecting the power supply VDD until it stabilizes may be used.

  d_vbbenb, d_cbpr, and d_cbnr are signals obtained by making vbbenb, cbpr, and cbnr into dual rails, respectively, but the substrate control state is set to the active state during the power-on reset period. d_vbbenbr is a dual rail signal for making vbbenbr in FIG. 5, which is made from cbpr and cbnr.

  FIG. 8 is a circuit diagram of the VBC30. A level conversion circuit 130 generates a signal 133 of 3.3 V amplitude from VWELL to VSS from a dual rail signal of 1.8 V amplitude from VDD to VSS of d_vbbenb and d_reset. 133 becomes “L” in an active state or a power-on reset period.

  131 is also a level conversion circuit, which generates a signal 134 of 3.3V amplitude from VWELL to VSS from a dual rail signal of 1.8V amplitude from VDD to VSS of d_cbpr and d_reset. 134 becomes 0V when cbpr is 0V or during a power-on reset period. When 133 becomes 0V, vbp becomes a high impedance state, cbp becomes 0V, and cbpenbr becomes 0V. When cbp becomes 0V, MP1 in all swcells in the main circuit is turned on, and vbp is driven to 1.8V.

  Reference numeral 132 denotes a level conversion circuit that outputs the d_vbbenbr signal from the VBC 80 described in FIG. 7 as a vbbenbr signal having a 3.3 V amplitude.

  FIG. 9 shows the transition of cbp, but the output impedance of cbp changes in two stages. The cbp is driven by the inverter 135 controlled by the 133 signal. When 133 is 0V and 134 is 0V, the NMOS 136 is turned on and is also driven by the NMOS. Here, the gate width of the NMOS 136 is made sufficiently larger than the gate width of the NMOS in the inverter 135. When the state transits to the active state and 133 becomes 0V, the inverter 135 drives cbp to 0V. However, cbp is wired throughout the main circuit, and its load capacity is large. For this reason, cbp is slowly driven to 0V. The transition is detected by the transition of the cbp return signal cbpr, and the d_cbpr signal changes. As a result, 134 becomes 0 V, and the NMOS 136 is turned on. This drives cbp to 0V with low impedance. In this way, in the active state, cbp is driven to a low impedance, and the influence of noise due to the operation of the main circuit can be reduced. Also, when cbp is driven to 0V, MP1 in all swcells in the main circuit is turned on, but by driving cbp to 0V slowly as shown in Fig. 8 (B), all swcells in all swcells are turned on. MP1 simultaneous switching noise can be reduced.

  FIG. 10 is a circuit diagram of the VBC85. Reference numeral 140 denotes a level conversion circuit, which generates a signal 142 of 3.3 V amplitude from VDD to VSUB from a dual rail signal of 1.8 V amplitude from VDD to VSS of d_vbbenb and d_reset. 142 becomes 1.8V during the active state or power-on reset period.

  141 is also a level conversion circuit, and a signal 143 having a 3.3 V amplitude from VDD to VSUB is generated from a dual rail signal of 1.8 V amplitude from VDD to VSS of d_cbnr and d_reset. 143 becomes 1.8V when cbnr is 1.8V or during the power-on reset period. When 142 becomes 1.8V, vbn becomes a high impedance state and cbn becomes 1.8V. When cbn becomes 1.8V, MN1 in all swcells in the main circuit is turned on, and vbn is driven to 0V.

  FIG. 11 shows the state of the transition of cbn, but the output impedance of cbn changes in two stages, similar to cbp. The cbn is driven by the inverter 144 controlled by the 143 signal. When 142 is 1.8V and 143 is 1.8V, the PMOS 145 is turned on and is also driven by the PMOS 145. Here, the gate width of the PMOS 145 is made sufficiently larger than the gate width of the PMOS in the inverter 144. When transitioning to the active state and 142 becomes 1.8V, the inverter 144 drives cbn to 0V. However, cbn is wired throughout the main circuit, and its load capacity is large. For this reason, cbn is slowly driven to 0V. The transition is detected by the transition of the return signal cbnr of cbn, and the d_cbnr signal changes. As a result, 143 becomes 1.8V and PMOS 145 is turned on. This drives cbn to 1.8V with low impedance. In this way, in the active state, cbn is driven to a low impedance like cbp, and the influence of noise due to the operation of the main circuit can be reduced. Also, when cbn is driven to 1.8V, MN1 in all swcells in the main circuit is turned on, but by driving cbn to 1.8V slowly as shown in FIG. 11, MN1 in all swcells Simultaneous switching noise can be reduced.

  As is apparent from the above description, in the substrate bias control system of the present invention, the substrate drive impedance is the standby state in which the substrate is pulled in the active state (substrate drive by all swcells) in which the substrate is not pulled (substrate by VBC). It is smaller than (driving). Therefore, as described above, the transition to the active state in which the substrate is not pulled when the power is turned on can avoid the problem of an increase in through current between power sources and a latch-up problem caused by the substrate potential being unstable. In addition, when active, the main circuit operates to generate a lot of substrate noise. However, the substrate noise can be reduced by reducing the driving impedance of the substrate, and malfunction of the main circuit, latch-up, etc. can be prevented. .

  FIG. 12 shows the internal configuration of the negative voltage generation circuit VSUBGEN. It consists of three circuit blocks, VSUBSEN is a substrate bias sense circuit, PMP1 is a charge pump circuit 1, and PMP2 is a charge pump circuit 2. The substrate bias sense circuit VSUBSEN monitors the VSUB potential, monitors the active and standby states with the vbpenb signal, and controls PMP1 and PMP2 using the control signals pmp1enb and pmp2enb to satisfy VSUB = VDD + VSS-VWELL To do.

  PMP1 operates when the pmp1enb signal is asserted, and PMP2 operates when pmp2enb is asserted. The difference between PMP1 and PMP2 is the difference in pumping capacity. PMP1 has a larger pumping capacity than PMP2. Whether to use PMP1 or PMP2 is determined by the vbpenb signal. PMP2 is used in the active state, and PMP1 is used in the standby state.

  In the active state, the VSUB potential is used only in the substrate bias control circuit VBC, so that no current flows through the VSUB. For this reason, PMP2 having a small pumping capacity is used. Since the VSUB potential is supplied to the entire main circuit in the standby state, a current such as a junction current flows through VSUB. For this reason, PMP1 having a large pumping capacity is used.

  FIG. 13 shows a circuit diagram of the charge pump circuit 1 PMP1 of the present invention. OSC is a ring oscillator that oscillates only when pmp1enb is asserted and charges VSUB to a negative voltage.

  Figure 14 shows the addition of PMOS 162 and 163 to the charge pump circuit described in Ito Kiyoo, "VLSI LSI", Bafukan, p266. One cycle period of the ring oscillator using 160 and 161 PMOS It is a charge pump circuit that performs charge pump twice. In the present invention, NMOSs 164 and 165 are further added as shown in FIG. As a result, the influence of the threshold values of the PMOS 160 and 161 is eliminated, and a sufficiently deep VSUB can be obtained even at low voltage operation. When VWELL is 3.3V, only VSUB = -3.3 + vthp (vthp = the absolute value of the threshold of PMOS 160, 161) can be obtained with the configuration of FIG. 14, and VSUB = -2.3V at most. On the other hand, with the method of the present invention, VSUB = −3.3V can be obtained.

  Although a circuit diagram of the charge pump circuit 2 PMP2 is not particularly shown here, the capacitors CP3 and CP4 used as capacitors in FIG. 13 may be reduced to reduce the capacitance of the capacitors. Of course, other MOS sizes may be optimized in accordance with CP3 or CP4.

  FIG. 15 shows a circuit diagram of the substrate bias sense circuit VSUBSEN. VREFGEN is a reference voltage generation circuit, and an output of VREF = (VDD−VSS) / 2 is obtained by connecting NMOSs 150 and 151 in series. V1GEN is a VSUB potential sense circuit, which obtains an output of V1 = (VWELL-VSUB) / 2 by connecting NMOS transistors 152 to 155 in series. Only a potential difference of about 1 V is applied between the source and drain of each NMOS, and the gate length is further increased. As a result, the through current from VDD to VSS or VWELL to VSUB can be kept small. Further, since it operates in the saturation region, VREF or V1 can be obtained insensitive to variations. Furthermore, the present invention uses NMOS instead of PMOS. Since NMOS has better saturation characteristics than PMOS, VREF or V1 can be obtained insensitive to variations between NMOSs even if a potential of about 1 V is not applied between the source and drain.

AMP1, AMP2, and AMP3 are each a differential amplifier and constitute one differential amplifier. VREF and V1 are input to the differential amplifier composed of AMP1, AMP2, and AMP3. When VREF <V1, pmp1enb or pmp2enb is asserted. As a result, VSUB is charged in the negative voltage direction. When VREF> V1, pmp1enb or pmp2enb is negated. Since VSUB has some leakage current in the VSS, VWELL, and VDD directions, VSUB is discharged in the positive potential direction when both pmp1enb and pmp2enb are negated. By repeatedly asserting and negating pmp1enb or pmp2enb, V1 = VREF, that is, VSUB = VDD-VSS-VWELL is maintained. As described above, when vbpenb is 3.3V (in the standby state), pmp1enb is asserted, and when vbpenb is 0V (in the active state), pmp2enb is asserted.

  Further, there is a feedback path between AMP1 and AMP2, and the differential amplifier composed of AMP1, AMP2, and AMP3 has a hysteresis characteristic. Here, the hysteresis characteristic means that the differential point of the differential amplifier changes according to the output of the amplifier, and has a so-called Schmitt characteristic. This prevents pmp1enb or pmp2enb from repeatedly repeating assertion and negation near V1 = VREF, thereby preventing an increase in power consumption.

  Furthermore, the operating current of the differential amplifier from AMP1 to AMP3 is changed when vbpenb is asserted and negated. During standby in which vbp is asserted, VSUB of the main circuit is connected to VSUB, so that a large substrate capacity is connected. Therefore, VSUB changes slowly. Since AMP1 to AMP3 do not need to operate at high speed, the operating current can be limited. Thereby, the power consumption of AMP1 to AMP3 can be reduced. On the other hand, when vbp is negated and active, only the substrate bias control circuit VBC is connected to VSUB, so that a relatively small capacity is connected to VSUB. Therefore, VSUB changes quickly and AMP1 to AMP3 need to operate at high speed. Also, when active, not much power consumption. For this reason, the operating current of AMP1 to AMP3 is increased to operate at high speed.

  Hereinafter, a more detailed embodiment of the substrate bias feeding method will be described.

  FIG. 16 shows a layout example of ncell and swcell. Swcells are arranged continuously in the vertical direction (Y direction). The cell height of swcell and ncell is unified to the same height, and the interval L in the horizontal direction (X direction) between swcell and swcell is made variable within a certain value. Of course, the interval may be constant, but the degree of freedom of layout increases if it is variable to some extent. In any case, the interval L may be determined in consideration of the following items.

(1) Power line impedance
(2) Migration of power supply wiring
(3) Substrate noise generated in vbp and vbn when ncell operates FIG. 17 shows an example layout of ncell. As in the case of FIG. 2, an inverter is taken as an example. vbp, vbn, VDD, and VSS are supplied with power by four parallel first layer metal wires (hereinafter referred to as M1). vbp and vbn are also fed by the surface high concentration layer. H is the cell height and represents the basic repeating unit in the vertical direction. Based on this height, they are arranged mirror-symmetrically in the vertical direction. As a result, vbp and vbn can be shared with upper and lower adjacent ncells, and the area can be reduced.

  FIG. 18 shows a cross-sectional view taken along the line AB of FIG. N-well is an N-type well for forming MP2, and P-well is a P-type well for forming MN2. Deep-N is an N-type well located deeper than N-well and P-well, and has a so-called triple well structure.

  FIG. 19 shows a layout example of swcell. The height of the cell is H like ncell, and the power lines of vbp, vbn, VDD and VSS by M1 are in the same position as ncell. As shown in FIG. 16, swcells are continuous in the vertical direction and are arranged at intervals within a certain interval in the horizontal direction. With this arrangement, the power reinforcing line can be arranged at the location of the swcell. In FIG. 19, the second-layer metal wiring (hereinafter referred to as M2) wired in parallel in the vertical direction is the two power reinforcing lines. Between the two power reinforcing lines, two vbp and vbn reinforcing lines and two cbp and cbn are arranged in parallel. The four substrate bias control lines having relatively high impedance can be protected from external noise by the power reinforcing lines VDD and VSS at both ends.

  MP1 is formed by being separated into six transistors, the gate is connected to cbp, the drain is connected to vbp, and the source is connected to VDD. Further, MN1 is formed by being separated into three transistors, the gate is connected to cbn, the drain is connected to vbn, and the source is connected to VSS. The decoupling capacitors CP1 and CP2 are separated into two transistors, respectively, and are formed at both ends of MP1 and MN1, and the capacitance is made using MOS gate capacitance.

  The ratio of the sizes of the decoupling capacitors CP1 and CP2 and the sizes of MP1 and MN1 is not particularly limited. In an extreme example, one or both of the decoupling capacitors CP1 and CP2 may be eliminated. Increasing the decoupling capacitor can reduce power supply noise. On the other hand, if MP1 and MN1 are increased, the substrate bias can be connected to the power source with a lower impedance when the microcomputer is in a normal state, and it is more resistant to noise and less likely to latch up.

  The VIA hole between the VDD line of M1 and the VDD line of M2 and the VIA hole between the VSS line of M1 and the VSS line of M2 are omitted for simplicity, but VIA is at the intersection of each wiring. A hole may be provided.

  FIG. 20 shows a cross-sectional view taken along the line AB of FIG. Similarly to FIG. 18, P-well is a P-type well for forming MN1, Deep-N is an N-type well deeper than P-well, and has a so-called triple well structure. . Here, the VIA hole between the VSS line of M1 and the VSS line of M2 omitted in FIG. 19 is also illustrated. As described in the explanation of FIG. 2, a thick oxide film transistor is used for MN2 to increase the threshold value.

  FIG. 21 shows a more specific example of the wiring method of the power supply wirings VDD, VSS and the substrate bias control lines vbp, vbn, cbp, cbn. This figure is obtained by adding the above wiring to FIG. In the horizontal direction, VDD, VSS, vbp, and vbn wired by M1 are wired in parallel. As described in FIG. 17, vbp is shared by two upper and lower cells, and VDD is wired in parallel above and below the cell. In addition, vbn is also shared by two upper and lower cells, and VSS is wired in parallel above and below. Of course, it is better to make VDD and VSS thicker than vbp and vbn.

  As explained in Fig. 19, VDD, VSS, vbp, vbn, cbp, cbn wired in M2 are wired on swcell in the vertical direction, and VDD, VSS, vbp at the intersection of M1 and M2, respectively. , Vbn are connected in mesh.

  FIG. 22 shows how the power supplies VDD and VSS are reinforced. Power supply lines VDD and VSS formed of a fourth metal wiring layer (hereinafter referred to as M4) and a fifth metal wiring layer (hereinafter referred to as M5) are further wired in a mesh shape in the basic repeating unit of FIG.

  VDD and VSS wired by M4 are wired above M2 VDD and VSS that are wired vertically, but a third metal wiring layer (hereinafter referred to as M3) is used to connect both. is required. If this connection is performed on all swcells, M3 is wired in the vertical direction, and there is a problem that the path in the horizontal direction of M3 is lost.

  In FIG. 22, the connection of the power lines M2 and M4 is performed only on every three swcells indicated by swcell2 or swcell3. By doing so, it is possible to secure a wiring path in the horizontal direction of M3.

  The power line of M5 is performed only on every six swcells indicated by swcell3, and is connected at the intersection with the power line of M4 on swcell3.

As described above, the impedance of the power supply lines VDD and VSS can be lowered by reinforcing the power supply mesh having a fine pitch of M1 and M2 with the power supply mesh having a rough pitch of M4 and M5.

  In FIG. 22, the power supply lines in the vertical direction of M4 are wired on all swcells, but may be wired roughly every two or three in the horizontal direction. Although the impedance of the power supply line becomes high, the M4 vertical path can be secured.

  FIG. 23 shows the relationship between the swcell arrangement shown in FIG. 22 and the wells. P-type wells P-wells and N-type wells are alternately arranged in a strip shape, and two ncells are arranged to share one well.

  FIG. 24 shows a layout example of the memory cell swcell and the power supply line. Although word lines and bit lines are not shown here, word lines are arranged in the horizontal direction and bit lines are arranged in the vertical direction. The power lines of the memory mat run in the horizontal direction in the memory cell, but they are reinforced by the power lines 200, 201, 202 at both ends of the memory mat. Reference numeral 203 denotes a power supply line for supplying power to each word driver and word decoder, and 204 denotes a power supply line for supplying power to each sense amplifier. The swcell is arranged on the above 200 to 204 power lines as shown in FIG.

Usually, only one or two of a plurality of word drivers and word decoders operate simultaneously. Therefore, since the amount of substrate noise does not increase so much, only two swcells are arranged at both ends of 203 as shown in the figure.

  Conversely, a large number of sense amplifiers operate simultaneously. However, the number of nodes in the sense amplifier that have a transition from 'L' to 'H' is substantially the same as the number of nodes to transition from 'H' to 'L'. Therefore, even if many sense amplifiers operate simultaneously, the substrate noise does not increase so much. Here, as shown in the figure, swcells are arranged in addition to both ends of the power supply line 204 to reduce substrate noise.

  In addition, there are various methods for arranging swcells. However, the larger the proportion of devices operating on the same well, the more swcells may be arranged on the well. In the diffusion layer in one well, the potential change of the diffusion layer is expressed as | NH-NL | / NA (NH = area of the diffusion layer excluding the diffusion layer connected to the power source, NH = potential is' H The area of the diffusion layer that changes from 'to' L ', NL = the area of the diffusion layer where the potential changes from' L 'to' H '), and based on that, the number of swcells, the spacing between swcells, L, and The size of the MOS transistor in the swcell can be determined. In short, the value of | NH-NL | / NA should be as small as possible.

  For example, in the case of a circuit having a regular data flow such as a data path, the data flow direction of the data path may be set to the X direction in FIG. Since cells operating simultaneously are distributed in a plurality of wells, the above | NH-NL | / NA becomes small.

  FIG. 25 shows a sectional view of the semiconductor integrated circuit device 100 of the present invention. As shown in FIG. 18, N shown by 302, 304, 306, 308, 310 is the same as the N-well and is an N-type well for forming a PMOS transistor, 301, 303, 305, 307, 309, 311. P indicated by is the same as P-well and is a P-type well for forming an NMOS transistor. Deep-N indicated by 312 and 313 is an N-type well deeper than N and P, and has a so-called triple well structure.

  Deep-N 312 and 313 are electrically separated by 310 p-substrate and 307 P-well. Therefore, the substrate potential of the MOS transistor A formed on 302, 304, 306, 308, 310 and the substrate potential of the MOS transistor B formed on 301, 303, 305, 307, 309, 311 are independent. A potential can be applied. In addition, it is possible to reduce the influence of noise generated in the MOS transistor A on the MOS transistor B.

  FIG. 26 shows the Deep-N structure of the semiconductor integrated circuit device of the present invention. The CPG is a clock control unit and includes an analog circuit such as a PLL (phase locked loop). TLB is an address conversion unit, CACHE is a cache memory, CPU is a central processing unit, FPU is a floating point arithmetic unit, LOG1 is random logic 1, LOG2 is random logic 2, and PAD is an I / O unit. In this way, each circuit block is formed on a different Deep-N.

  As described with reference to FIG. 25, it is possible to reduce the noise generated in each circuit block from affecting other blocks. For example, PAD generates a large noise because an external pin is driven with an amplitude larger than an internal signal amplitude. This noise can be prevented from affecting analog circuits such as CPG.

  Further, since the substrate potential can be given independently, for example, a circuit that does not perform substrate control by vbp, vbn, cbp, cbn can be arranged in LOG2. That is, a circuit in which the power supply and the substrate potential are connected (VDD = vbp, VSS = vbn) can be arranged.

  FIG. 27 shows a guard band arranged between Deep-N and Deep-N. As shown in FIG. 27, a guard band gband1 is arranged between Deep-N and Deep-N.

  FIG. 28 shows a cross-sectional view. P well 307 between Deep-N is grounded to VSS potential through P + diffusion layer 314. Noise propagation between Deep-N can be further reduced. For example, substrate noise generated in the MOS on the P-well 305 propagates as noise to the Deep-N 312 due to capacitive coupling because the impedance of the Deep-N 312 is not so low. Similarly, this noise tends to propagate to the p substrate 300 by capacitive coupling, but the p substrate is fixed to the ground potential at a low impedance by a guard band. Therefore, the noise appearing on the p substrate is reduced. In this way, the propagation of noise from the MOS transistors formed on 302, 304, 306, 308, 310 to the MOS transistors formed on 301, 303, 305, 307, 309, 311 is reduced. The

  FIG. 29 shows the layout image of cbp and cbpr on the semiconductor integrated circuit and the position of the return cell VBCR in FIG. Since cbn and cbnr can be made in the same manner, they are omitted here. As shown in FIG. 21, vbp and vbn are wired like a mesh by arranging swcells, but cbp and cbn are not wired like a mesh but wired like a stripe. FIG. 29 shows a state in which the stripe-like wirings that are wired by arranging the swcells are connected so as to be shunted. The return cell is a cell for returning the input cbp and cbn to the substrate bias control circuit VBC as cbpr and cbnr, and the return timing is within each swcell, compared to the arrival timing of the ccell of the slowest ccell propagation time It is arranged so that cbpr can be returned at a later timing. For example, it may be arranged at a position farthest from the substrate bias control circuit VBC.

  In the above embodiments, the potential applied to the substrate bias is 1.8 V and 0.0 V during active and 3.3 V and −1.5 V during standby, but is not particularly limited. An appropriate potential may be applied to the substrate bias when active to adjust the threshold variation of the MOS transistor.

  Further, the main circuit may be divided into a plurality of circuit blocks, and control circuits such as VBC30 and VBC85 may be individually provided in each circuit block, and an active state and a standby state may be provided independently. If each circuit block is controlled, a circuit block that is not operating can be set in a standby state, power consumption can be controlled more finely, and power consumption can be reduced. Depending on the circuit block, it may not be necessary to pull the substrate bias even in the standby state. This is the case, for example, when the circuit block is composed of a high threshold MOS transistor and the subthreshold leakage current can be ignored.

  In the above embodiment, the threshold value of the MOS transistor is set to a low threshold value when the circuit operation mode is active, and is set to a high threshold value when the circuit is in the standby mode. To page 71, 1996 (1996 IEEE SPECTRUM, pp66-71), the substrate bias may be set so as to be a high threshold during the IDDQ test.

  At this time, it is desirable that the substrate potential applied to the substrate during the IDDQ test be larger than the substrate potential applied during standby. That is, a higher potential is applied to the PMOSFET than at the standby time, and a lower potential is applied to the NMOSFET. In this way, the subthreshold leakage current that flows during the IDDQ test can be further reduced, so that the accuracy of fault detection is improved.

  In order to enable such an operation, the VWELL potential is raised from 3.3 V to 4.0 V, for example, and the VSUB potential is lowered from -1.5 V to -2.2 V during the IDDQ test. In terms of circuit, it is necessary to prevent a through current from flowing even if the VWELL potential is different from the VDDQ potential. For this purpose, for example, all the signals to the substrate bias control circuit VBC are converted to VWELL potential or VSUB potential after being lowered in level by VBC80. This can be realized by providing a voltage buffer.

  In the above embodiments, the substrate structure is assumed to be a triple well structure, but the structure is not particularly limited. A double well structure having a so-called twin tab structure or an SOI (Silicon on insulator) structure may be used.

  Further, as shown in FIGS. 17, 19, and 21, in the present invention, the substrate bias power supply in the cell is performed by M1, but this structure is not particularly limited. See, for example, 1997 Symposium on VLSI circuits Digest of Technical Papers, pp. 95-96. As described above, power may be supplied by a diffusion layer or a silicided diffusion layer.

1 is a block diagram of a semiconductor integrated circuit device of the present invention. The circuit diagram which illustrated the content of the main circuit in detail. A schematic diagram of the I / O circuit. Each circuit block diagram of a substrate bias control circuit. The figure showing the operation waveform of a substrate bias control circuit. FIG. 6 is a waveform diagram illustrating an embodiment different from FIG. 5 of operation waveforms of the substrate bias control circuit. The circuit diagram of VBC80. The circuit diagram of VBC30. The operation waveform diagram of VBC30. Circuit diagram of VBC85 Operation waveform diagram of VBC85. Each circuit block diagram of VSUBGEN. The circuit diagram of a charge pump. The circuit diagram of a charge pump. Circuit diagram of VSUBSEN. The layout of the switch cell of the present invention. Standard cell layout diagram. FIG. 18 is a cross-sectional view of FIG. The layout diagram of a switch cell. FIG. 20 is a cross-sectional view of FIG. 19. Power supply wiring and wiring diagram of vbp, vbn, cbp, cbn. The wiring diagram of a power supply reinforcement wire. The block diagram of a well. FIG. 3 is a layout diagram of switch cells in a memory circuit. Sectional drawing of a well. Layout diagram of Deep-N well. Layout diagram of Deep-N well and guard band. FIG. 28 is a cross-sectional view of FIG. Layout of cbpr, cbnr, and VBCR.

Explanation of symbols

VBC substrate bias control circuit
LOG main circuit
VBCC standby control circuit
I / OI / O circuit
vbbenb board bias control start signal
vbbenbr Substrate bias control signal
vbp PMOS substrate bias line
vbn NMOS substrate bias line
cbp PMOS substrate control line
cbn NMOS substrate control line
cbpr PMOS substrate control return line
cbnr NMOS substrate control return line
AMP1, AMP2 differential amplifier
AMP3 Schmitt input differential amplifier
VBCR return cell
swcell switch cell
ncell Standard cell
P-sub P substrate
PLL phase locked loop
CPG clock controller
TLB address converter
CACHE cache memory
CPU central processing unit
FPU floating point unit
PAD I / O section

Claims (8)

A voltage generation circuit capable of taking a first voltage and generating a second voltage different from the first voltage and outputting the second voltage from an output node;
The voltage generating circuit includes a first capacitor including a first node and a second node, a first clock signal transmitted to the first node of the first capacitor, and a second node of the first capacitor. Including a first charge pump circuit for taking in via
The first charge pump circuit includes a first PMOS transistor coupled to the second node of the first capacitor and an output node of the voltage generation circuit;
A semiconductor integrated circuit device comprising: a first NMOS transistor coupled to the second node of the first capacitor and an output node of the voltage generation circuit ;
A first logic circuit including a second PMOS transistor;
A second logic circuit including a second NMOS transistor;
The substrate bias of the first PMOS transistor is electrically separated from the substrate bias of the second PMOS transistor,
The first PMOS transistor includes a first N-type well formed in the first deep N-type well,
The first NMOS transistor includes a first P-type well formed in the first deep N-type well,
The second PMOS transistor includes a second N-type well formed in the second deep N-type well,
The first deep N-type well is electrically isolated from the second deep N-type well,
The voltage generation circuit includes a second capacitor including a first node and a second node, a second clock signal transmitted to the first node of the second capacitor, and a second node of the second capacitor. A second charge pump circuit that takes in via
The second charge pump circuit includes a third PMOS transistor coupled to the second node of the second capacitor and an output node of the voltage generation circuit;
A semiconductor integrated circuit device comprising: a third NMOS transistor coupled to the second node of the second capacitor and an output node of the voltage generation circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein a guard band set at a predetermined potential is formed between the first deep N-type well and the second deep N-type well . 2. The semiconductor integrated circuit device according to claim 1 , wherein the second clock signal is obtained by logically inverting the first clock signal . A gate of the first PMOS transistor is coupled to a second node of the first capacitor;
A gate of the third PMOS transistor is coupled to a second node of the second capacitor;
A gate of the first NMOS transistor is coupled to a second node of the second capacitor;
2. The semiconductor integrated circuit device according to claim 1 , wherein a gate of the second NMOS transistor is coupled to a second node of the first capacitor . 2. The semiconductor integrated circuit device according to claim 1 , wherein the second voltage generated by the voltage generation circuit is supplied to the second P-type well . A plurality of PMOS transistors; a plurality of NMOS transistors; a substrate on which a first voltage is supplied to form the plurality of PMOS transistors; and a substrate on which a second voltage is supplied to form the plurality of NMOS transistors. Logic circuit;
A voltage generation circuit that takes in the first voltage and generates the second voltage;
A substrate bias sense circuit, and
The substrate bias sense circuit includes a plurality of first MOS transistors connected in series between the first voltage and the second voltage, and a first intermediate potential between the first voltage and the second voltage. A sense circuit for generating
A third voltage, which is a voltage between the first voltage and the second voltage, and a fourth voltage, which is a voltage between the third voltage and the second voltage, are connected in series. A plurality of second MOS transistors, and a reference voltage generating circuit for generating a second intermediate potential between the third voltage and the fourth voltage;
A comparison circuit that compares the first intermediate potential with the second intermediate potential and outputs a control signal for controlling the operation of the voltage generation circuit based on the comparison result;
The comparison circuit includes a first differential amplifier to which the first intermediate potential and the second intermediate potential are input;
A second differential amplifier to which the second intermediate potential and the output signal of the first differential amplifier are input;
A third differential amplifier to which an output signal of the first differential amplifier and an output signal of the second differential amplifier are input;
The semiconductor integrated circuit device, wherein the control signal is output from the third differential amplifier . The semiconductor integrated circuit device according to claim 6 , wherein the comparison circuit has a hysteresis characteristic . 7. The semiconductor integrated circuit device according to claim 6 , wherein the first MOS transistor is an NMOS transistor, and the second MOS transistor is an NMOS transistor .

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