JP4800253B2 - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
- Publication number
- JP4800253B2 JP4800253B2 JP2007098458A JP2007098458A JP4800253B2 JP 4800253 B2 JP4800253 B2 JP 4800253B2 JP 2007098458 A JP2007098458 A JP 2007098458A JP 2007098458 A JP2007098458 A JP 2007098458A JP 4800253 B2 JP4800253 B2 JP 4800253B2
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- Prior art keywords
- support plate
- electrode pad
- layer
- insulating layer
- wiring board
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 238000005530 etching Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 91
- 238000000034 method Methods 0.000 description 40
- 238000010586 diagram Methods 0.000 description 15
- 239000011229 interlayer Substances 0.000 description 11
- 239000000126 substance Substances 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000032798 delamination Effects 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0376—Etching temporary metallic carrier substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
11,21,31,101,201 電極パッド
12,22,32,102,104,106,108 絶縁層
103,105,107 導電パターン
Claims (5)
- 支持板上に金属からなる電極パッドを形成する第1の工程と、
前記支持板が、前記電極パッドに接する突起部を有する形状となるように前記支持板を
エッチングする第2の工程と、
前記電極パッドを覆う絶縁層を前記支持板の表面に形成する第3の工程と、
前記電極パッドに接続される導電パターンを前記絶縁層の表面に形成する第4の工程と、
前記支持板を除去する第5の工程と、を有することを特徴とする配線基板の製造方法。 - 前記電極パッドと前記支持板は異なる金属材料により構成され、前記第2の工程では、
前記電極パッドと前記支持板のうち、該支持板が選択的にエッチングされることを特徴と
する請求項1記載の配線基板の製造方法。 - 前記支持板と前記電極パッドの間に、該支持板と実質的に同じ材料により構成される高さ調整パッドを形成する工程をさらに有することを特徴とする請求項1または2に記載の配線基板の製造方法。
- 前記第5の工程では、ウェットエッチングにより、前記高さ調整パッドが前記支持板とともに除去されることを特徴とする請求項3記載の配線基板の製造方法。
- 前記第2の工程では、前記突起部がテーパー状となるように前記支持板がエッチングされることを特徴とする請求項1乃至4のいずれか1項記載の配線基板の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007098458A JP4800253B2 (ja) | 2007-04-04 | 2007-04-04 | 配線基板の製造方法 |
KR1020080030604A KR101392950B1 (ko) | 2007-04-04 | 2008-04-02 | 배선기판 및 배선기판 제조방법 |
CN2008100899017A CN101281872B (zh) | 2007-04-04 | 2008-04-03 | 布线基板和布线基板的制造方法 |
US12/062,018 US7582551B2 (en) | 2007-04-04 | 2008-04-03 | Wiring substrate and wiring substrate manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007098458A JP4800253B2 (ja) | 2007-04-04 | 2007-04-04 | 配線基板の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011138089A Division JP5468572B2 (ja) | 2011-06-22 | 2011-06-22 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008258373A JP2008258373A (ja) | 2008-10-23 |
JP4800253B2 true JP4800253B2 (ja) | 2011-10-26 |
Family
ID=39826237
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007098458A Active JP4800253B2 (ja) | 2007-04-04 | 2007-04-04 | 配線基板の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7582551B2 (ja) |
JP (1) | JP4800253B2 (ja) |
KR (1) | KR101392950B1 (ja) |
CN (1) | CN101281872B (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
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US9049807B2 (en) * | 2008-06-24 | 2015-06-02 | Intel Corporation | Processes of making pad-less interconnect for electrical coreless substrate |
JP5101451B2 (ja) | 2008-10-03 | 2012-12-19 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP5269563B2 (ja) * | 2008-11-28 | 2013-08-21 | 新光電気工業株式会社 | 配線基板とその製造方法 |
JP5479073B2 (ja) * | 2009-12-21 | 2014-04-23 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP2012009586A (ja) * | 2010-06-24 | 2012-01-12 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置及び配線基板の製造方法 |
JP2012033875A (ja) * | 2010-06-30 | 2012-02-16 | Canon Inc | 積層型半導体装置 |
JP5675443B2 (ja) * | 2011-03-04 | 2015-02-25 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
TWI562295B (en) | 2012-07-31 | 2016-12-11 | Mediatek Inc | Semiconductor package and method for fabricating base for semiconductor package |
US9177899B2 (en) | 2012-07-31 | 2015-11-03 | Mediatek Inc. | Semiconductor package and method for fabricating base for semiconductor package |
US10991669B2 (en) | 2012-07-31 | 2021-04-27 | Mediatek Inc. | Semiconductor package using flip-chip technology |
CN102867759B (zh) * | 2012-08-17 | 2015-04-29 | 日月光半导体制造股份有限公司 | 半导体封装构造及其制造方法 |
TWI527173B (zh) * | 2013-10-01 | 2016-03-21 | 旭德科技股份有限公司 | 封裝載板 |
FR3011850B1 (fr) | 2013-10-15 | 2018-04-06 | Cfl Biotech | Vaccin therapeutique contre le cancer a base de proteines de stress rendues immunogenes |
US9478472B2 (en) * | 2014-05-19 | 2016-10-25 | Dyi-chung Hu | Substrate components for packaging IC chips and electronic device packages of the same |
JP6626687B2 (ja) * | 2015-10-28 | 2019-12-25 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
JP6608108B2 (ja) | 2015-12-25 | 2019-11-20 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
CN110545637B (zh) * | 2018-05-29 | 2021-08-24 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制作方法 |
CN110545635B (zh) * | 2018-05-29 | 2021-09-14 | 鹏鼎控股(深圳)股份有限公司 | 多层电路板的制作方法 |
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JP4819304B2 (ja) | 2000-10-18 | 2011-11-24 | 日本電気株式会社 | 半導体パッケージ |
JP4087080B2 (ja) * | 2001-05-17 | 2008-05-14 | 株式会社日立製作所 | 配線基板の製造方法およびマルチップモジュールの製造方法 |
US7071024B2 (en) * | 2001-05-21 | 2006-07-04 | Intel Corporation | Method for packaging a microelectronic device using on-die bond pad expansion |
US6988312B2 (en) | 2001-10-31 | 2006-01-24 | Shinko Electric Industries Co., Ltd. | Method for producing multilayer circuit board for semiconductor device |
JP3666591B2 (ja) | 2002-02-01 | 2005-06-29 | 株式会社トッパンNecサーキットソリューションズ | 半導体チップ搭載用基板の製造方法 |
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JP4445777B2 (ja) | 2004-02-27 | 2010-04-07 | 日本特殊陶業株式会社 | 配線基板、及び配線基板の製造方法 |
WO2005093817A1 (ja) * | 2004-03-29 | 2005-10-06 | Nec Corporation | 半導体装置及びその製造方法 |
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2007
- 2007-04-04 JP JP2007098458A patent/JP4800253B2/ja active Active
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2008
- 2008-04-02 KR KR1020080030604A patent/KR101392950B1/ko active IP Right Grant
- 2008-04-03 US US12/062,018 patent/US7582551B2/en active Active
- 2008-04-03 CN CN2008100899017A patent/CN101281872B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US7582551B2 (en) | 2009-09-01 |
CN101281872A (zh) | 2008-10-08 |
CN101281872B (zh) | 2011-08-17 |
KR20080090308A (ko) | 2008-10-08 |
JP2008258373A (ja) | 2008-10-23 |
US20080246146A1 (en) | 2008-10-09 |
KR101392950B1 (ko) | 2014-05-09 |
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