JP4890233B2 - Signal conversion circuit - Google Patents

Description

  The present invention is applied to a drive control circuit for a motor, a luminance control circuit for a backlight, and the like, and is a signal conversion circuit for obtaining a voltage signal having a voltage value corresponding to the duty ratio from a PWM signal. The present invention relates to a configuration of a signal conversion circuit that requires no element and can be easily integrated.

  For example, when it is desired to control the motor speed or the illuminance of the LED linearly, (1) a reference signal corresponding to the target value of the controlled variable is generated, and (2) the reference value or the reference of the detected value of the controlled variable A process is performed in which a PWM signal having a duty ratio corresponding to a deviation from the value is generated, and (3) the motor or LED is controlled by a voltage or current corresponding to the duty ratio of the PWM signal. Here, for example, a voltage and a current corresponding to the duty ratio of the PWM signal are generated in a signal conversion circuit or a current source combined therewith. There are several examples of signal conversion circuits that convert PWM signals into voltage signals, but in general, an RC low-pass filter with the simplest configuration is often used. (For example, see Patent Document 2, Patent Document 3, and Patent Document 4)

FIG. 4 shows an example of the configuration of an RC low-pass filter used as a signal conversion circuit. 4 has a configuration in which a resistor 203 is connected in series between an input terminal 201 and an output terminal 202, and a resistor 204 and a capacitor 205 are connected in parallel between the output terminal 202 and the ground. . When the PWM signal S _PWM is supplied to the input terminal 201 of the low-pass filter having such a configuration, a DC voltage signal S _DC substantially equal to the average value of the PWM signal S _PWM appears at the output terminal 202. Assuming that the low level of the pulse is zero volts, the average value of the PWM signal S _PWM is obtained by the product of the high level voltage value and the duty ratio. Therefore, the DC voltage signal S _DC has a magnitude corresponding to the duty ratio of the PWM signal S _PWM .

When a DC voltage is generated from the PWM signal by the RC low-pass filter, a ripple is generated in the DC voltage based on alternating low and high levels of the PWM signal. Conventionally, with respect to this problem, the ripple of the DC voltage signal has been reduced to a level that can be ignored by setting the cutoff frequency of the RC low-pass filter to about one-hundredth of the frequency of the PWM signal.
Specifically, assuming that the frequency of the PWM signal is 20 kHz, the cutoff frequency of the RC low-pass filter is set to 0.2 kHz. Here, when the RC low-pass filter has a configuration as shown in FIG. 4, in order to set the cutoff frequency to approximately 0.2 kHz, elements having a resistance value of 16 kΩ are provided in the resistors 203 and 204, and a capacitor is provided in the capacitor 205. It is necessary to use an element having a value of 0.1 μF.
JP 11-356077 A Japanese Patent Laid-Open No. 06-037641 JP 06-188738 A JP 2000-307427 A

The signal conversion circuit using the RC low-pass filter has a simple configuration and is easy to design. However, it is very difficult to form all elements having large capacitance values and resistance values as in the above specific example on an integrated circuit having a limited area. For this reason, the signal conversion circuit using the RC low-pass filter cannot be practically configured integrally with the functional circuits before and after the integrated circuit.
Therefore, an object of the present invention is to provide a signal conversion circuit that does not require a large-capacity element and can be easily integrated.

In order to solve the above problems, the present invention provides a signal conversion circuit for receiving an input signal subjected to pulse width modulation and obtaining an output signal having a voltage value corresponding to the duty ratio of the input signal. A first counter unit that generates a first signal according to a level period; a second counter unit that generates a second signal according to a low level period of an input signal; a first signal; An adder that generates a third signal corresponding to a period of approximately one cycle of the input signal from the signal, a first converter circuit that generates a fourth signal having a voltage value corresponding to the third signal, A second converter circuit that generates a fifth signal having a voltage value corresponding to the signal of
Here, the output signal is obtained by making the magnitude of the fifth signal proportional to a positive coefficient in the high level period of the input signal and proportional to a negative coefficient in the period of the input signal. And

Since the high-level and low-level periods of the PWM signal are counted and the obtained signal is processed to obtain a DC voltage signal, a capacitor having a large capacitance value and a resistor having a large resistance value are not required. Integrated circuit becomes easy.
Additionally, even if the high level voltage value and the low level voltage value of the PWM signal are different, the same DC voltage signal can be obtained for the PWM signal having the same duty ratio.

First and second count circuits and an edge detection circuit are provided, and a PWM signal is supplied to two count circuits and an edge detection circuit, and a clock signal and a signal from the edge detection circuit are further supplied to the two count circuits. Configure.
A first shift register and a second shift register are provided at the subsequent stage of the first and second count circuits, respectively. The first shift register is configured to count the number of pulses of the clock signal during a period in which the PWM signal detected by the first count circuit is at a high level, and the second shift register is configured by the second count circuit. The number of pulses of the clock signal during the period in which the detected PWM signal is at a low level is counted.

A first register and a second register are provided after the first shift register and the second shift register, respectively. The first register is configured to store a signal representing the number of pulses in the high level period generated by the first shift register in response to a signal from the edge detection circuit, and the second register is configured to detect the edge A signal representing the number of pulses in the low level period generated by the second shift register in accordance with the signal from the circuit is stored.
An adder and a third register are provided, and signals representing the number of pulses in the high level period and the low level period stored in the first and second registers are added in the adder, and 1 obtained by the addition process A signal representing the number of pulses in the period is stored in the third register.

A first D / A converter circuit driven with a constant current is provided, and a signal having a voltage value corresponding to the signal stored in the third register is generated.
A current source circuit including an error amplifier, a control transistor, and a resistor is provided, and a current corresponding to the voltage signal generated in the first D / A converter circuit is supplied.
A reference current source is provided in series with the control transistor, and a current signal corresponding to a difference between a constant value of the reference current and a current flowing through the current source circuit is obtained.

A second D / A converter circuit driven by a variable current is provided and configured to generate a signal having a voltage value corresponding to the signal stored in the first register, and according to the previous current signal. The driving current is supplied. Here, it is assumed that the second D / A converter circuit changes the magnitude of the voltage signal generated there according to the magnitude of the drive current.
As a result, the magnitude of the voltage signal generated in the second D / A converter circuit is proportional to the number of pulses in the high level period by a positive coefficient and proportional to the number of pulses in one cycle by a negative coefficient. Then, an output signal by signal conversion is obtained from the output side of the second D / A converter circuit.

FIG. 1 shows the configuration of a signal conversion circuit according to the present invention which does not require a large capacity element and can be easily integrated. The signal conversion circuit according to the present invention has the following configuration. The parts shown in FIGS. 1A and 1B are only divided for the sake of convenience, and are actually combined at positions 1 and 1 ′ and 2 and 2 ′. It shall be.
The input terminal 101 is connected to each input side of the first count circuit 104, the edge detection circuit 112, and the second count circuit 108 via the waveform shaping circuit 103. Here, each control input and each clock input of the first count circuit 104 and the second count circuit 108 are connected to an edge detection circuit 112 and a clock input terminal 113, respectively.

  The output side of the first count circuit 104 is connected to the first shift register 105, and the output side of the first shift register 105 is connected to the input side of the first register 106. The first counter circuit 107 is formed by the first count circuit 104, the first shift register 105, and the first register 106. Similarly, the output side of the second count circuit 108 is connected to the second shift register 109, and the output side of the second shift register 109 is connected to the input side of the second register 110. The second counter circuit 107 is formed by the second count circuit 108, the second shift register 109, and the second register 110. Here, the control inputs of the first register 106 and the second register 109 are connected to the edge detection circuit 110, respectively.

  The output sides of the first register 106 and the second register 110 are connected to the first input side and the second input side of the adder 114, respectively. The output side of the adder 114 is connected to the input side of the third register 115, and the output side of the third register 115 is connected to the input side of the first D / A converter circuit 116. The output side of the first D / A converter circuit 116 is connected to a non-inverting input terminal (+) of an error amplifier 119 having a resistor 118 connected to the ground. Here, it is assumed that the first D / A converter circuit 116 receives a constant current generated in the current source 117 as a drive current.

  The output side of the error amplifier 119 is connected to the gate of the control transistor 121, and the source of the control transistor 121 is connected to the output side of the reference current source 120. The drain of the control transistor 121 is connected to the ground via the resistor 122, and the drain is further connected to the inverting input terminal (−) of the error amplifier 118.

The output side of the first register 106 is also connected to the input side of the second D / A converter circuit 123, and the output side of the second D / A converter circuit 123 is connected to the output terminal 102. Here, the second D / A converter circuit 123 receives the current generated in the variable current source 124 as a drive current, and the current generated in the variable current source 124 includes the reference current source 120 and the control transistor. _Suppose that it changes according to the current signal S _PT generated at the contact 121.

In the signal conversion circuit having the above configuration, the DC voltage signal S _DC is obtained from the PWM signal S _PWM as follows.
The PWM signal S _PWM supplied to the input terminal 101 is adjusted in waveform by the waveform shaping circuit 103 and then supplied to the first count circuit 104, the second count circuit 108, and the edge detection circuit 112. The edge detection circuit 112 monitors the level change of the pulse of the supplied PWM signal S _PWM , and generates a predetermined signal S _E when the pulse rises and falls. The signal S _E is supplied from the edge detection circuit 112 to the first count circuit 104, the second count circuit 108, the first register 106, and the second register 110, respectively.

When the signal S _E is in a state indicating the rising _edge of the pulse of the PWM signal S _PWM , the first count circuit 104 detects the pulse of the clock signal S _CLK supplied from the terminal 113 (for example, from low level to high level). Change detection). The first shift register 105 receives a signal based on detection of a pulse generated in the first count circuit 104 and generates an n-bit data signal corresponding to the number of detected pulses. Then, the first count circuit 104 and the first shift register 105 detect the pulse of the clock signal _SCLK until the signal S _E indicates the falling edge of the pulse of the PWM signal S _PWM , and set the number of pulses. Continue to generate data signals based on it.

The n-bit data signal held in the first shift register 105 is sequentially sent to the first register 106 at an appropriate timing and stored therein. Here, the first register 106 receives the signal S _E from the edge detection circuit 112 as a latch signal, and the pulse of the PWM signal S _PWM is high during the period when the first count circuit 104 detects the pulse. During the period that is the level, it operates so as to maintain the output of the previous data without reading new data. As a result, the n-bit data signal stored in and output from the first register 106 is the number of pulses of the clock signal S _CLK detected during the period when the pulse of the latest PWM signal S _PWM is at a high level. It turns out that.

On the other hand, when the signal S _E indicates a state in which the pulse of the PWM signal S _PWM falls, the second count circuit 108 starts detecting the pulse of the clock signal S _CLK supplied from the terminal 113. The second shift register 109 receives a signal based on pulse detection generated in the second count circuit 108 and generates an n-bit data signal corresponding to the number of detected pulses. Then, the second count circuit 108 and the second shift register 109 detect the pulse of the clock signal S _CLK until the signal S _E indicates a rising _edge of the pulse of the PWM signal S _PWM , and based on the number of pulses. Continue to generate data signals.

The n-bit data signal held in the second shift register 109 is sequentially sent to the second register 110 at an appropriate timing and stored therein. Here, the second register 110 receives the signal S _E from the edge detection circuit 112 as a latch signal, and during the period when the second count circuit 108 detects a pulse, that is, the pulse of the PWM signal S _PWM is low. During the period that is the level, it operates so as to maintain the output of the previous data without reading new data. As a result, the n-bit data signal stored in and output from the second register 110 is the number of pulses of the clock signal S _CLK detected during the period when the pulse of the most recent PWM signal S _PWM is at low level. It turns out that.

The data stored in each of the first register 106 and the second register 110 is appropriately sent to the adder 114 and added. The data obtained by this addition is sent to the third register 115 and stored therein. As a result, the data stored in and output from the third register 115 is the number of pulses of the clock signal S _CLK detected during a period corresponding to approximately one cycle of the PWM signal S _PWM .

The data stored in the third register 115 is appropriately sent to the first D / A converter circuit 116, and a voltage signal S _VOL having a voltage value (analog amount) corresponding to the number of clocks (digital amount) in one cycle. Is converted to This voltage signal S _VOL is supplied as a reference voltage to the non-inverting input terminal (+) of the error amplifier 119. Here, the error amplifier 119, the control transistor 121, and the resistor 122 constitute a current source circuit, and the current flowing through the control transistor 121 is controlled to a magnitude corresponding to the period of one cycle of the PWM signal _SPWM . On the other hand, since the control transistor 121 is configured to be supplied with a constant current from the reference current source 120, a period of one cycle of the PWM signal S _PWM is present at the contact point between the reference current source 120 and the control transistor 121. A current signal _SPT corresponding to the cycle is generated, which decreases as the length increases and increases as the length decreases.

Data stored in the first register 106 is also sent to the second D / A converter circuit 123, a clock number of high-level period signal S _DC voltage value corresponding to the (digital quantity) (analog quantity) Converted. Here, the second D / A converter circuit 123 is configured to be driven by a variable current from the current source 124. Further, the drive current supplied from the current source 124 to the second D / A converter circuit 123 is controlled to a magnitude according to the previous current signal _SPT . Therefore, the correction according to the magnitude of the current signal S _PT added to the DC voltage signal S _DC, the voltage value of the voltage signal S _DC is proportional with the positive coefficients to the high-level period of the PWM signal S _PWM, PWM The value is proportional to the cycle of the signal S _{PWM by} a negative coefficient.

Incidentally, as shown in FIG. 2, even if the PWM signal S _PWM has the same duty ratio, if the period (= frequency) is different, the number of pulses of the clock signal S _CLK counted in the high level period also varies. Come different. (The height of CL1, CL2, and CL3 in FIG. 2 indicates the number of pulses.) Here, the number of pulses counted when the period is T1 is CL1, and the number of pulses counted when the period is T2 is CL2. If the number of pulses counted when the period is T3 is CL3, CL1 / T1 = CL2 / T2 = CL3 / T3 when the duty ratio of each PWM signal is “same” at 80%. This means that T1: T2 = CL1: CL2, T2: T3 = CL2: CL3, and between signals having the same duty ratio, the period and the number of pulses in the high level period are proportional to each other. Yes. In addition, since the number of pulses increases as the period becomes longer, the coefficient becomes positive.

On the other hand, the second D / A converter circuit 123 shown in (b) of FIG. 1, the configuration to generate a DC voltage signal S _DC in accordance with the number of pulses counted in the high level period of the PWM signal S _PWM. This DC voltage signal S _DC has a magnitude that is faithful to the number of detected pulses if no correction is made during the generation process. For this reason, even if the duty ratio is the same, the pure DC voltage signal S _DC that has not been corrected becomes different in magnitude if the period is different. Specifically, as indicated by the line (i) on the left side of FIG. 3, the signals also change to S _DC1 , S _DC2 , and S _DC3 corresponding to the periods T1, T2, and T3. Between signals with the same duty ratio, the number of pulses in the period and the high level period is proportional to a positive coefficient. Therefore, the periods T1, T2, and T3 and the signals S _DC1 , S _DC2 , and S _DC3 are also proportional to a positive coefficient. Is a straight line that rises to the right (positive slope).

Here, as shown by the line (ii) in FIG. 3, the signal S changes with a negative slope with respect to the change of the period, that is, with a signal or circuit operation that is proportional to the negative coefficient with respect to the period. When properly corrected _DC1, S _DC2, S _DC3, as shown in FIG. 3 right line (iii), will direct voltage signal S _DC of the same size with respect to the PWM signal of the same duty ratio can be obtained with I can expect. Therefore, the signal conversion circuit shown in FIG. 1, (1) the period of the PWM signal S _PWM becomes small as long to generate larger current signal S _PT and period is short, (2) the in that the current signal S _PT The output gain of the second D / A converter circuit 123 is controlled.

According to such a configuration, the DC voltage signal S _DC is corrected according to the current signal S _PT , that is, the period of the PWM signal S _PWM . That is, the magnitude of the DC voltage signal S _DC is proportional with positive coefficients to the high-level period of the PWM signal S _PWM, the magnitude proportional with a negative coefficient to the cycle of the PWM signal S _PWM. As a result, the signal conversion circuit of FIG. 1 can obtain a DC voltage signal S _DC having the same magnitude as the PWM signal S _PWM having the same duty ratio even when the frequency of the PWM signal S _PWM changes. Yes.

Note that the second D / A converter circuit 123 of FIG. 1 changes the gain by a variable drive current from the current source 124. However, the second D / A converter circuit 123 is a circuit having the same fixed gain as that of the first D / A converter circuit 116, and a gain variable type amplifier circuit is newly provided on the output side, and a current signal is supplied to the amplifier circuit. S _PT may be supplied. A variable conductance circuit using a Gilbert cell is newly provided on the output side of the second D / A converter circuit 123, and one of two currents (I ₁ / I ₀ ) that determines the gain is passed through the control transistor 119. You may make it change with.

  Each counter unit 107 and 111 in FIG. 1 is configured by a combination of a count circuit, a shift register, and a register. For example, if a binary n-bit digital counter is applied to the count circuit, the shift register or register Can be omitted. Further, in the embodiment of FIG. 1, the PWM signal and the edge detection signal are simultaneously supplied to each count circuit in order to set the operation start and operation end of the circuit or the timing of circuit initialization. However, the internal configuration of the count circuit may be modified so that all operations are performed by supplying only one of the signals. If the waveform distortion of the PWM signal supplied via the input terminal 101 is small, the waveform shaping circuit 103 may be omitted.

  The signal conversion circuit according to the present invention described above includes a step of measuring the number of pulses in a high level period and a low level period, a step of digitally processing the signal, and a step of generating a signal corresponding to the cycle. The method is characterized by combining a step of correcting a voltage signal corresponding to a high level period with the signal. According to the present invention, a capacitor having a large capacitance value and a resistance element having a large resistance value are not required, and the signal conversion circuit can be easily integrated. Further, even if the high-level and low-level voltage values of the PWM signal fluctuate, an additional effect is obtained that the DC output voltage is hardly affected.

The block diagram of the signal converter circuit by this invention. The figure explaining the change of the clock number of the high level period with respect to the period change of the PWM signal with the same duty ratio. The figure explaining the change of the DC voltage signal with respect to the period change of the PWM signal with the same duty ratio, and its correction method. The block diagram of the conventional signal converter circuit by RC low pass filter.

Explanation of symbols

101: input terminal 102: output terminal 104: first counter 105: first shift register 106: first register 107: first counter unit 108: second counter 109: second shift register 110: second Second register 111: Second counter unit 112: Edge detection circuit 113: Clock input terminal 114: Adder 115: Third register 116: First D / A converter circuit 119: Error amplifier 120: Reference current source 121 : Control transistor 123: second D / A converter circuit S _PWM : PWM signal S _E : edge detection signal S _VOL : voltage signal corresponding to the cycle (fourth signal)
S _PT : Current signal according to the period

Claims (6)

In a signal conversion circuit for obtaining an output signal having a voltage value corresponding to the duty ratio of the input signal by receiving a pulse width modulated input signal,
A first counter unit for generating a first signal corresponding to a high level period of the input signal;
A second counter unit for generating a second signal corresponding to a low level period of the input signal;
An adder that generates a third signal corresponding to a period of approximately one cycle of the input signal from the first signal and the second signal;
A first converter circuit for generating a fourth signal having a voltage value corresponding to the third signal;
A second converter circuit for generating a fifth signal having a voltage value corresponding to the first signal;
Comprising
The output signal is obtained by making the magnitude of the fifth signal proportional to a positive coefficient in the high level period of the input signal and proportional to a negative coefficient in the period of the input signal. Signal conversion circuit. The first signal, the second signal, and the third signal are each a digital signal having a predetermined number of bits, and the fourth signal and the fifth signal are analog signals. The signal conversion circuit according to claim 1, wherein: A current source circuit which receives the supply of the fourth signal and generates a current signal whose value decreases as the value of the fourth signal increases;
3. The signal conversion circuit according to claim 1, wherein the fifth signal is controlled to a magnitude proportional to the fourth signal by a negative coefficient by the current signal. The second converter circuit comprises a configuration for changing the magnitude of the fifth signal in accordance with the magnitude of the supplied drive current,
4. The signal conversion circuit according to claim 3, wherein the magnitude of the drive current is controlled by the current signal. The first converter circuit is driven with a constant drive current;
5. The signal conversion circuit according to claim 4, wherein the second converter circuit is driven with a variable drive current. In a signal conversion circuit for obtaining an output signal having a voltage value corresponding to the duty ratio of the input signal by receiving a pulse width modulated input signal,
A first counter unit for generating a first signal corresponding to a high level period of the input signal;
A second counter unit for generating a second signal corresponding to a low level period of the input signal;
An adder that generates a third signal corresponding to a period of approximately one cycle of the input signal from the first signal and the second signal;
A first converter circuit for generating a fourth signal having a voltage value corresponding to the third signal;
A second converter circuit for generating a fifth signal having a voltage value corresponding to the first signal;
Comprising
A signal conversion circuit, wherein the output signal is obtained by correcting the magnitude of the fifth signal with a current signal based on the fourth signal.

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