JP4884518B2 - Analog-to-digital converter - Google Patents

Description

  The present invention relates to a successive approximation analog-to-digital converter (SAR ADC), and more particularly to a charge-sharing SAR ADC.

  As an analog-digital converter (ADC) mounted on a microcomputer or system LSI, a successive approximation (SAR) type is often used from the viewpoint of miniaturization and high accuracy. A general SAR ADC uses a DA converter, compares the voltage of the analog input signal and the output voltage of the DA converter with a comparator, and determines the digital signal to be given to the DA converter in order from the high-order bit based on the comparison result. To do. In other words, in the SAR ADC using a DA converter, signal processing for calculating an approximate digital value is performed with a voltage. In a general SAR ADC, the operation speed is limited by the settling time of the output of the DA converter, so it is difficult to increase the speed. If an element having a large driving capability is used to increase the speed, there is a problem that power consumption increases. there were.

  In order to solve such problems, Non-Patent Documents 1 and 2 have proposed charge sharing SAR ADCs as SAR ADCs that can realize high-speed operation and low power consumption. In the charge sharing SAR ADC, signal processing for calculating an approximate digital value is performed with charges. The configuration and operation of the charge sharing SAR ADC will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of a charge sharing SAR ADC that converts the voltage of the analog input signal Vin into an n-bit AD converted digital signal and outputs the converted signal. As illustrated in FIG. 1, the charge sharing SAR ADC includes an input signal capacitor Cs, a plurality of reference capacitor circuits 11-1 to 11-n-1, a comparator 12, and a control circuit 13.

  The input signal capacitor Cs has one terminal (input terminal) connected to the input terminal of the analog input signal Vin via the switch SW1, and the other terminal (reference terminal) connected to the power source of the reference potential (here, GND). The

  The reference capacitor circuit 11-1 includes a reference capacitor C1, a switch SW11 that connects one terminal of the reference capacitor C1 to the power source of the reference voltage Vref, and a switch that connects the other terminal of the reference capacitor C1 to the power source of the reference potential GND. SW12, a switch SW13 that connects one terminal of the reference capacitor C1 to the input terminal of the input signal capacitor Cs, and a switch SW14 that connects the other terminal of the reference capacitor C1 to the reference terminal (here, GND) of the input signal capacitor Cs. A switch SW15 that connects the other terminal of the reference capacitor C1 to the input terminal of the input signal capacitor Cs, and a switch SW16 that connects one terminal of the reference capacitor C1 to the reference terminal (here, GND) of the input signal capacitor Cs. . With such a configuration, the reference capacitor C1 is charged to the reference voltage Vref by opening SW13 to SW16 and closing SW11 and SW12. Further, the reference capacitor C1 has SW11, SW12, SW15 and SW16 open and SW13 and SW14 closed so that one terminal is the input terminal of the input signal capacitor Cs and the other terminal is the input signal capacitor. The forward connection state connected to the reference terminal of Cs is established, SW11 to SW14 are opened, and SW15 and SW16 are closed, so that one terminal is the reference terminal of the input signal capacitor Cs and the other terminal is A reverse connection state is established, which is connected to the input terminal of the input signal capacitor Cs.

The other reference capacitance circuits 11-2 to 11-n-1 have the same configuration as the reference capacitance circuit 11-1, but the capacitance values of the reference capacitances C1 to Cn-1 are different. The capacitance values of the reference capacitors Cn-1 to C1 and the input signal capacitor Cs are set to 1: 2: 4... 2 ^n-2 : 2 ⁿ⁻¹ , that is, a ratio of powers of 2.

  The comparator 12 determines whether the voltage at the input terminal of the input signal capacitor Cs is higher or lower than the reference potential (GND).

  Based on the determination result of the comparator 12, the control circuit 13 selects the connection state of the reference capacitor circuits 11-1 to 11-n-1 so that the voltage at the input terminal of the input signal capacitor Cs approaches the reference potential GND. The reference capacitor circuits 11-1 to 11-n-1 when the input signal capacitors Cs are sequentially connected and all the reference capacitor circuits 11-1 to 11-n-1 are completely connected to the input signal capacitors Cs. A digital value corresponding to the voltage of the analog input signal is calculated from the connection state and the final determination result.

  2 to 4 are diagrams for explaining the operation of the charge sharing SAR ADC of FIG. Here, in order to simplify the description, a case where n = 3, that is, a case of 3 bits will be described as an example. Accordingly, two reference capacitance circuits 11-1 and 11-2 are provided, and the capacitance values of the reference capacitances C2, C1 and the input signal capacitance Cs are 1: 2: 4, and are represented by C, 2C, 4C. The analog input signal Vin that can be digitally converted by the charge sharing SAR ADC is in the range of + Vref to −Vref, and Vin outside this range is “111” or “000”.

  The operation of the charge sharing SAR ADC will be described with reference to FIGS.

  First, a sampling step is performed. In the sampling step, as shown in FIG. 2A, the analog input signal Vin is applied to the input signal capacitor Cs with the SW1 closed, and the reference capacitor circuits 11-1 and 11-2 have SW11 and SW12. Is closed, SW13 to SW16 are opened, and the reference voltage Vref is applied to the reference capacitors C1 and C2. Thereafter, SW1 is opened and SW11 and SW12 are opened. As a result, Qin = 4C × Vin is accumulated in the input signal capacitor Cs, and 2C × Vref and C × Vref are accumulated in the reference capacitors C1 and C2.

  In the first comparison step, as shown in FIG. 2B, the comparator 12 determines whether the voltage at the input terminal of the input signal capacitor Cs is higher or lower than GND.

  In the second comparison step, when the determination result of the first comparison step is “1”, as shown in FIG. 3A, the SW15 and SW16 of the reference capacitance circuit 11-1 are closed, and the reference capacitance C1 is set. One terminal is connected to the reference terminal of the input signal capacitor Cs, and the other terminal of the reference capacitor C1 is connected in a reverse connection state where it is connected to the input terminal of the input signal capacitor Cs. As a result, the total charge Qx = 4C × Vin−2C × Vref accumulated in the input signal capacitor Cs and the reference capacitor C1, and the voltage Vx = Qx / (4C + 2C) = (4 × Vin−2 × Vref) at the reference terminal. / 6. In this state, the comparator 12 performs comparison.

  When the determination result of the first comparison step is “0”, as shown in FIG. 3B, the SW13 and SW14 of the reference capacitor circuit 11-1 are closed, and one terminal of the reference capacitor C1 is connected. The other terminal of the reference capacitor C1 is connected to the input terminal of the input signal capacitor Cs in a forward connection state in which the other terminal of the reference capacitor C1 is connected to the reference terminal of the input signal capacitor Cs. As a result, the total charge accumulated in the input signal capacitor Cs and the reference capacitor C1 becomes Qx = 4C × Vin + 2C × Vref, and the voltage of the reference terminal Vx = Qx / (4C + 2C) = (4 × Vin + 2 × Vref) / 6. . In this state, the comparator 12 performs comparison.

  In the third comparison step, when the determination result of the second comparison step is “1”, as shown in FIG. 4A, the SW15 and SW16 of the reference capacitance circuit 11-2 are closed, and the reference capacitance C2 One terminal is connected to the reference terminal of the input signal capacitor Cs, and the other terminal of the reference capacitor C2 is connected in a reverse connection state where it is connected to the input terminal of the input signal capacitor Cs. Assuming that the total charge accumulated in the input signal capacitor Cs and the reference capacitor C1 when the second comparison step is performed is Qx2, Qx = Qx2−C × Vref is obtained by the reference capacitor C2, and the reference terminal voltage Vx = Qx / (4C + 2C + C) = (Qx2-C × Vref) / 7. In this state, the comparator 12 performs comparison.

  When the determination result of the second comparison step is “0”, as shown in FIG. 4B, the SW13 and SW14 of the reference capacitor circuit 11-2 are closed, and one terminal of the reference capacitor C2 is connected. The other terminal of the reference capacitor C2 is connected to the input terminal of the input signal capacitor Cs in a forward connection state in which the other terminal of the reference capacitor C2 is connected to the reference terminal of the input signal capacitor Cs. As a result, Qx = Qx2 + C × Vref and the voltage Vx = Qx / (4C + 2C + C) = (Qx2 + C × Vref) / 7 at the reference terminal. In this state, the comparator 12 performs comparison.

  Here, a specific voltage value of Vin will be described as an example. FIG. 5 is a diagram for explaining an example of change in the voltage Vx at the input terminal when 0 (GND) <Vin <+ Vref / 4. In this case, the correct conversion result is that the digital conversion value is “100”. It is.

  In the first comparison step, as shown in FIG. 5A, the charge Qx = 4C × Vin accumulated in the input signal capacitor Cs, the reference terminal voltage Vx = Qx / 4C = Vin, and 0 ( Since (GND) <Vin <+ Vref / 4, the determination result is “1”.

  At the time of the second comparison step, as shown in FIG. 5B, Qx = 4C × Vin−2C × Vref, Vx = (4 × Vin−2 × Vref) / 6, and 0 (GND) <Vin Since <+ Vref / 4, the determination result is “0”.

  In the third comparison step, as shown in FIG. 5C, Qx = 4C × Vin−2C × Vref−C × Vref = (4 × Vin−3 × Vref) C, Vx = (4 × Vin− Since 3 × Vref) / 7 and 0 (GND) <Vin <+ Vref / 4, the determination result is “0”.

  As described above, the converted digital value becomes “100”.

In the charge sharing SAR ADC, the capacitance values of the reference capacitors Cn-1 to C1 and the input signal capacitor Cs are set to 1: 2: 4... 2 ^n-2 : 2 ⁿ⁻¹ , that is, a ratio of a power of 2. The A method of setting such a ratio to a power of 2 is called a binary algorithm, and is the most efficient method for converting to a digital value, and is generally used.

  Non-Patent Document 2 discloses that in charge sharing SAR ADC, in addition to a plurality of capacitances whose capacitance values are changed by a binary algorithm, an additional minimum weight capacitance is provided, and a low power consumption and high noise comparator is provided in the first half. Use a high power consumption and low noise comparator in the second half, and add an extra step to determine the minimum weight capacity at the end to further reduce power consumption and increase the high power used in the first half. It has been proposed to correct misjudgment of noise comparators.

  Non-Patent Documents 3 and 4 propose using a non-binary (redundant) algorithm to correct an incomplete settling error of the DA converter in the SAR ADC using the DA converter.

  Non-Patent Document 5 describes a non-binary (redundant) algorithm in a SAR ADC using a DA converter.

  None of Non-Patent Documents 3 to 5 describes the charge sharing SAR ADC.

J. Craninckx and G. Van der Plas, “A 65fJ / Conversion-Step 0-to-50MS / s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS”, ISSCC Dig. Tech. Papers, pp . 246-247, Feb. 2007 V.Giannini, P.Nuzzo, V.Chironi, A.Baschirotto, G.V.Plas, J.Craninckx, “An 820uW 9b 40MS / s Noise-Tolerant Dynamic-SARADC in 90nm Digital CMOS”, ISSCC (Feb. 2007) F.Kuttner “A 1.2V 10b 20MS / S Non-Binary Successive Approximation ADC in 0.13um CMOS” Tech. Digest of ISSCC (Feb. 2002) M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske “A 14b 40MS / s Redundant SAR ADC with 480MHz Clock in 0.13um CMOS” Tech. Digest of ISSCC (Feb. 2007) T.Ogawa, H.Kobayashi, M.Hotta, Y.Takahashi, H.San, N.Takai “SAR ADC Algorithm with Redundancy”, IEEE Asia Pacific Conference on Circuits and Systems, Macao, pp.268-271, Dec. 2008

  The comparator has an offset due to manufacturing variations. In a general SAR ADC using a DA converter, the offset of the comparator becomes an offset of the entire ADC, and only a level shift occurs, and there is no problem in the linearity of the ADC. On the other hand, in the signal processing by charges in the charge sharing SAR ADC, the offset of the comparator affects the input offset, so that the linearity of the ADC deteriorates. This problem is caused by an increase in the charge conversion offset because the input conversion offset of the comparator is a voltage, and a reference capacitor is added as the comparison step proceeds.

  FIG. 6 is a diagram illustrating a change in charge conversion offset in the 3-bit charge sharing SAR ADC described with reference to FIGS. 2 to 5. If the offset of the comparator is Voff, the charge conversion offset is 4C × Voff in the first comparison step, but the charge conversion offset changes to 6C × Voff in the second comparison step, 7C × Voff in the second comparison step, and so on. .

  In order to solve this problem, Non-Patent Documents 1 and 2 describe that a variable capacitor is provided inside the comparator and the offset is adjusted to be within 1/2 LSB.

  However, as described in Non-Patent Documents 1 and 2, in order to make the offset adjustment small, the circuit becomes complicated accordingly, and it is necessary to provide an offset adjustment process in the manufacturing process, and the cost increases accordingly. There is.

  An object of the present invention is to realize a charge sharing SAR ADC satisfying both high accuracy and high speed with a simple configuration.

  In order to solve the above problem, the charge sharing SAR (Successive Approximation Register) analog-digital converter (ADC) of the present invention applies a non-binary algorithm, and the capacitance value of the input signal capacitance and one or more reference capacitances is Set to be non-binary.

  That is, the charge sharing SAR analog-digital converter of the present invention has an input terminal to which an analog input signal is applied at the time of sampling and a reference terminal connected to a reference potential, and the analog input signal to be applied at the time of sampling. An input signal capacitor that holds a charge amount corresponding to the voltage of the reference voltage, and one or more reference capacitors that hold a charge amount corresponding to the voltage of the reference voltage applied during sampling, and two terminals of each reference capacitor are , One or more reference capacitors configured to be connectable to the input terminal and the reference terminal of the input signal capacity in either the forward connection state or the reverse connection state, and the voltage of the input terminal of the input signal capacity are: A comparator that determines whether the voltage is higher or lower than the reference potential, and one or more comparators so that the voltage at the input terminal of the input signal capacitor approaches the reference potential based on the determination result of the comparator. A control circuit that sequentially connects while selecting the connection state of the reference capacitor to the input signal capacitor and calculates a digital value corresponding to the voltage of the analog input signal from the result of combining the determination results of the comparators. The converter is characterized in that the input signal capacity and the capacity values of one or more reference capacitors are set in non-binary.

  It is desirable that the input signal capacity and the capacity values of one or more reference capacitors are all different.

  According to the present invention, since the redundant non-binary algorithm is applied, the number of reference capacitors and the number of comparison processes (steps) are slightly increased, but the allowable range of the offset variation of the comparator can be widened.

  According to the present invention, the accuracy of the charge-sharing SAR ADC capable of high-speed operation is improved, and the manufacturing yield can be improved.

FIG. 1 is a block diagram illustrating a configuration example of a general charge sharing SAR ADC. FIG. 2 is a diagram for explaining the conversion operation in the charge sharing SAR ADC. FIG. 3 is a diagram for explaining the conversion operation in the charge sharing SAR ADC. FIG. 4 is a diagram illustrating a conversion operation in the charge sharing SAR ADC. FIG. 5 is a diagram for explaining a comparison step and a determination result for a certain analog input signal value in the charge sharing SAR ADC. FIG. 6 is a diagram illustrating a change in charge conversion offset in the 3-bit charge sharing SAR ADC. FIG. 7 is a diagram illustrating a configuration of the charge sharing SAR ADC according to the embodiment of the present invention. FIG. 8 is a diagram illustrating a configuration of an input signal capacitor, a plurality of reference capacitors, and a comparator in the charge sharing SAR ADC of the embodiment. FIG. 9 is a diagram illustrating the capacitance value of the reference capacitor and the allowable error in the charge sharing SAR ADC of the embodiment.

  FIG. 7 is a diagram illustrating the configuration of the 10-bit charge sharing SAR ADC according to the embodiment of the present invention. FIG. 8 illustrates the input signal capacitance, the plurality of reference capacitors, and the comparator portion of the charge sharing SAR ADC according to the embodiment. It is a figure which shows a structure.

  As shown in FIG. 7, the charge sharing SAR ADC of the embodiment includes a comparison processing unit 21 having a C_array 22 and a comparator 12, a timing generation circuit 25, a C register 26, a shift register 27, a memory 28, and an adder. 29, a subtracter 30, a multiplexer 31, an A register 32, and an AD_out register 33. A portion excluding the comparison processing unit 21 forms a portion corresponding to the control circuit 13 of FIG.

  As illustrated in FIG. 8, the C_array 22 includes a switch SW1, an input signal capacitor Cs, and ten reference capacitor circuits 23-1,. As shown in FIG. 8, the configuration of each reference capacitance circuit is the same as that of the conventional charge sharing SAR ADC shown in FIG. However, the conventional n-bit charge sharing SAR ADC includes n−1, ie, 9 reference capacitance circuits in the case of 10 bits, whereas the 10-bit charge sharing SAR ADC of the present embodiment includes 10 pieces. FIG. 1 shows that the reference capacitances C1 to C10 and the input signal capacitances provided in the ten reference capacitance circuits are set according to a non-binary algorithm. Different from SAR ADC. Since ten reference capacitance circuits are provided, 11 comparison steps are performed. The switches SW11 and SW12 of the reference capacitance circuits 23-1 to 23-10 are controlled by a signal sample_CLK, and the switches SW13 to SW16 are controlled by a signal SR_out output from the shift register 27.

  FIG. 9 shows capacitance values Cu (k) of reference capacitors C1 to C10 (C (k) (k = 1 to 9)), allowable 1LSB equivalent offset error er (k), and error tolerance expressed in LSB. Indicates the value. The capacitance value Cu (k) is expressed as a relative value with the capacitance value of C10 being 1. The capacitance value of the input signal capacitor Cs is 512 times the capacitance value of C10, and when the capacitance value of C10 is C, it is 512C. The setting of the capacitance value Cu (k) of the reference capacitance shown in FIG. 9 will be described later.

  Returning to FIG. 7, the timing generation circuit 25 receives the reset signal Reset and the clock CLK, and generates timing signals sample_CLK, SR_Reset, SR_CLK, Comp, CR_CLK, address 1-11, AR_Reset, AR_CLK, AD_out_CLK for controlling each part. Output.

  Sample_CLK is a signal that is turned on during the sampling period. SW1 in FIG. 8 and switches SW11 and SW12 of each reference capacitance circuit are closed while sample_CLK is on, and are open during other periods.

  The comparator 12 outputs a comparison operation result according to the signal comp.

  The C register 26 latches the output of the comparator 12 according to the signal CR_CLK and outputs it as Comp_out.

  The shift register 27 resets the value held in accordance with the signal SR_Reset, then sequentially takes the output of the C register 26 in accordance with the signal SR_CLK, stores it in the register, and outputs it as the signal SR_out.

  The memory 28 is composed of a ROM and stores values corresponding to the capacitance values of the input signal capacitance Cs and the reference capacitances C1 to C10 in correspondence with the signal address1-10, and according to the input signal address1-10. Output the stored value. Further, the memory 28 stores values so as to output “0” to the adder 29 and “1” to the subtracter 30 in correspondence with the signal address11.

  The adder 29 adds the output value of the memory 28 to the output value of the A register 32 and outputs it to the multiplexer 31. The subtracter 30 subtracts the output value of the memory 28 from the output value of the A register 32. Output to.

  The multiplexer 31 selects and outputs one of the outputs from the adder 29 or the subtracter 30 based on the determination result output from the C register 26.

  The A register 32 outputs an initial value set in advance according to the signal AR_Reset, and thereafter latches the output of the multiplexer 31 according to the signal AR_CLK and outputs it to the adder 29 and the subtracter 30.

  The AD_out register 33 latches the output of the multiplexer 31 according to AD_out_CLK and outputs it as a digital conversion value.

  Next, the operation of the 10-bit charge sharing SAR ADC of the embodiment will be described. The charge sharing SAR ADC of the embodiment performs one sampling step and eleven comparison steps, and each step is performed in one clock. As described above, the conventional 10-bit charge sharing SAR ADC includes nine reference capacitance circuits, and performs one sampling step and ten comparison steps. The shared SAR ADC includes ten reference capacitance circuits 23-1 to 23-10 and performs 11 comparison steps. The ten reference capacitor circuits 23-1 to 23-10 include ten reference capacitors C 1 to C 10, and the capacitance values of the reference capacitors C 1 to C 10 and the input signal capacitor Cs are as shown in FIG. Weighted according to non-binary algorithm.

  First, a sampling step is performed according to the signal Reset. In the sampling step, similarly to the conventional example, SW1 is closed and the analog input signal Vin is applied to the input signal capacitor Cs, and in the reference capacitor circuits 23-1 to 23-10, SW11 and SW12 are closed. SW13 to SW16 are opened, and the reference voltage Vref is applied to the reference capacitors C1 to C10. Thereafter, SW1 is opened and SW11 and SW12 are opened. Thereby, charges of Qin = 512C × Vin are accumulated in the input signal capacitor Cs, and Cu (k) × Vref (k = 1-10) is accumulated in the reference capacitors C1 to C10. Further, the A register 32 is set to output an initial value 512, that is, an intermediate value of a 10-bit digital value.

  In the first comparison step, the comparator 12 determines whether the voltage at the input terminal of the input signal capacitor Cs is higher or lower than GND. At this time, the memory 28 outputs Cu (1) = 237 of C1 stored at the first address, and the adder 29 subtracts the value 749 obtained by adding 237 to the initial value 512 output from the A register 32. The unit 30 outputs a value 275 obtained by subtracting 237 from the initial value 512 output from the A register 32. The multiplexer 31 selects the value 749 output from the adder 29 when the determination result is “high (1)”, and selects the value 275 output from the subtractor 30 when the determination result is “low (0)”. The A register 32 latches and outputs the value output from the multiplexer 31.

  In the second comparison step, when the determination result of the first comparison step is “1”, SW15 and SW16 of the reference capacitor circuit 23-1 are closed, and one terminal of the reference capacitor C1 is a reference terminal of the input signal capacitor Cs. Are connected in a reverse connection state in which the other terminal of the reference capacitor C1 is connected to the input terminal of the input signal capacitor Cs. As a result, the total charge accumulated in the input signal capacitor Cs and the reference capacitor C1 is Qx = 512C × Vin−237C × Vref, and the voltage Vx = Qx / (512C + 237C) = (512 × Vin−237 × Vref) at the reference terminal. / 749. In this state, the comparator 12 performs comparison.

  When the determination result of the first comparison step is “0”, SW13 and SW14 of the reference capacitor circuit 23-1 are closed, and one terminal of the reference capacitor C1 is connected to the input terminal of the input signal capacitor Cs. The other terminal of C1 is connected in a forward connection state where it is connected to the reference terminal of the input signal capacitor Cs. As a result, the total charge accumulated in the input signal capacitor Cs and the reference capacitor C1 becomes Qx = 512C × Vin + 237C × Vref, and the voltage Vx = Qx / (512C + 237C) = (512 × Vin + 237 × Vref) / 749 of the reference terminal. . In this state, the comparator 12 performs comparison.

  At this time, the memory 28 outputs Cu (2) = 127 of C2 stored at the second address, and the adder 29 adds 127 to the value (749 or 275) output from the A register 32 ( 876 or 402), the subtractor 30 outputs a value (622 or 148) obtained by subtracting 127 from the value (749 or 275) output from the A register 32, respectively. The multiplexer 31 outputs the value (876 or 402) output from the adder 29 when the determination result is “high (1)”, and outputs the value (output from the subtractor 30 when the determination result is “low (0)”). 622 or 148) is selected, and the A register 32 latches and outputs the value output from the multiplexer 31.

  Hereinafter, in the third comparison step to the eleventh comparison step, the reference capacitors C2 to C10 are connected to the input capacitor Cs according to the determination result of the previous step, and Cu (3) to Cu output from the memory 28 according to the step. (10) is repeatedly added or subtracted to the value held in the A register 32 in the previous comparison step, and a digital conversion value is generated.

  In the final eleventh comparison step, the memory 28 outputs “0” to the adder 29 and “1” to the subtractor 30, and the adder 29 outputs the first comparison step output from the A register 32. The comparison level is output as it is, and the subtracter 30 outputs a value obtained by subtracting 1 from the comparison level of the eleventh comparison step. The multiplexer 31 selects and outputs the adder 29 or the subtracter 30 according to the comparison result of the eleventh comparison step, and the AD_out register 33 latches the output of the multiplexer 31 according to AD_out_CLK and outputs it as an AD conversion value To do.

  This completes the AD conversion process.

  Next, a method for setting the capacitance values of the reference capacitors C1 to C10 will be generalized and described.

First, an error occurring in the N-bit charge sharing SAR ADC is estimated. Consider an N-bit M-step SAR ADC. When the total value of the capacities at the k-th step is C _sum (k), it can be expressed as follows.

If the input conversion offset of the comparator is V _os , the charge conversion offset O _{os at the} k-th step can be expressed as follows.

  In the non-binary redundancy algorithm, an error is considered based on the final step. Therefore, the charge error Qer (k) due to the k-th offset is as follows.

If the full scale of the input charge and _{Q FS,} the offset error er of 1LSB terms (k) is as follows.

  Design an algorithm that allows this.

The offset Q _os (M) of the final comparison value is the offset of the entire ADC. 1LSB-converted ADC offset _{D os} is as follows.

If there is an offset across the ADC, output saturation occurs with respect to the end input. This output saturation can be eliminated by providing an overrange to the redundancy algorithm and designing the output gradation to be 2 ^N + 2 * D _os .

FIG. 9 shows an example in the case of Vin = −1V to + 1V, Vref = 1V, Cs = 512C, and V _os = 55 mV in 10 bits and 11 steps.

  Although the embodiments have been described above, the described embodiments are for explaining the invention, and those skilled in the art can easily understand that there can be various modifications within the scope of the claims.

  The present invention is applicable to a charge sharing successive approximation type AD converter circuit.

12 Comparator 21 Comparison Processing Unit 22 C_array
23-1 to 23-10 Reference capacity circuit 25 Timing generation circuit 26 C register 27 Shift register 28 Memory 29 Adder 29
30 Subtractor 31 Multiplexer 31
32 A register 33 AD_out register 33

Claims (2)

An input signal capacitor having an input terminal to which an analog input signal is applied at the time of sampling and a reference terminal connected to a reference potential, and holding a charge amount corresponding to the voltage of the analog input signal applied at the time of sampling;
One or more reference capacitors holding a charge amount corresponding to the voltage of the reference voltage applied at the time of sampling, and two terminals of each reference capacitor are connected to the input terminal and the reference terminal of the input signal capacitor, One or more reference capacitors configured to be connectable in either a forward connection state or a reverse connection state;
A comparator for determining whether a voltage at the input terminal of the input signal capacity is higher or lower than the reference potential;
Based on the determination result of the comparator, sequentially connect while selecting the connection state of the one or more reference capacitors with the input signal capacitor so that the voltage at the input terminal of the input signal capacitor approaches the reference potential And a control circuit that calculates a digital value corresponding to the voltage of the analog input signal from the result of combining the determination results of the comparator, and an analog-digital converter comprising:
The analog-digital converter characterized in that the input signal capacity and the capacity value of the one or more reference capacitors are set in non-binary.   The analog-to-digital converter according to claim 1, wherein the input signal capacitance and the capacitance value of the one or more reference capacitors are all different.

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