JP4880958B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4880958B2 JP4880958B2 JP2005270773A JP2005270773A JP4880958B2 JP 4880958 B2 JP4880958 B2 JP 4880958B2 JP 2005270773 A JP2005270773 A JP 2005270773A JP 2005270773 A JP2005270773 A JP 2005270773A JP 4880958 B2 JP4880958 B2 JP 4880958B2
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- 239000004065 semiconductor Substances 0.000 title claims description 73
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 229910021332 silicide Inorganic materials 0.000 claims description 110
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 108
- 238000000137 annealing Methods 0.000 claims description 37
- 238000009792 diffusion process Methods 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 12
- 239000000203 mixture Substances 0.000 claims description 9
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical group [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims 2
- 229910052697 platinum Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 239000012535 impurity Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 4
- 229910019001 CoSi Inorganic materials 0.000 description 3
- 229910008484 TiSi Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- SWXQKHHHCFXQJF-UHFFFAOYSA-N azane;hydrogen peroxide Chemical compound [NH4+].[O-]O SWXQKHHHCFXQJF-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Description
前記第1のゲート電極を挟んで前記半導体基板中に形成された第1の拡散層と、
前記第1の拡散層に形成され、少なくとも1つの金属を含む金属シリサイドから構成された引っ張り応力を内在する第1の導電体層とを具備するnMOSFETと、
前記半導体基板上に絶縁膜を介して形成された第2のゲート電極と、
前記第2のゲート電極を挟んで前記半導体基板中に形成された第2の拡散層と、
前記第2の拡散層に形成され、前記少なくとも1つの金属を含む金属シリサイドから構成され、前記少なくとも1つの金属とシリコンとの組成比が前記第1の導電体層の組成比と同じである、圧縮応力を内在する第2の導電体層とを具備するpMOSFETと、
を具備する。
Claims (5)
- 半導体基板上に絶縁膜を介して形成された第1のゲート電極と、
前記第1のゲート電極を挟んで前記半導体基板中に形成された第1の拡散層と、
前記第1の拡散層に形成され、少なくとも1つの金属を含む金属シリサイドから構成された引っ張り応力を内在する第1の導電体層とを具備するnMOSFETと、
前記半導体基板上に絶縁膜を介して形成された第2のゲート電極と、
前記第2のゲート電極を挟んで前記半導体基板中に形成された第2の拡散層と、
前記第2の拡散層に形成され、前記少なくとも1つの金属を含む金属シリサイドから構成され、前記少なくとも1つの金属とシリコンとの組成比が前記第1の導電体層の組成比と同じである、圧縮応力を内在する第2の導電体層とを具備するpMOSFETと、
を具備することを特徴とする半導体装置。 - 前記少なくとも1つの金属は、ニッケル、コバルト、チタニウム、プラチナ、パラジウムあるいはエルビウムであることを特徴とする、請求項1に記載の半導体装置。
- 前記引っ張り及び圧縮の内部応力は、前記第1及び第2の導電体層を形成する際に同時に形成されることを特徴とする、請求項1または2に記載の半導体装置。
- 半導体基板中にnMOSFET形成用の第1の半導体領域およびpMOSFET形成用の第2の半導体領域を形成する工程と、
前記第1の半導体領域上に絶縁膜を介して第1のゲート電極を形成し、前記第2の半導体領域上に絶縁膜を介して第2のゲート電極を形成する工程と、
前記第1のゲート電極を挟む前記半導体基板中に第1の拡散層を形成し、前記第2のゲート電極を挟む前記半導体基板中に第2の拡散層を形成する工程と、
前記第1及び第2の拡散層に接触させて金属材料を堆積する工程と、
第1のアニールにより前記金属材料と前記半導体基板とを反応させて前記第1及び第2の拡散層上に引っ張り応力を内在する第1相の第1及び第2の導電体層をそれぞれ形成する工程と、
前記第2の半導体領域上に圧縮応力を内在する応力制御膜を形成する工程と、
第2のアニールにより第1の半導体領域に前記引っ張り応力を内在する第2相の第1の導電体層を形成し、第2の半導体領域に前記圧縮応力を内在する第2相の第2の導電体層を形成する工程と、
を具備することを特徴とする、半導体装置の製造方法。 - 前記第1のアニールは、前記第2のアニールより、低温、短時間で行われることを特徴とする請求項4に記載の半導体装置の製造方法。
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JP2005270773A JP4880958B2 (ja) | 2005-09-16 | 2005-09-16 | 半導体装置及びその製造方法 |
US11/340,517 US7372108B2 (en) | 2005-09-16 | 2006-01-27 | Semiconductor device and manufacturing method thereof |
US12/081,439 US7741220B2 (en) | 2005-09-16 | 2008-04-16 | Semiconductor device and manufacturing method thereof |
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JP2005270773A JP4880958B2 (ja) | 2005-09-16 | 2005-09-16 | 半導体装置及びその製造方法 |
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JP2007081330A JP2007081330A (ja) | 2007-03-29 |
JP4880958B2 true JP4880958B2 (ja) | 2012-02-22 |
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Families Citing this family (24)
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JP4880958B2 (ja) * | 2005-09-16 | 2012-02-22 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7696019B2 (en) * | 2006-03-09 | 2010-04-13 | Infineon Technologies Ag | Semiconductor devices and methods of manufacturing thereof |
US20080142897A1 (en) * | 2006-12-19 | 2008-06-19 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system having strained transistor |
US20080217700A1 (en) * | 2007-03-11 | 2008-09-11 | Doris Bruce B | Mobility Enhanced FET Devices |
US7494937B2 (en) * | 2007-03-30 | 2009-02-24 | Tokyo Electron Limited | Strained metal silicon nitride films and method of forming |
US7713868B2 (en) * | 2007-03-30 | 2010-05-11 | Tokyo Electron Limited | Strained metal nitride films and method of forming |
US7531452B2 (en) * | 2007-03-30 | 2009-05-12 | Tokyo Electron Limited | Strained metal silicon nitride films and method of forming |
US8178446B2 (en) * | 2007-03-30 | 2012-05-15 | Tokyo Electron Limited | Strained metal nitride films and method of forming |
JP2009260004A (ja) * | 2008-04-16 | 2009-11-05 | Renesas Technology Corp | 半導体装置の製造方法 |
TW200910526A (en) * | 2007-07-03 | 2009-03-01 | Renesas Tech Corp | Method of manufacturing semiconductor device |
US7985652B2 (en) * | 2007-09-14 | 2011-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal stress memorization technology |
JP2009158621A (ja) * | 2007-12-25 | 2009-07-16 | Toshiba Corp | 半導体装置 |
KR101406226B1 (ko) * | 2008-05-07 | 2014-06-13 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
JP4770885B2 (ja) * | 2008-06-30 | 2011-09-14 | ソニー株式会社 | 半導体装置 |
DE102009006800B4 (de) * | 2009-01-30 | 2013-01-31 | Advanced Micro Devices, Inc. | Verfahren zur Herstellung von Transistoren und entsprechendes Halbleiterbauelement |
JP5569243B2 (ja) | 2010-08-09 | 2014-08-13 | ソニー株式会社 | 半導体装置及びその製造方法 |
JP4771024B2 (ja) * | 2011-04-15 | 2011-09-14 | ソニー株式会社 | 半導体装置の製造方法 |
JP5653519B2 (ja) | 2011-06-23 | 2015-01-14 | 三菱電機株式会社 | 半導体装置及び半導体装置の製造方法 |
FR2979482B1 (fr) * | 2011-08-25 | 2013-09-27 | Commissariat Energie Atomique | Procede de realisation d'un dispositif a transistors contraints a l'aide d'une couche externe |
FR2979480B1 (fr) * | 2011-08-25 | 2013-09-27 | Commissariat Energie Atomique | Procede de realisation d'un dispositif a transistors contraints par siliciuration des zones de source et de drain |
KR101876793B1 (ko) | 2012-02-27 | 2018-07-11 | 삼성전자주식회사 | 전계효과 트랜지스터 및 그 제조 방법 |
CN103311281B (zh) * | 2012-03-14 | 2016-03-30 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US20140048888A1 (en) * | 2012-08-17 | 2014-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained Structure of a Semiconductor Device |
JP6178065B2 (ja) * | 2012-10-09 | 2017-08-09 | 株式会社東芝 | 半導体装置 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003086708A (ja) * | 2000-12-08 | 2003-03-20 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2005057301A (ja) | 2000-12-08 | 2005-03-03 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2003060076A (ja) * | 2001-08-21 | 2003-02-28 | Nec Corp | 半導体装置及びその製造方法 |
JP4173672B2 (ja) * | 2002-03-19 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
KR100500451B1 (ko) * | 2003-06-16 | 2005-07-12 | 삼성전자주식회사 | 인장된 채널을 갖는 모스 트랜지스터를 구비하는반도체소자의 제조 방법 |
JP4860102B2 (ja) * | 2003-06-26 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR101025761B1 (ko) * | 2004-03-30 | 2011-04-04 | 삼성전자주식회사 | 디지탈 회로 및 아날로그 회로를 가지는 반도체 집적회로및 그 제조 방법 |
US7173312B2 (en) * | 2004-12-15 | 2007-02-06 | International Business Machines Corporation | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
US20060163670A1 (en) * | 2005-01-27 | 2006-07-27 | International Business Machines Corporation | Dual silicide process to improve device performance |
US7224033B2 (en) * | 2005-02-15 | 2007-05-29 | International Business Machines Corporation | Structure and method for manufacturing strained FINFET |
DE102005030583B4 (de) * | 2005-06-30 | 2010-09-30 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung von Kontaktisolationsschichten und Silizidgebieten mit unterschiedlichen Eigenschaften eines Halbleiterbauelements und Halbleiterbauelement |
US20070018252A1 (en) * | 2005-07-21 | 2007-01-25 | International Business Machines Corporation | Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same |
US7470943B2 (en) * | 2005-08-22 | 2008-12-30 | International Business Machines Corporation | High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same |
JP4880958B2 (ja) * | 2005-09-16 | 2012-02-22 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7709317B2 (en) * | 2005-11-14 | 2010-05-04 | International Business Machines Corporation | Method to increase strain enhancement with spacerless FET and dual liner process |
US7504336B2 (en) * | 2006-05-19 | 2009-03-17 | International Business Machines Corporation | Methods for forming CMOS devices with intrinsically stressed metal silicide layers |
JP2008244059A (ja) * | 2007-03-27 | 2008-10-09 | Renesas Technology Corp | 半導体装置の製造方法 |
TW200910526A (en) * | 2007-07-03 | 2009-03-01 | Renesas Tech Corp | Method of manufacturing semiconductor device |
US8349732B2 (en) * | 2008-07-18 | 2013-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Implanted metal silicide for semiconductor device |
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JP2007081330A (ja) | 2007-03-29 |
US20070066001A1 (en) | 2007-03-22 |
US7372108B2 (en) | 2008-05-13 |
US20090227079A1 (en) | 2009-09-10 |
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